imx: mx6: correct enable_fec_anatop_clock

We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ba6cc75a7b21193e51f5d17e651c1a3a61afda1c..11efd12c9a7764770f1fbedab2cf47a66f9c4ef3 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
        if (freq < ENET_25MHZ || freq > ENET_125MHZ)
                return -EINVAL;
 
+       reg = readl(&anatop->pll_enet);
+
        if (fec_id == 0) {
                reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
                reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);