mx6: soc: Clear the LDO ramp values up prior to setting the LDO voltages
authorFabio Estevam <fabio.estevam@freescale.com>
Thu, 26 Dec 2013 16:51:31 +0000 (14:51 -0200)
committerStefano Babic <sbabic@denx.de>
Thu, 2 Jan 2014 16:16:50 +0000 (17:16 +0100)
Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
arch/arm/cpu/armv7/mx6/soc.c

index 2eee6e9a2db2a7c1730b01cc731ae5b6f55fba65..486b870312c179c789cfac42a0fb9db3bf5804e5 100644 (file)
@@ -93,6 +93,20 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr4);
 }
 
+static void clear_ldo_ramp(void)
+{
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       int reg;
+
+       /* ROM may modify LDO ramp up time according to fuse setting, so in
+        * order to be in the safe side we neeed to reset these settings to
+        * match the reset value: 0'b00
+        */
+       reg = readl(&anatop->ana_misc2);
+       reg &= ~(0x3f << 24);
+       writel(reg, &anatop->ana_misc2);
+}
+
 /*
  * Set the VDDSOC
  *
@@ -113,6 +127,8 @@ static void set_vddsoc(u32 mv)
        else
                val = (mv - 700) / 25;
 
+       clear_ldo_ramp();
+
        /*
         * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
         * and set them to the calculated value (0.7V + val * 0.25V)