arm: zynq: Add mini u-boot configuration for zynq

Add configuration files/dtses for mini u-boot configurations which runs
out of OCM.

ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE
0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE  0x40000
was hardcoded.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index debf5e3b430149d947f1331be377d75f6f4756a1..7517a5df5a37be04f1bda6789c79840039407740 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
 
 dtb-$(CONFIG_ARCH_ZYNQ) += \
        zynq-cc108.dtb \
+       zynq-cse-qspi-single.dtb \
        zynq-microzed.dtb \
        zynq-picozed.dtb \
        zynq-syzygy-hub.dtb \

diff --git a/arch/arm/dts/zynq-cse-qspi-single.dts b/arch/arm/dts/zynq-cse-qspi-single.dts
new file mode 100644 (file)
index 0000000..bc08303
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi-single.dts
@@ -0,0 +1,13 @@
+/*
+ * Xilinx CSE QSPI single DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include "zynq-cse-qspi.dtsi"
+
+&qspi {
+       spi-rx-bus-width = <4>;
+};

diff --git a/arch/arm/dts/zynq-cse-qspi.dtsi b/arch/arm/dts/zynq-cse-qspi.dtsi
new file mode 100644 (file)
index 0000000..1c3736f
--- /dev/null
+++ b/arch/arm/dts/zynq-cse-qspi.dtsi
@@ -0,0 +1,126 @@
+/*
+ * Xilinx CSE QSPI board DTS
+ *
+ * Copyright (C) 2015 - 2017 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+/dts-v1/;
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       model = "Zynq CSE QSPI Board";
+       compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
+
+       aliases {
+               spi0 = &qspi;
+               serial0 = &dcc;
+       };
+
+       memory@fffc0000 {
+               device_type = "memory";
+               reg = <0xFFFC0000 0x40000>;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       dcc: dcc {
+               compatible = "arm,dcc";
+               status = "disabled";
+               u-boot,dm-pre-reloc;
+       };
+
+       amba: amba {
+               u-boot,dm-pre-reloc;
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&intc>;
+               ranges;
+
+               intc: interrupt-controller@f8f01000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0xF8F01000 0x1000>,
+                             <0xF8F00100 0x100>;
+               };
+
+               qspi: spi@e000d000 {
+                       clock-names = "ref_clk", "pclk";
+                       clocks = <&clkc 10>, <&clkc 43>;
+                       compatible = "xlnx,zynq-qspi-1.0";
+                       status = "okay";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 19 4>;
+                       reg = <0xe000d000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       num-cs = <1>;
+                       flash@0 {
+                               compatible = "n25q128a11";
+                               reg = <0x0>;
+                               spi-tx-bus-width = <1>;
+                               spi-rx-bus-width = <4>;
+                               spi-max-frequency = <50000000>;
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               partition@qspi-fsbl-uboot {
+                                       label = "qspi-fsbl-uboot";
+                                       reg = <0x0 0x100000>;
+                               };
+                               partition@qspi-linux {
+                                       label = "qspi-linux";
+                                       reg = <0x100000 0x500000>;
+                               };
+                               partition@qspi-device-tree {
+                                       label = "qspi-device-tree";
+                                       reg = <0x600000 0x20000>;
+                               };
+                               partition@qspi-rootfs {
+                                       label = "qspi-rootfs";
+                                       reg = <0x620000 0x5E0000>;
+                               };
+                               partition@qspi-bitstream {
+                                       label = "qspi-bitstream";
+                                       reg = <0xC00000 0x400000>;
+                               };
+                       };
+               };
+
+               slcr: slcr@f8000000 {
+                       u-boot,dm-pre-reloc;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+                       reg = <0xF8000000 0x1000>;
+                       ranges;
+                       clkc: clkc@100 {
+                               #clock-cells = <1>;
+                               compatible = "xlnx,ps7-clkc";
+                               fclk-enable = <0xf>;
+                               u-boot,dm-pre-reloc;
+                               clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                               "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                               "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                               "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                               "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                               "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                               "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                               "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                               "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                               "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                               "dbg_trc", "dbg_apb";
+                               reg = <0x100 0x100>;
+                       };
+               };
+       };
+
+};
+
+&dcc {
+       status = "okay";
+};

diff --git a/board/xilinx/zynq/zynq-cse-qspi-single b/board/xilinx/zynq/zynq-cse-qspi-single
new file mode 120000 (symlink)
index 0000000..764d141
--- /dev/null
+++ b/board/xilinx/zynq/zynq-cse-qspi-single
@@ -0,0 +1 @@
+zynq-zc706
\ No newline at end of file

diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig
new file mode 100644 (file)
index 0000000..86c5d44
--- /dev/null
+++ b/configs/zynq_cse_qspi_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_ARCH_ZYNQ=y
+CONFIG_SYS_TEXT_BASE=0xFFFC0000
+# CONFIG_ZYNQ_DDRC_INIT is not set
+CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
+CONFIG_DEBUG_UART=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_BOOTDELAY=-1
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL=y
+CONFIG_SYS_PROMPT="Zynq> "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_SPL is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_CLK is not set
+# CONFIG_CMD_DM is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_OF_EMBED=y
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SPL_BLK is not set
+# CONFIG_ZYNQ_GPIO is not set
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DEBUG_UART_ARM_DCC=y
+CONFIG_DEBUG_UART_BASE=0x0
+CONFIG_DEBUG_UART_CLOCK=0
+CONFIG_ZYNQ_QSPI=y
+# CONFIG_EFI_LOADER is not set

diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h
new file mode 100644 (file)
index 0000000..dd65b52
--- /dev/null
+++ b/include/configs/zynq_cse.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2013 - 2017 Xilinx.
+ *
+ * Configuration settings for the Xilinx Zynq CSE board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_CSE_H
+#define __CONFIG_ZYNQ_CSE_H
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#include <configs/zynq-common.h>
+
+/* Undef unneeded configs */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_BOOTCOMMAND
+#undef CONFIG_ENV_SIZE
+#undef CONFIG_CMDLINE_EDITING
+#undef CONFIG_AUTO_COMPLETE
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
+#undef CONFIG_SYS_LONGHELP
+
+#undef CONFIG_SYS_CBSIZE
+#undef CONFIG_BOOTM_VXWORKS
+#undef CONFIG_BOOTM_LINUX
+
+#define CONFIG_SYS_CBSIZE      1024
+
+#define CONFIG_ENV_SIZE                400
+#undef CONFIG_SYS_INIT_RAM_ADDR
+#undef CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFFFDE000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000
+#undef CONFIG_SPL_BSS_START_ADDR
+#undef CONFIG_SPL_BSS_MAX_SIZE
+#define CONFIG_SPL_BSS_START_ADDR      0x20000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x8000
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN  0x1000
+
+#define CONFIG_SYS_SDRAM_BASE  0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE  0x40000
+
+#endif /* __CONFIG_ZYNQ_CSE_H */