mxc_i2c: specify i2c base address in config file
authorTroy Kisky <troy.kisky@boundarydevices.com>
Tue, 24 Apr 2012 17:33:25 +0000 (17:33 +0000)
committerHeiko Schocher <hs@denx.de>
Wed, 11 Jul 2012 08:54:29 +0000 (10:54 +0200)
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
drivers/i2c/mxc_i2c.c
include/configs/flea3.h
include/configs/imx31_phycore.h
include/configs/mx35pdk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h

index 6454acbd42c2cddd1db3b84963ebe988cd77cda2..7ddbbd627c1a3488ee1ec65d310c6979c8897765 100644 (file)
@@ -606,6 +606,13 @@ struct esdc_regs {
 #define UART4_BASE     0x43FB0000
 #define UART5_BASE     0x43FB4000
 
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET                26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET                28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET                30
+
 #define ESDCTL_SDE                     (1 << 31)
 #define ESDCTL_CMD_RW                  (0 << 28)
 #define ESDCTL_CMD_PRECHARGE           (1 << 28)
index e570ad1e36e965dbaf26990707758d594f374d36..314600621c8e0977a9ec994ba34c14b8da9fe472 100644 (file)
@@ -39,7 +39,7 @@
 #define MAX_BASE_ADDR           0x43F04000
 #define EVTMON_BASE_ADDR        0x43F08000
 #define CLKCTL_BASE_ADDR        0x43F0C000
-#define I2C_BASE_ADDR           0x43F80000
+#define I2C1_BASE_ADDR         0x43F80000
 #define I2C3_BASE_ADDR          0x43F84000
 #define ATA_BASE_ADDR           0x43F8C000
 #define UART1_BASE             0x43F90000
index c88ac7cf98b318e5c6706c1dbcd6febf4bce1d94..416ffeed00bc34dcde4cc40715ad61e37977a537 100644 (file)
@@ -59,27 +59,10 @@ struct mxc_i2c_regs {
 #define I2SR_IIF       (1 << 1)
 #define I2SR_RX_NO_AK  (1 << 0)
 
-#if defined(CONFIG_SYS_I2C_MX31_PORT1)
-#define I2C_BASE       0x43f80000
-#define I2C_CLK_OFFSET 26
-#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
-#define I2C_BASE       0x43f98000
-#define I2C_CLK_OFFSET 28
-#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
-#define I2C_BASE       0x43f84000
-#define I2C_CLK_OFFSET 30
-#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
-#define I2C_BASE        I2C1_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
-#define I2C_BASE        I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
-#define I2C_BASE       I2C_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
-#define I2C_BASE       I2C2_BASE_ADDR
-#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
-#define I2C_BASE       I2C3_BASE_ADDR
+#ifdef CONFIG_SYS_I2C_BASE
+#define I2C_BASE       CONFIG_SYS_I2C_BASE
 #else
-#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
+#error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
 #endif
 
 #define I2C_MAX_TIMEOUT                10000
@@ -114,7 +97,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
                (struct clock_control_regs *)CCM_BASE;
 
        /* start the required I2C clock */
-       writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
+       writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
                &sc_regs->cgr0);
 #endif
 
index 6c5fcac6c1d4484c328634e3d375eaecfbfad52a..e8e3c6a03d4ace3bfc39b3e1ef4efd58da346bda 100644 (file)
@@ -66,7 +66,7 @@
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_BASE            I2C3_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_SYS_I2C_SLAVE           0xfe
 #define CONFIG_MXC_SPI
index acbd6701c753aec3a4106855b98d43ea9ca6f2dc..a412cf61eefce91a814b1f3660e09bc0f254a1fe 100644 (file)
@@ -54,7 +54,8 @@
 
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX31_PORT2
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_CLK_OFFSET      I2C2_CLK_OFFSET
 #define CONFIG_SYS_I2C_SPEED           100000
 
 #define CONFIG_MXC_UART
index ebbd371165c56d30558a2489417a34179d05735a..f930ed0a671b07211b34872cc2055b3e5b5f3809 100644 (file)
@@ -57,7 +57,7 @@
  */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX35_PORT1
+#define CONFIG_SYS_I2C_BASE            I2C1_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_MXC_SPI
 #define CONFIG_MXC_GPIO
index ffc799cd7fe817a08a8bc8bffa2c51c515c4dbe6..0a928afc82c0d5a199e7307631f2d5e26b1ec6c3 100644 (file)
@@ -50,7 +50,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* MMC Configs */
index 8f2c03f1a039e3fc071601b48be53fed6d32a6ee..67def93f63f09c76580e1b6973ededf89841699d 100644 (file)
@@ -53,7 +53,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2       1
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* PMIC Configs */
index e71148dee60c8aae3922c592aa68cee885b21c94..61ecd02e4cdcfbb13b098e31174668e93d04249d 100644 (file)
@@ -89,7 +89,7 @@
 /* I2C Configs */
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT1
+#define CONFIG_SYS_I2C_BASE            I2C1_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED           100000
 
 /* PMIC Controller */
index 1df20faf6b42a35dc07fddc0607c36e642d16f29..760014fce508f26aa069585d393a5aae71a48e3c 100644 (file)
@@ -50,7 +50,7 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MXC
-#define CONFIG_SYS_I2C_MX53_PORT2
+#define CONFIG_SYS_I2C_BASE            I2C2_BASE_ADDR
 #define CONFIG_SYS_I2C_SPEED            100000
 
 /* MMC Configs */