net: dwc_eth_qos: Flush the RX descriptors on init
authorMarek Vasut <marex@denx.de>
Mon, 23 Mar 2020 01:09:01 +0000 (02:09 +0100)
committermarex <marex@desktop.lan>
Fri, 1 May 2020 10:35:21 +0000 (12:35 +0200)
Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
drivers/net/dwc_eth_qos.c

index e2fb690a1c26511d8f82ab38a3099a7318880a2b..e33f3045fea4a362f8118acb4278bc3633a78358 100644 (file)
@@ -1289,8 +1289,8 @@ static int eqos_start(struct udevice *dev)
                rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
                                             (i * EQOS_MAX_PACKET_SIZE));
                rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+               eqos->config->ops->eqos_flush_desc(rx_desc);
        }
-       eqos->config->ops->eqos_flush_desc(eqos->descs);
 
        writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
        writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);