socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_sockit.dtb \
- socfpga_cyclone5_socrates.dtb
+ socfpga_cyclone5_socrates.dtb \
+ socfpga_cyclone5_sr1500.dtb
+
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "SoCFPGA Cyclone V SR1500";
+ compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ aliases {
+ /*
+ * This allows the ethaddr uboot environmnet variable
+ * contents to be added to the gmac1 device tree blob.
+ */
+ ethernet0 = &gmac1;
+ };
+
+ memory@0 {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ phy-mode = "rgmii";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ speed-mode = <0>;
+};
+
+&i2c1 {
+ status = "okay";
+ speed-mode = <0>;
+};
+
+&mmc0 {
+ status = "okay";
+ bus-width = <8>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ flash0: n25q00@0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00", "spi-flash";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_SR1500
+ bool "SR1500 (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
+
config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "sr1500" if TARGET_SOCFPGA_SR1500
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
+ default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
endif
}
#endif
-#ifdef CONFIG_DWMMC
-/*
- * Initializes MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
- return socfpga_dwmmc_init(gd->fdt_blob);
-}
-#endif
-
struct {
const char *mode;
const char *name;
--- /dev/null
+SOCFPGA SR1500 BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/sr1500/
+F: include/configs/socfpga_sr1500.h
+F: configs/socfpga_sr1500_defconfig
--- /dev/null
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
--- /dev/null
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x000E0180,
+ 0x18060000,
+ 0x18000000,
+ 0x00018060,
+ 0x00020000,
+ 0x00004000,
+ 0x000700C0,
+ 0x1C030000,
+ 0x0C000000,
+ 0x00000070,
+ 0x0001C030,
+ 0x00002000,
+ 0x00018060,
+ 0x0E018000,
+ 0x06000000,
+ 0x00000038,
+ 0x0000E018,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x001C0300,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x000000E0,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x1C030000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x01800000,
+ 0x00000006,
+ 0x00001806,
+ 0x00000400,
+ 0x00000000,
+ 0x00C03000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00601806,
+ 0x00000000,
+ 0x80600000,
+ 0x80000601,
+ 0x00000601,
+ 0x00000100,
+ 0x00300C03,
+ 0xC0300C00,
+ 0xC0300000,
+ 0xC0000300,
+ 0x000C0300,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x000C0300,
+ 0x700C0000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x000700C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x200300C0,
+ 0x0C030000,
+ 0x0C000000,
+ 0x00000070,
+ 0x0001C030,
+ 0x00002000,
+ 0x10018060,
+ 0x0E018000,
+ 0x06000000,
+ 0x00010018,
+ 0x0000E018,
+ 0x00001000,
+ 0x0001C030,
+ 0x04000000,
+ 0x03000000,
+ 0x0000800C,
+ 0x00C0300C,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x0C420D80,
+ 0x0C3000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680618,
+ 0x45034071,
+ 0x0A281A01,
+ 0x806180D0,
+ 0x34071C06,
+ 0x01A034D0,
+ 0x180D0000,
+ 0x71C06806,
+ 0x01450340,
+ 0xD000001A,
+ 0x0680E380,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x20430000,
+ 0x0C003001,
+ 0x00C00481,
+ 0x00000FF0,
+ 0x4810C000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x90218000,
+ 0x86001800,
+ 0x00600240,
+ 0x80090218,
+ 0x24086001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x4810C000,
+ 0x43000C00,
+ 0x00300120,
+ 0xC004810C,
+ 0x12043000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000010,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0xC0680618,
+ 0x45034071,
+ 0x0A281A01,
+ 0x80E380D0,
+ 0x34071C06,
+ 0x01A00040,
+ 0x180D0002,
+ 0x71C06806,
+ 0x01450340,
+ 0xD00A281A,
+ 0x06806180,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x18000000,
+ 0x01800902,
+ 0x00240860,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xCB2CA3DD,
+ 0xF5D5551E,
+ 0x034AD348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x030C0680,
+ 0xDD59647A,
+ 0x1ECB2CA3,
+ 0x48F5D555,
+ 0x00035AD3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00808000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x86120800,
+ 0x00600240,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xCB2CA3DD,
+ 0xF5D9651E,
+ 0x035AB2C8,
+ 0x821A0041,
+ 0x0000D000,
+ 0x00000680,
+ 0xDD59647A,
+ 0x1ECB2CA3,
+ 0x48F5D965,
+ 0x00035AD3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x10000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820004,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00808000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x2043090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010000,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00202000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xCB2CA3D5,
+ 0xF6D9651E,
+ 0x035AB2C8,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xDD59647A,
+ 0x1ECB2CA3,
+ 0x48F5D965,
+ 0x00034AD3,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820004,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0xAA0D4000,
+ 0x01C3A800,
+ 0x00040000,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00800000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020000,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D400,
+ 0x00000000,
+ 0x0000090C,
+ 0x00001000,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x2A835000,
+ 0x0070EA00,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC0D5F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x04864000,
+ 0x69A47A01,
+ 0xCB2CA3D5,
+ 0xF6D9651E,
+ 0x034AD348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD559647A,
+ 0x1ECB2CA3,
+ 0x48F6D965,
+ 0x00034A92,
+ 0x00080000,
+ 0x00001000,
+ 0x00080000,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875001,
+ 0x00000000,
+ 0x00000010,
+ 0x0080C000,
+ 0x41000000,
+ 0x00000002,
+ 0x00820004,
+ 0x00489800,
+ 0x801A1A1A,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x80000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00000200,
+ 0x00000004,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00004000,
+ 0x00010000,
+ 0x40002080,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x00020000,
+ 0x08000000,
+ 0x00000008,
+ 0x00000020,
+ 0x00008000,
+ 0x20001040,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x20000001,
+ 0x00000080,
+ 0x00000001,
+ 0x00010000,
+ 0x04000000,
+ 0x00FF0000,
+ 0x00000000,
+ 0x00004000,
+ 0x00000800,
+ 0xC0000001,
+ 0x00041419,
+ 0x40000000,
+ 0x04000816,
+ 0x000D0000,
+ 0x00006800,
+ 0x00000340,
+ 0xD000001A,
+ 0x06800000,
+ 0x00340000,
+ 0x0001A000,
+ 0x00000D00,
+ 0x40000068,
+ 0x1A000003,
+ 0x00D00000,
+ 0x00068000,
+ 0x00003400,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x80000008,
+ 0x0000007F,
+ 0x20000000,
+ 0x00000000,
+ 0xE0000080,
+ 0x0000001F,
+ 0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 0, /* GENERALIO17 */
+ 0, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 0, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 0, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 0, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 0, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 0, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 0, /* GPLMUX40 */
+ 0, /* GPLMUX41 */
+ 0, /* GPLMUX42 */
+ 0, /* GPLMUX43 */
+ 0, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 0, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 0, /* GPLMUX53 */
+ 0, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 0, /* GPLMUX57 */
+ 0, /* GPLMUX58 */
+ 0, /* GPLMUX59 */
+ 0, /* GPLMUX60 */
+ 0, /* GPLMUX61 */
+ 0, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 12500000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x49
+#define RW_MGR_GUARANTEED_READ 0x4C
+#define RW_MGR_GUARANTEED_READ_CONT 0x54
+#define RW_MGR_GUARANTEED_WRITE 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7B
+#define RW_MGR_IDLE_LOOP2 0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0 0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x59
+#define RW_MGR_READ_B2B_WAIT1 0x61
+#define RW_MGR_READ_B2B_WAIT2 0x6B
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7D
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define TINIT_CNTR0_VAL 99
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 99
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+ 0x20700000,
+ 0x20780000,
+ 0x10080421,
+ 0x10080520,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080441,
+ 0x100804c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ int ret;
+
+ /* Reset the Marvell PHY 88E1510 */
+ ret = gpio_request(63, "PHY reset");
+ if (ret)
+ return ret;
+
+ gpio_direction_output(63, 0);
+ mdelay(1);
+ gpio_set_value(63, 1);
+ mdelay(10);
+
+ return 0;
+}
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_MMC=y
*/
#include <common.h>
-#include <malloc.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <dwmmc.h>
-#include <errno.h>
-#include <asm/arch/dwmmc.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/dwmmc.h>
#include <asm/arch/system_manager.h>
+#include <dm.h>
+#include <dwmmc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <linux/err.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(void *)SOCFPGA_CLKMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
-/* socfpga implmentation specific drver private data */
+/* socfpga implmentation specific driver private data */
struct dwmci_socfpga_priv_data {
- unsigned int drvsel;
- unsigned int smplsel;
+ struct dwmci_host host;
+ unsigned int drvsel;
+ unsigned int smplsel;
};
static void socfpga_dwmci_clksel(struct dwmci_host *host)
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}
-static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
+static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
/* FIXME: probe from DT eventually too/ */
const unsigned long clk = cm_get_mmc_controller_clk_hz();
- struct dwmci_host *host;
- struct dwmci_socfpga_priv_data *priv;
- fdt_addr_t reg_base;
- int bus_width, fifo_depth;
+ struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int fifo_depth;
if (clk == 0) {
- printf("DWMMC%d: MMC clock is zero!", idx);
- return -EINVAL;
- }
-
- /* Get the register address from the device node */
- reg_base = fdtdec_get_addr(blob, node, "reg");
- if (!reg_base) {
- printf("DWMMC%d: Can't get base address\n", idx);
+ printf("DWMMC: MMC clock is zero!");
return -EINVAL;
}
- /* Get the bus width from the device node */
- bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
- if (bus_width <= 0) {
- printf("DWMMC%d: Can't get bus-width\n", idx);
- return -EINVAL;
- }
-
- fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "fifo-depth", 0);
if (fifo_depth < 0) {
- printf("DWMMC%d: Can't get FIFO depth\n", idx);
+ printf("DWMMC: Can't get FIFO depth\n");
return -EINVAL;
}
- /* Allocate the host */
- host = calloc(1, sizeof(*host));
- if (!host)
- return -ENOMEM;
-
- /* Allocate the priv */
- priv = calloc(1, sizeof(*priv));
- if (!priv) {
- free(host);
- return -ENOMEM;
- }
-
- host->name = "SOCFPGA DWMMC";
- host->ioaddr = (void *)reg_base;
- host->buswidth = bus_width;
+ host->name = dev->name;
+ host->ioaddr = (void *)dev_get_addr(dev);
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "bus-width", 4);
host->clksel = socfpga_dwmci_clksel;
- host->dev_index = idx;
+
+ /*
+ * TODO(sjg@chromium.org): Remove the need for this hack.
+ * We only have one dwmmc block on gen5 SoCFPGA.
+ */
+ host->dev_index = 0;
/* Fixed clock divide by 4 which due to the SDMMC wrapper */
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
- priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
- priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
+ priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "drvsel", 3);
+ priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ "smplsel", 0);
host->priv = priv;
- return add_dwmci(host, host->bus_hz, 400000);
-}
-
-static int socfpga_dwmci_process_node(const void *blob, int nodes[],
- int count)
-{
- int i, node, ret;
-
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = socfpga_dwmci_of_probe(blob, node, i);
- if (ret) {
- printf("%s: failed to decode dev %d\n", __func__, i);
- return ret;
- }
- }
return 0;
}
-int socfpga_dwmmc_init(const void *blob)
+static int socfpga_dwmmc_probe(struct udevice *dev)
{
- int nodes[2]; /* Max. two controllers. */
- int ret, count;
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int ret;
- count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_ALTERA_SOCFPGA_DWMMC,
- nodes, ARRAY_SIZE(nodes));
+ ret = add_dwmci(host, host->bus_hz, 400000);
+ if (ret)
+ return ret;
- ret = socfpga_dwmci_process_node(blob, nodes, count);
+ upriv->mmc = host->mmc;
- return ret;
+ return 0;
}
+
+static const struct udevice_id socfpga_dwmmc_ids[] = {
+ { .compatible = "altr,socfpga-dw-mshc" },
+ { }
+};
+
+U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
+ .name = "socfpga_dwmmc",
+ .id = UCLASS_MMC,
+ .of_match = socfpga_dwmmc_ids,
+ .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
+ .probe = socfpga_dwmmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
+};
DECLARE_GLOBAL_DATA_PTR;
+/* The STATUS register */
+#define QUADSPI_SR_BP0 BIT(2)
+#define QUADSPI_SR_BP1 BIT(3)
+#define QUADSPI_SR_BP2 BIT(4)
+#define QUADSPI_SR_BP2_0 GENMASK(4, 2)
+#define QUADSPI_SR_BP3 BIT(6)
+#define QUADSPI_SR_TB BIT(5)
+
/*
* The QUADSPI_MEM_OP register is used to do memory protect and erase operations
*/
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
+static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
+ uint64_t *len);
+
void flash_print_info(flash_info_t *info)
{
+ struct mtd_info *mtd = info->mtd;
+ loff_t ofs;
+ u64 len;
+
printf("Altera QSPI flash Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
+ altera_qspi_get_locked_range(mtd, &ofs, &len);
+ printf(" %08lX +%lX", info->start[0], info->size);
+ if (len) {
+ printf(", protected %08llX +%llX",
+ info->start[0] + ofs, len);
+ }
+ putc('\n');
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
instr.len = mtd->erasesize * (s_last + 1 - s_first);
ret = mtd_erase(mtd, &instr);
if (ret)
- return ERR_NOT_ERASED;
+ return ERR_PROTECTED;
return 0;
}
ret = mtd_write(mtd, to, cnt, &retlen, src);
if (ret)
- return ERR_NOT_ERASED;
+ return ERR_PROTECTED;
return 0;
}
{
}
+static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
+ uint64_t *len)
+{
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_regs *regs = pdata->regs;
+ int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
+ int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
+ u32 stat = readl(®s->rd_status);
+ unsigned pow = ((stat & QUADSPI_SR_BP2_0) >> shift0) |
+ ((stat & QUADSPI_SR_BP3) >> shift3);
+
+ *ofs = 0;
+ *len = 0;
+ if (pow) {
+ *len = mtd->erasesize << (pow - 1);
+ if (*len > mtd->size)
+ *len = mtd->size;
+ if (!(stat & QUADSPI_SR_TB))
+ *ofs = mtd->size - *len;
+ }
+}
+
+static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_regs *regs = pdata->regs;
+ u32 sector_start, sector_end;
+ u32 num_sectors;
+ u32 mem_op;
+ u32 sr_bp;
+ u32 sr_tb;
+
+ num_sectors = mtd->size / mtd->erasesize;
+ sector_start = ofs / mtd->erasesize;
+ sector_end = (ofs + len) / mtd->erasesize;
+
+ if (sector_start >= num_sectors / 2) {
+ sr_bp = fls(num_sectors - 1 - sector_start) + 1;
+ sr_tb = 0;
+ } else if (sector_end < num_sectors / 2) {
+ sr_bp = fls(sector_end) + 1;
+ sr_tb = 1;
+ } else {
+ sr_bp = 15;
+ sr_tb = 0;
+ }
+
+ mem_op = (sr_tb << 12) | (sr_bp << 8);
+ mem_op |= QUADSPI_MEM_OP_SECTOR_PROTECT;
+ debug("lock %08x\n", mem_op);
+ writel(mem_op, ®s->mem_op);
+
+ return 0;
+}
+
+static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+ struct udevice *dev = mtd->dev;
+ struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
+ struct altera_qspi_regs *regs = pdata->regs;
+ u32 mem_op;
+
+ mem_op = QUADSPI_MEM_OP_SECTOR_PROTECT;
+ debug("unlock %08x\n", mem_op);
+ writel(mem_op, ®s->mem_op);
+
+ return 0;
+}
+
static int altera_qspi_probe(struct udevice *dev)
{
struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
mtd->_read = altera_qspi_read;
mtd->_write = altera_qspi_write;
mtd->_sync = altera_qspi_sync;
+ mtd->_lock = altera_qspi_lock;
+ mtd->_unlock = altera_qspi_unlock;
mtd->numeraseregions = 0;
mtd->erasesize = 0x10000;
if (add_mtd_device(mtd))
int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
{
struct dwc3 *dwc;
- struct device *dev;
+ struct device *dev = NULL;
u8 lpm_nyet_threshold;
u8 tx_de_emphasis;
u8 hird_threshold;
int dwc3_omap_uboot_init(struct dwc3_omap_device *omap_dev)
{
u32 reg;
- struct device *dev;
+ struct device *dev = NULL;
struct dwc3_omap *omap;
omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
---help---
Enables support for the on-chip EHCI controller on UniPhier SoCs.
+config USB_EHCI_GENERIC
+ bool "Support for generic EHCI USB controller"
+ depends on OF_CONTROL
+ depends on DM_USB
+ default n
+ ---help---
+ Enables support for generic EHCI controller.
+
endif
obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
endif
obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
+obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o
obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Alexey Brodkin <abrodkin@synopsys.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include "ehci.h"
+
+/*
+ * Even though here we don't explicitly use "struct ehci_ctrl"
+ * ehci_register() expects it to be the first thing that resides in
+ * device's private data.
+ */
+struct generic_ehci {
+ struct ehci_ctrl ctrl;
+};
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
+ struct ehci_hcor *hcor;
+
+ hcor = (struct ehci_hcor *)((uintptr_t)hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+ return ehci_deregister(dev);
+}
+
+static const struct udevice_id ehci_usb_ids[] = {
+ { .compatible = "generic-ehci" },
+ { }
+};
+
+U_BOOT_DRIVER(ehci_generic) = {
+ .name = "ehci_generic",
+ .id = UCLASS_USB,
+ .of_match = ehci_usb_ids,
+ .probe = ehci_usb_probe,
+ .remove = ehci_usb_remove,
+ .ops = &ehci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct generic_ehci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
{ }
};
-U_BOOT_DRIVER(usb_ehci) = {
+U_BOOT_DRIVER(ehci_sunxi) = {
.name = "ehci_sunxi",
.id = UCLASS_USB,
.of_match = ehci_usb_ids,
/* reset USB3 phy - if required */
dwc3_phy_reset(dwc3_reg);
+ mdelay(100);
+
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}
return 0;
}
-void usb_phy_reset(struct dwc3 *dwc3_reg)
-{
- /* Assert USB3 PHY reset */
- setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Assert USB2 PHY reset */
- setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-
- mdelay(200);
-
- /* Clear USB3 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
-
- /* Clear USB2 PHY reset */
- clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
-}
-
static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
{
int ret = 0;
static struct omap_xhci omap;
-inline int __board_usb_init(int index, enum usb_init_type init)
+__weak int __board_usb_init(int index, enum usb_init_type init)
{
return 0;
}
--- /dev/null
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * Zynq USB HOST xHCI Controller
+ *
+ * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
+ *
+ * This file was reused from Freescale USB xHCI
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm-generic/errno.h>
+#include <asm/arch-zynqmp/hardware.h>
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include "xhci.h"
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Default to the ZYNQMP XHCI defines */
+#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
+#define USB3_PHY_RX_POWERON BIT(14)
+#define USB3_PHY_TX_POWERON BIT(15)
+#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT 14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET BIT(17)
+#define USBOTGSS_DMADISABLE BIT(16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
+#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
+#define USBOTGSS_IDLEMODE_SMRT BIT(3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN BIT(1)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
+
+struct zynqmp_xhci {
+ struct xhci_hccr *hcd;
+ struct dwc3 *dwc3_reg;
+};
+
+static struct zynqmp_xhci zynqmp_xhci;
+
+unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST;
+
+static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
+{
+ int ret = 0;
+
+ ret = dwc3_core_init(zynqmp_xhci->dwc3_reg);
+ if (ret) {
+ debug("%s:failed to initialize core\n", __func__);
+ return ret;
+ }
+
+ /* We are hard-coding DWC3 core to Host Mode */
+ dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+ return ret;
+}
+
+int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
+{
+ struct zynqmp_xhci *ctx = &zynqmp_xhci;
+ int ret = 0;
+ uint32_t hclen;
+
+ if (index < 0 || index >= ARRAY_SIZE(ctr_addr))
+ return -EINVAL;
+
+ ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
+ ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET);
+
+ ret = board_usb_init(index, USB_INIT_HOST);
+ if (ret != 0) {
+ puts("Failed to initialize board for USB\n");
+ return ret;
+ }
+
+ ret = zynqmp_xhci_core_init(ctx);
+ if (ret < 0) {
+ puts("Failed to initialize xhci\n");
+ return ret;
+ }
+
+ *hccr = (struct xhci_hccr *)ctx->hcd;
+ hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase));
+ *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen);
+
+ debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n",
+ *hccr, *hcor, hclen);
+
+ return ret;
+}
+
+void xhci_hcd_stop(int index)
+{
+ /*
+ * Currently zynqmp socs do not support PHY shutdown from
+ * sw. But this support may be added in future socs.
+ */
+
+ return;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SR1500_H__
+#define __CONFIG_SOCFPGA_SR1500_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_HW_WATCHDOG
+
+/* U-Boot Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TIME
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+
+/* Ethernet on SoC (EMAC) */
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+/* The PHY is autodetected, so no MII PHY address is needed here */
+#define CONFIG_PHY_MARVELL
+#define PHY_ANEG_TIMEOUT 8000
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME sr1500
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* Enable SPI NOR flash reset, needed for SPI booting */
+#define CONFIG_SPI_N25Q256A_RESET
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+/* U-Boot payload is stored at offset 0x60000 */
+#undef CONFIG_SYS_SPI_U_BOOT_OFFS
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
+
+/* Environment setting for SPI flash */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE (16 * 1024)
+#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MODE SPI_MODE_3
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+
+#endif /* __CONFIG_SOCFPGA_SR1500_H__ */
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_XHCI_ZYNQMP
+
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_AHCI
+#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
+ ZYNQMP_USB1_XHCI_BASEADDR}
#include <configs/xilinx_zynqmp.h>
switch (soc) {
case SVR_T4240:
case SVR_T4160:
+ case SVR_T4080:
return IS_SVR_REV(svr, 2, 0);
case SVR_T1024:
case SVR_T1023:
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
int dwc3_core_init(struct dwc3 *dwc3_reg);
-void usb_phy_reset(struct dwc3 *dwc3_reg);
void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
#endif
#endif /* __DWC3_H_ */
projects / oweals / u-boot.git / commitdiff