edid: Set timings flags according to edid
authorJernej Skrabec <jernej.skrabec@siol.net>
Sat, 29 Apr 2017 12:43:35 +0000 (14:43 +0200)
committerAnatolij Gustschin <agust@denx.de>
Mon, 15 May 2017 18:28:12 +0000 (20:28 +0200)
Timing flags are never set, so they may contain garbage. Since some
drivers check them, video output may be broken on those drivers.

Initialize them to 0 and check for few common flags.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
common/edid.c

index e08e4209202e0ffa852ea75c2848ba0fc5a28238..ab7069fdcd6cf3449fe8e8726b17f3afa7c7710c 100644 (file)
@@ -85,6 +85,7 @@ static void decode_timing(u8 *buf, struct display_timing *timing)
        uint x_mm, y_mm;
        unsigned int ha, hbl, hso, hspw, hborder;
        unsigned int va, vbl, vso, vspw, vborder;
+       struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf;
 
        /* Edid contains pixel clock in terms of 10KHz */
        set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000);
@@ -111,6 +112,19 @@ static void decode_timing(u8 *buf, struct display_timing *timing)
        set_entry(&timing->vback_porch, vbl - vso - vspw);
        set_entry(&timing->vsync_len, vspw);
 
+       timing->flags = 0;
+       if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t))
+               timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+       else
+               timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+       if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t))
+               timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+       else
+               timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+
+       if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t))
+               timing->flags = DISPLAY_FLAGS_INTERLACED;
+
        debug("Detailed mode clock %u Hz, %d mm x %d mm\n"
              "               %04x %04x %04x %04x hborder %x\n"
              "               %04x %04x %04x %04x vborder %x\n",