Cleanup build problems (on Fedora Core x86_64 build host)
authorWolfgang Denk <wd@pollux.denx.de>
Wed, 3 Aug 2005 20:32:02 +0000 (22:32 +0200)
committerWolfgang Denk <wd@pollux.denx.de>
Wed, 3 Aug 2005 20:32:02 +0000 (22:32 +0200)
CHANGELOG
MAINTAINERS
Makefile
board/amcc/yellowstone/flash.c
board/amcc/yellowstone/yellowstone.c
common/environment.c
include/configs/Yukon8220.h [new file with mode: 0644]
tools/envcrc.c

index 343080c208edb176e88933e11b2484268c8ec382..6d3bb93b0ac8b44d14a8caba25f788a202d328b4 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Cleanup build problems on 64 bit build hosts
+
 * Update MAINTAINERS file
 
 * Patch by Stefan Roese, 01 Aug 2005:
index 0bcad8e128bf7a71eaec3c311ca27408bfb7f282..0fff4f608465afed38209c16b66fcedd76aedb54 100644 (file)
@@ -129,6 +129,34 @@ Thomas Frieden <ThomasF@hyperion-entertainment.com>
 
        AmigaOneG3SE            MPC7xx
 
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+
+       ADCIOP                  IOP480 (PPC401)
+       APC405                  PPC405GP
+       AR405                   PPC405GP
+       ASH405                  PPC405EP
+       CANBT                   PPC405CR
+       CPCI405                 PPC405GP
+       CPCI4052                PPC405GP
+       CPCI405AB               PPC405GP
+       CPCI405DT               PPC405GP
+       CPCI440                 PPC440GP
+       CPCIISER4               PPC405GP
+       DASA_SIM                IOP480 (PPC401)
+       DP405                   PPC405EP
+       DU405                   PPC405GP
+       G2000                   PPC405EP
+       HH405                   PPC405EP
+       HUB405                  PPC405EP
+       OCRTC                   PPC405GP
+       ORSG                    PPC405GP
+       PCI405                  PPC405GP
+       PLU405                  PPC405EP
+       PMC405                  PPC405GP
+       VOH405                  PPC405EP
+       VOM405                  PPC405EP
+       WUH405                  PPC405EP
+
 Frank Gottschling <fgottschling@eltec.de>
 
        MHPC                    MPC8xx
@@ -168,10 +196,6 @@ Sangmoon Kim <dogoil@etinsys.com>
 
        debris                  MPC8245
 
-Nye Liu <nyet@zumanetworks.com>
-
-       ZUMA                    MPC7xx_74xx
-
 Thomas Lange <thomas@corelatus.se>
 
        GTH                     MPC860
@@ -180,6 +204,21 @@ The LEOX team <team@leox.org>
 
        ELPT860                 MPC860T
 
+Nye Liu <nyet@zumanetworks.com>
+
+       ZUMA                    MPC7xx_74xx
+
+Jon Loeliger <jdl@freescale.com>
+
+       MPC8540ADS              MPC8540
+       MPC8560ADS              MPC8560
+       MPC8541CDS              MPC8541
+       MPC8555CDS              MPC8555
+
+Dan Malek <dan@embeddededge.com>
+
+       STxGP3                  MPC85xx
+
 Eran Man <eran@nbase.co.il>
 
        EVB64260_750CX          MPC750CX
@@ -194,6 +233,7 @@ Reinhard Meyer <r.meyer@emk-elektronik.de>
        TOP5200                 MPC5200
 
 Tolunay Orkun <torkun@nextio.com>
+
        csb272                  PPC405GP
        csb472                  PPC405GP
 
@@ -202,17 +242,6 @@ Keith Outwater <Keith_Outwater@mvis.com>
        GEN860T                 MPC860T
        GEN860T_SC              MPC860T
 
-Stefan Roese <sr@denx.de>
-
-       bamboo                  PPC440EP
-       bunbinga                PPC405EP
-       ebony                   PPC440GP
-       ocotea                  PPC440GX
-       sycamore                PPC405GPr
-       walnut                  PPC405GP
-       yellowstone             PPC440GR
-       yosemite                PPC440EP
-
 Frank Panno <fpanno@delphintech.com>
 
        ep8260                  MPC8260
@@ -234,33 +263,20 @@ Daniel Poirot <dan.poirot@windriver.com>
        sbc8240                 MPC8240
        sbc405                  PPC405GP
 
-Matthias Fuchs <matthias.fuchs@esd-electronics.com>
+Stefan Roese <sr@denx.de>
 
-       ADCIOP                  IOP480 (PPC401)
-       APC405                  PPC405GP
-       AR405                   PPC405GP
-       ASH405                  PPC405EP
-       CANBT                   PPC405CR
-       CPCI405                 PPC405GP
-       CPCI4052                PPC405GP
-       CPCI405AB               PPC405GP
-       CPCI405DT               PPC405GP
-       CPCI440                 PPC440GP
-       CPCIISER4               PPC405GP
-       DASA_SIM                IOP480 (PPC401)
-       DP405                   PPC405EP
-       DU405                   PPC405GP
-       G2000                   PPC405EP
-       HH405                   PPC405EP
-       HUB405                  PPC405EP
-       OCRTC                   PPC405GP
-       ORSG                    PPC405GP
-       PCI405                  PPC405GP
-       PLU405                  PPC405EP
-       PMC405                  PPC405GP
-       VOH405                  PPC405EP
-       VOM405                  PPC405EP
-       WUH405                  PPC405EP
+       bamboo                  PPC440EP
+       bunbinga                PPC405EP
+       ebony                   PPC440GP
+       ocotea                  PPC440GX
+       sycamore                PPC405GPr
+       walnut                  PPC405GP
+       yellowstone             PPC440GR
+       yosemite                PPC440EP
+
+Yusdi Santoso <yusdi_santoso@adaptec.com>
+
+       HIDDEN_DRAGON   MPC8241/MPC8245
 
 Travis Sawyer (travis.sawyer@sandburst.com>
 
@@ -297,21 +313,6 @@ John Zhan <zhanz@sinovee.com>
 
        svm_sc8xx               MPC8xx
 
-Jon Loeliger <jdl@freescale.com>
-
-       MPC8540ADS              MPC8540
-       MPC8560ADS              MPC8560
-       MPC8541CDS              MPC8541
-       MPC8555CDS              MPC8555
-
-Dan Malek <dan@embeddededge.com>
-
-       STxGP3                  MPC85xx
-
-Yusdi Santoso <yusdi_santoso@adaptec.com>
-
-       HIDDEN_DRAGON   MPC8241/MPC8245
-
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -346,6 +347,10 @@ Unknown / orphaned boards:
 #      Board                   CPU                                     #
 #########################################################################
 
+Rishi Bhattacharya <rishi@ti.com>
+
+       omap5912osk             ARM926EJS
+
 George G. Davis <gdavis@mvista.com>
 
        assabet                 SA1100
@@ -364,6 +369,11 @@ Marius Gr
        impa7                   ARM720T (EP7211)
        ep7312                  ARM720T (EP7312)
 
+Kshitij Gupta <kshitij@ti.com>
+
+       omap1510inn             ARM925T
+       omap1610inn             ARM926EJS
+
 Kyle Harris <kharris@nexus-tech.net>
 
        lubbock                 xscale
@@ -375,29 +385,13 @@ Gary Jennejohn <gj@denx.de>
        smdk2400                ARM920T
        trab                    ARM920T
 
-Prakash Kumar <prakash@embedx.com>
-
-       cerf250                 xscale
-
-Kshitij Gupta <kshitij@ti.com>
-
-       omap1510inn             ARM925T
-       omap1610inn             ARM926EJS
-
-Dave Peverley <dpeverley@mpc-data.co.uk>
-       omap730p2               ARM926EJS
-
 Nishant Kamat <nskamat@ti.com>
 
        omap1610h2              ARM926EJS
 
-Rishi Bhattacharya <rishi@ti.com>
-
-       omap5912osk             ARM926EJS
-
-Richard Woodruff <r-woodruff2@ti.com>
+Prakash Kumar <prakash@embedx.com>
 
-       omap2420h4              ARM1136EJS
+       cerf250                 xscale
 
 David Müller <d.mueller@elsoft.ch>
 
@@ -408,6 +402,10 @@ Rolf Offermanns <rof@sysgo.de>
 
        shannon                 SA1100
 
+Dave Peverley <dpeverley@mpc-data.co.uk>
+
+       omap730p2               ARM926EJS
+
 Robert Schwebel <r.schwebel@pengutronix.de>
 
        csb226                  xscale
@@ -415,7 +413,7 @@ Robert Schwebel <r.schwebel@pengutronix.de>
 
 Andrea Scian <andrea.scian@dave-tech.it>
 
-       B2                              ARM7TDMI (S3C44B0X)
+       B2                      ARM7TDMI (S3C44B0X)
 
 Greg Ungerer <greg.ungerer@opengear.com>
 
@@ -423,6 +421,10 @@ Greg Ungerer <greg.ungerer@opengear.com>
        cm4116                  ks8695p
        cm4148                  ks8695p
 
+Richard Woodruff <r-woodruff2@ti.com>
+
+       omap2420h4              ARM1136EJS
+
 Alex Züpke <azu@sysgo.de>
 
        lart                    SA1100
index d23a6dde559f8c78226ad2dd7a4d1a0ec21c6633..b24b26d104c30c53bda35a9075e67a529b56cb72 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -881,15 +881,14 @@ yellowstone_config:       unconfig
 #########################################################################
 ## MPC8220 Systems
 #########################################################################
-Alaska8220_config:     unconfig
+
+Alaska8220_config      \
+Yukon8220_config:      unconfig
        @./mkconfig $(@:_config=) ppc mpc8220 alaska
 
 sorcery_config:                unconfig
        @./mkconfig $(@:_config=) ppc mpc8220 sorcery
 
-Yukon8220_config:      unconfig
-       @./mkconfig $(@:_config=) ppc mpc8220 yukon
-
 #########################################################################
 ## MPC824x Systems
 #########################################################################
index 99fcfb5c7ed6a66e1032afee291ba9f6c833960d..cd6a2e61e66fdcf72ffda2457f23da00636992d3 100644 (file)
@@ -329,7 +329,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
        volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
        volatile FLASH_WORD_SIZE *addr2;
        int flag, prot, sect, l_sect;
-       int i;
 
        if ((s_first < 0) || (s_first > s_last)) {
                if (info->flash_id == FLASH_UNKNOWN) {
@@ -517,7 +516,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  */
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 {
-       volatile vu_long *addr2 = (vu_long *) (info->start[0]);
+       vu_long *addr2 = (vu_long *) (info->start[0]);
        volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
        volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
        ulong start;
index 840a46c86557654dc6fafbbefcf2002aa7d05c38..a6b81e6008a9acda3c95f2bd799d9340189f77f1 100644 (file)
@@ -315,10 +315,6 @@ int pci_pre_init(struct pci_controller *hose)
 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
-       u16 cmdstat;
-
-       DECLARE_GLOBAL_DATA_PTR;
-
        /*--------------------------------------------------------------------------+
         * Set up Direct MMIO registers
         *--------------------------------------------------------------------------*/
index 61a8d245f9e9bff8aa17857142cced243c0f5137..c7f54c6bd8613657053271b56273ffff81758b24 100644 (file)
  * MA 02111-1307 USA
  */
 
+#ifndef __ASSEMBLY__
+#define        __ASSEMBLY__                    /* Dirty trick to get only #defines     */
+#endif
+#define        __ASM_STUB_PROCESSOR_H__        /* don't include asm/processor.         */
 #include <config.h>
+#undef __ASSEMBLY__
 #include <environment.h>
 
 /*
diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h
new file mode 100644 (file)
index 0000000..2d3c0e5
--- /dev/null
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2004
+ * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC8220         1
+#define CONFIG_YUKON8220       1       /* ... on Yukon board   */
+
+/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
+   determine the CPU speed. */
+#define CFG_MPC8220_CLKIN      30000000/* ... running at 30MHz */
+#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+
+#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM          0x02    /* Software reboot      */
+
+#define CFG_CACHELINE_SIZE     32      /* For MPC8220 CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT  5   /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+
+/* Define this for PSC console
+#define CONFIG_PSC_CONSOLE     1
+*/
+
+#define CONFIG_EXTUART_CONSOLE 1
+
+#ifdef CONFIG_EXTUART_CONSOLE
+#   define CONFIG_CONS_INDEX   1
+#   define CFG_NS16550_SERIAL
+#   define CFG_NS16550
+#   define CFG_NS16550_REG_SIZE 1
+#   define CFG_NS16550_COM1    (CFG_CPLD_BASE + 0x1008)
+#   define CFG_NS16550_CLK     18432000
+#endif
+
+#define CONFIG_BAUDRATE                115200      /* ... at 115200 bps */
+
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_TIMESTAMP                       /* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_BOOTD   | \
+                               CFG_CMD_CACHE   | \
+                               CFG_CMD_DHCP    | \
+                               CFG_CMD_DIAG    | \
+                               CFG_CMD_EEPROM  | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_NET     | \
+                               CFG_CMD_NFS     | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_PING    | \
+                               CFG_CMD_REGINFO | \
+                               CFG_CMD_SDRAM   | \
+                               CFG_CMD_SNTP    )
+
+#define CONFIG_NET_MULTI
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY       5    /* autoboot after 5 seconds */
+#define CONFIG_BOOTARGS                "root=/dev/ram rw"
+#define CONFIG_ETHADDR         00:e0:0c:bc:e0:60
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR                00:e0:0c:bc:e0:61
+#define CONFIG_IPADDR          192.162.1.2
+#define CONFIG_NETMASK         255.255.255.0
+#define CONFIG_SERVERIP                192.162.1.1
+#define CONFIG_GATEWAYIP       192.162.1.1
+#define CONFIG_HOSTNAME                yukon
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C                1
+#define CFG_I2C_MODULE         1
+
+#define CFG_I2C_SPEED          100000 /* 100 kHz */
+#define CFG_I2C_SLAVE          0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR            0x52    /* 1011000xb */
+#define CFG_I2C_EEPROM_ADDR_LEN                1
+#define CFG_EEPROM_PAGE_WRITE_BITS     3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
+/*
+#define CFG_ENV_IS_IN_EEPROM   1
+#define CFG_ENV_OFFSET         0
+#define CFG_ENV_SIZE           256
+*/
+
+/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+   else undefined it will boot from Intel Strata flash */
+#define CFG_AMD_BOOT           1
+
+/*
+ * Flexbus Chipselect configuration
+ */
+#if defined (CFG_AMD_BOOT)
+#define CFG_CS0_BASE           0xfff0
+#define CFG_CS0_MASK           0x00080000  /* 512 KB */
+#define CFG_CS0_CTRL           0x003f0d40
+
+#define CFG_CS1_BASE           0xfe00
+#define CFG_CS1_MASK           0x01000000  /* 16 MB */
+#define CFG_CS1_CTRL           0x003f1540
+#else
+#define CFG_CS0_BASE           0xff00
+#define CFG_CS0_MASK           0x01000000  /* 16 MB */
+#define CFG_CS0_CTRL           0x003f1540
+
+#define CFG_CS1_BASE           0xfe08
+#define CFG_CS1_MASK           0x00080000  /* 512 KB */
+#define CFG_CS1_CTRL           0x003f0d40
+#endif
+
+#define CFG_CS2_BASE           0xf100
+#define CFG_CS2_MASK           0x00040000
+#define CFG_CS2_CTRL           0x003f1140
+
+#define CFG_CS3_BASE           0xf200
+#define CFG_CS3_MASK           0x00040000
+#define CFG_CS3_CTRL           0x003f1100
+
+
+#define CFG_FLASH0_BASE                (CFG_CS0_BASE << 16)
+#define CFG_FLASH1_BASE                (CFG_CS1_BASE << 16)
+
+#if defined (CFG_AMD_BOOT)
+#define CFG_AMD_BASE           CFG_FLASH0_BASE
+#define CFG_INTEL_BASE         CFG_FLASH1_BASE + 0xf00000
+#define CFG_FLASH_BASE         CFG_AMD_BASE
+#else
+#define CFG_INTEL_BASE         CFG_FLASH0_BASE + 0xf00000
+#define CFG_AMD_BASE           CFG_FLASH1_BASE
+#define CFG_FLASH_BASE         CFG_INTEL_BASE
+#endif
+
+#define CFG_CPLD_BASE          (CFG_CS2_BASE << 16)
+#define CFG_FPGA_BASE          (CFG_CS3_BASE << 16)
+
+
+#define CFG_MAX_FLASH_BANKS    4       /* max num of memory banks      */
+#define CFG_MAX_FLASH_SECT     128     /* max num of sects on one chip */
+
+#define CFG_FLASH_ERASE_TOUT   240000  /* Flash Erase Timeout (in ms)  */
+#define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (in ms)  */
+#define CFG_FLASH_LOCK_TOUT    5       /* Timeout for Flash Set Lock Bit (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT  10000   /* Timeout for Flash Clear Lock Bits (in ms) */
+#define CFG_FLASH_PROTECTION           /* "Real" (hardware) sectors protection */
+
+#define PHYS_AMD_SECT_SIZE     0x00010000 /*  64 KB sectors (x2) */
+#define PHYS_INTEL_SECT_SIZE   0x00020000 /* 128 KB sectors (x2) */
+
+#define CFG_FLASH_CHECKSUM
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH    1
+#if defined (CFG_AMD_BOOT)
+#define CFG_ENV_ADDR           (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV_SIZE           PHYS_AMD_SECT_SIZE
+#define CFG_ENV_SECT_SIZE      PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_ADDR          (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV1_SIZE          PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE     PHYS_INTEL_SECT_SIZE
+#else
+#define CFG_ENV_ADDR           (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CFG_ENV_SIZE           PHYS_INTEL_SECT_SIZE
+#define CFG_ENV_SECT_SIZE      PHYS_INTEL_SECT_SIZE
+#define CFG_ENV1_ADDR          (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CFG_ENV1_SIZE          PHYS_AMD_SECT_SIZE
+#define CFG_ENV1_SECT_SIZE     PHYS_AMD_SECT_SIZE
+#endif
+
+#define CONFIG_ENV_OVERWRITE   1
+
+#if defined CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_EEPROM
+#elif defined CFG_ENV_IS_IN_EEPROM
+#undef CFG_ENV_IS_IN_NVRAM
+#undef CFG_ENV_IS_IN_FLASH
+#endif
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK   0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS    1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR               0xF0000000
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_DEFAULT_MBAR       0x80000000
+#define CFG_SRAM_BASE          (CFG_MBAR + 0x20000)
+#define CFG_SRAM_SIZE          0x8000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR      (CFG_MBAR + 0x20000)
+#define CFG_INIT_RAM_END       0x8000  /* End of used area in DPRAM */
+
+#define CFG_GBL_DATA_SIZE      128     /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE       TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT         1
+#endif
+
+#define CFG_MONITOR_LEN                (256 << 10) /* Reserve 256 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 << 10) /* Reserve 128 kB for malloc()  */
+#define CFG_BOOTMAPSZ          (8 << 20)   /* Initial Memory map for Linux */
+
+/* SDRAM configuration */
+#define CFG_SDRAM_TOTAL_BANKS          2
+#define CFG_SDRAM_SPD_I2C_ADDR         0x51            /* 7bit */
+#define CFG_SDRAM_SPD_SIZE             0x40
+#define CFG_SDRAM_CAS_LATENCY          4               /* (CL=2)x2 */
+
+/* SDRAM drive strength register */
+#define CFG_SDRAM_DRIVE_STRENGTH       ((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+                                        (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
+                                        (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
+                                        (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
+                                        (DRIVE_STRENGTH_LOW  << SDRAMDS_SBD_SHIFT))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC8220_FEC     1
+#define CONFIG_FEC_10MBIT      1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR                0x18
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                       /* undef to save memory     */
+#define CFG_PROMPT             "=> "       /* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE             1024        /* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE             256         /* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)  /* Print Buffer Size */
+#define CFG_MAXARGS            16          /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CFG_MEMTEST_START      0x00100000  /* memtest works on */
+#define CFG_MEMTEST_END                0x00f00000  /* 1 ... 15 MB in DRAM  */
+
+#define CFG_LOAD_ADDR          0x100000    /* default load address */
+
+#define CFG_HZ                 1000        /* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CFG_HID0_INIT          HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL         HID0_ICE
+
+#endif /* __CONFIG_H */
index 5f13a63933cdebee5e683e91aff4c61d6273bdb2..7b7718324e13860f9167ffc0ebec600ff59ad9f8 100644 (file)
 #include <stdlib.h>
 #include <unistd.h>
 
-#define        __ASSEMBLY__    /* Dirty trick to get only #defines */
+#ifndef __ASSEMBLY__
+#define        __ASSEMBLY__                    /* Dirty trick to get only #defines     */
+#endif
+#define        __ASM_STUB_PROCESSOR_H__        /* don't include asm/processor.         */
 #include <config.h>
 #undef __ASSEMBLY__
 
@@ -73,24 +76,24 @@ extern unsigned char environment;
 int main (int argc, char **argv)
 {
 #ifdef ENV_IS_EMBEDDED
-    int crc ;
-    unsigned char      *envptr         = &environment,
-                       *dataptr        = envptr + ENV_HEADER_SIZE;
-    unsigned int       datasize        = ENV_SIZE;
+       int crc;
+       unsigned char *envptr = &environment,
+               *dataptr = envptr + ENV_HEADER_SIZE;
+       unsigned int datasize = ENV_SIZE;
 
-    crc = crc32(0, dataptr, datasize) ;
+       crc = crc32 (0, dataptr, datasize);
 
-    /* Check if verbose mode is activated passing a parameter to the program */
-    if (argc > 1) {
-       printf("CRC32 from offset %08X to %08X of environment = %08X\n",
-           (unsigned int)(dataptr - envptr),
-           (unsigned int)(dataptr - envptr) + datasize,
-           crc);
-    } else {
-       printf("0x%08X\n", crc);
-    }
+       /* Check if verbose mode is activated passing a parameter to the program */
+       if (argc > 1) {
+               printf ("CRC32 from offset %08X to %08X of environment = %08X\n",
+                       (unsigned int) (dataptr - envptr),
+                       (unsigned int) (dataptr - envptr) + datasize,
+                       crc);
+       } else {
+               printf ("0x%08X\n", crc);
+       }
 #else
-       printf("0\n");
+       printf ("0\n");
 #endif
-    return EXIT_SUCCESS;
+       return EXIT_SUCCESS;
 }