obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
+obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
--- /dev/null
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+src_dir := ../../arm1176/bcm2835/
+
+obj-y :=
+obj-y += $(src_dir)/init.o
+obj-y += $(src_dir)/reset.o
+obj-y += $(src_dir)/timer.o
+obj-y += $(src_dir)/mbox.o
/*
* Copyright (C) 2012 Vikram Narayananan
* <vikram186@gmail.com>
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BCM2835_GPIO_H_
#define _BCM2835_GPIO_H_
+#ifdef CONFIG_BCM2836
+#define BCM2835_GPIO_BASE 0x3f200000
+#else
#define BCM2835_GPIO_BASE 0x20200000
+#endif
#define BCM2835_GPIO_COUNT 54
#define BCM2835_GPIO_FSEL_MASK 0x7
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Raw mailbox HW */
+#ifdef CONFIG_BCM2836
+#define BCM2835_MBOX_PHYSADDR 0x3f00b880
+#else
#define BCM2835_MBOX_PHYSADDR 0x2000b880
+#endif
struct bcm2835_mbox_regs {
u32 read;
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
+#ifdef CONFIG_BCM2836
+#define BCM2835_SDHCI_BASE 0x3f300000
+#else
#define BCM2835_SDHCI_BASE 0x20300000
+#endif
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
+#ifdef CONFIG_BCM2836
+#define BCM2835_TIMER_PHYSADDR 0x3f003000
+#else
#define BCM2835_TIMER_PHYSADDR 0x20003000
+#endif
struct bcm2835_timer_regs {
u32 cs;
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
+#ifdef CONFIG_BCM2836
+#define BCM2835_WDOG_PHYSADDR 0x3f100000
+#else
#define BCM2835_WDOG_PHYSADDR 0x20100000
+#endif
struct bcm2835_wdog_regs {
u32 unknown0[7];