*.bin
*.cfgout
*.dtb
+*.dtbo
*.dtb.S
*.elf
*.exe
- name: "buildman arm926ejs (non-NXP,siemens,atmel,kirkwood,spear)"
env:
- JOB="arm926ejs"
- BUILDMAN="arm926ejs -x freescale,siemens,atmel,kirkwood,spear"
+ BUILDMAN="arm926ejs -x freescale,siemens,atmel,kirkwood,spear,omap"
- name: "buildman atmel"
env:
- BUILDMAN="atmel"
.. kernel-doc:: lib/efi_loader/efi_boottime.c
:internal:
+Image relocation
+~~~~~~~~~~~~~~~~
+
+.. kernel-doc:: lib/efi_loader/efi_image_loader.c
+ :internal:
+
Runtime services
----------------
N: meson
ARM BROADCOM BCM283X
-M: Alexander Graf <agraf@suse.de>
+M: Matthias Brugger <mbrugger@suse.com>
S: Maintained
F: arch/arm/mach-bcm283x/
F: drivers/gpio/bcm2835_gpio.c
F: test/dm/
EFI PAYLOAD
-M: Alexander Graf <agraf@suse.de>
-R: Heinrich Schuchardt <xypron.glpk@gmx.de>
+M: Heinrich Schuchardt <xypron.glpk@gmx.de>
+R: Alexander Graf <agraf@csgraf.de>
S: Maintained
T: git git://github.com/agraf/u-boot.git
F: doc/README.uefi
F: test/py/tests/test_efi*
F: test/unicode_ut.c
F: cmd/bootefi.c
+F: cmd/efidebug.c
+F: cmd/nvedit_efi.c
F: tools/file2include.c
FPGA
VERSION = 2019
PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
NAME =
# *DOCUMENTATION*
as a convenience, when switching between booting from
RAM and NFS.
-- Pre-Boot Commands:
- CONFIG_PREBOOT
-
- When this option is #defined, the existence of the
- environment variable "preboot" will be checked
- immediately before starting the CONFIG_BOOTDELAY
- countdown and/or running the auto-boot command resp.
- entering interactive mode.
-
- This feature is especially useful when "preboot" is
- automatically generated or modified. For an example
- see the LWMON board specific code: here "preboot" is
- modified when the user holds down a certain
- combination of keys on the (special) keyboard when
- booting the systems
-
- Serial Download Echo Mode:
CONFIG_LOADS_ECHO
If defined to 1, all characters received during a
config RISCV
bool "RISC-V architecture"
+ select CREATE_ARCH_SYMLINK
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
imply VIRTIO_BLK
imply VIRTIO_NET
imply DM_SOUND
+ imply PCH
config SH
bool "SuperH architecture"
imply USB_ETHER_ASIX
imply USB_ETHER_SMSC95XX
imply USB_HOST_ETHER
+ imply PCH
config XTENSA
bool "Xtensa architecture"
development platform that supports the QorIQ LS2081A/LS2041A
Layerscape Architecture processor.
+config TARGET_LX2160ARDB
+ bool "Support lx2160ardb"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2160ARDB platform.
+ The lx2160ardb (LX2160A Reference design board (RDB)
+ is a high-performance development platform that supports the
+ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+
+config TARGET_LX2160AQDS
+ bool "Support lx2160aqds"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2160AQDS platform.
+ The lx2160aqds (LX2160A QorIQ Development System (QDS)
+ is a high-performance development platform that supports the
+ QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
select BOARD_LATE_INIT
select SUPPORT_SPL
imply SCSI
+ imply SCSI_AHCI
help
Support for Freescale LS1043AQDS platform.
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
- imply SCSI
help
Support for Freescale LS1043ARDB platform.
source "board/freescale/ls1012aqds/Kconfig"
source "board/freescale/ls1012ardb/Kconfig"
source "board/freescale/ls1012afrdm/Kconfig"
+source "board/freescale/lx2160a/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
!TARGET_LS1012AFRWY && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
- !TARGET_LS2081ARDB && \
+ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
+ !TARGET_LX2160AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
- imply SCSI
- imply SCSI_AHCI
imply CMD_PCI
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
+ select FSL_LAYERSCAPE
select FSL_LSCH2
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select FSL_TZASC_1
+ select FSL_TZASC_400
+ select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
+ select FSL_LAYERSCAPE
select FSL_LSCH3
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
+ select FSL_TZASC_400
+ select FSL_TZPC_BP147
select SYS_FSL_ERRATUM_A008336 if !TFABOOT
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
+config FSL_LAYERSCAPE
+ bool
+
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
depends on PCIE_LAYERSCAPE
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config EMC2305
+ bool "Fan controller"
+ help
+ Enable the EMC2305 fan controller for configuration of fan
+ speed.
+
config SECURE_BOOT
bool "Secure Boot"
help
config FSL_TZASC_2
bool
+config FSL_TZASC_400
+ bool
+
+config FSL_TZPC_BP147
+ bool
endmenu
menu "Layerscape clock tree configuration"
printf("Did not wake secondary cores\n");
}
-#ifdef CONFIG_SYS_FSL_HAS_RGMII
- fsl_rgmii_init();
-#endif
-
config_core_prefetch();
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+ /* some dpmacs in armv8a based freescale layerscape SOCs can be
+ * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
+ * EC*_PMUX(rgmii) bits in RCW.
+ * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
+ * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
+ * Now if a dpmac is enabled by serdes bits then it takes precedence
+ * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
+ * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
+ * then the dpmac is SGMII and not RGMII.
+ *
+ * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
+ * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
+ * or not? if it is (fsl_serdes_init has already enabled the dpmac),
+ * then don't enable it.
+ */
+ fsl_rgmii_init();
+#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int i , j;
+#ifdef CONFIG_ARCH_LX2160A
+ for (i = XFI1, j = 1; i <= XFI14; i++, j++)
+ xfi_dpmac[i] = j;
+
+ for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
+ sgmii_dpmac[i] = j;
+
+ for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
+ a25gaui_dpmac[i] = j;
+
+ for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
+ xlaui_dpmac[i] = j;
+
+ for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
+ caui2_dpmac[i] = j;
+
+ for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
+ caui4_dpmac[i] = j;
+#else
for (i = XFI1, j = 1; i <= XFI8; i++, j++)
xfi_dpmac[i] = j;
for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
sgmii_dpmac[i] = j;
#endif
+#endif
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
- fsl-ls1088a-qds.dtb
+ fsl-ls1088a-qds.dtb \
+ fsl-lx2160a-rdb.dtb \
+ fsl-lx2160a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 B&R Industrial Automation GmbH
+ * http://www.br-automation.com
+ *
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+ model = "BRXRE1 Panel";
+ compatible = "ti,am33xx";
+
+ fset: factory-settings {
+ bl-version = " ";
+ order-no = " ";
+ cpu-order-no = " ";
+ hw-revision = " ";
+ serial-no = <0>;
+ device-id = <0xE681>;
+ parent-id = <0xE681>;
+ hw-variant = <0x3>;
+ hw-platform = <0x0>;
+ fram-offset = <0x1000>;
+ fram-size = <0x3000>;
+ cache-disable = <0x0>;
+ cpu-clock = <0x0>;
+ };
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootargs = "console=ttyO0,115200 earlyprintk";
+ stdout-path = &uart0;
+
+ framebuffer: framebuffer@8fbe0000 {
+ display = <&lcdscreen0>;
+ compatible = "simple-framebuffer";
+ status = "okay";
+ reg = <0x8fbef000 (1024 * 600 * 4)>;
+ width = <1024>;
+ height = <600>;
+ stride = <(1024 * 4)>;
+ format = "a8r8g8b8";
+ clocks = <&dpll_disp_m2_ck>, <&dpll_per_m2_ck>;
+ };
+ };
+
+ aliases {
+ fset = &fset;
+ mmc = &mmc2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ touch0 = &burtouch0;
+ screen0 = &lcdscreen0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ status = "okay";
+ };
+
+ vmmcsd_fixed: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ lcdscreen0: lcdscreen@0 {
+ status = "okay";
+ compatible = "ti,tilcdc,panel";
+
+ backlight = <&tps_bl>;
+
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <32>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: lcd {
+ clock-frequency = <9142857>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <8>;
+ hback-porch = <43>;
+ hsync-len = <2>;
+ vfront-porch = <4>;
+ vback-porch = <2>;
+ vsync-len = <10>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pupdelay = <10>;
+ pondelay = <10>;
+ };
+ };
+ };
+};
+
+&uart0 { /* console uart */
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&i2c0 {
+ u-boot,dm-spl;
+ status = "okay";
+ clock-frequency = <100000>;
+
+ tps: tps@24 { /* PMIC controller */
+ u-boot,dm-spl;
+ reg = <0x24>;
+ compatible = "ti,tps65217";
+
+ tps_bl: backlight {
+ compatible = "ti,tps65217-bl";
+ isel = <1>; /* 1 - ISET1, 2 ISET2 */
+ fdim = <1000>; /* TPS65217_BL_FDIM_1kHZ */
+ default-brightness = <50>;
+ };
+ };
+ resetc: rstpsc@75 { /* reset controller */
+ compatible = "bur,rstpsc";
+ reg = <0x75>;
+
+ cooling-min-state = <0>;
+ cooling-max-state = <1>; /* reset gets fired */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+ rtc0: rv3029c2@56 {
+ status = "okay";
+ #thermal-sensor-cells = <0>;
+ compatible = "rv3029c2";
+ reg = <0x56>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&edma {
+ status = "okay";
+};
+
+&cppi41dma {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&davinci_mdio {
+ status = "okay";
+};
+
+&mac {
+ status = "okay";
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <2>;
+ phy-mode = "mii";
+};
+
+&mmc1 {
+ u-boot,dm-pre-reloc;
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <0x4>;
+ ti,non-removable;
+ ti,needs-special-hs-handling;
+ ti,vcc-aux-disable-is-sleep;
+ status = "okay";
+};
+
+&mmc2 {
+ u-boot,dm-pre-reloc;
+ vmmc-supply = <&vmmcsd_fixed>;
+ bus-width = <0x8>;
+ ti,non-removable;
+ ti,needs-special-hs-handling;
+ ti,vcc-aux-disable-is-sleep;
+ status = "okay";
+};
+
+&lcdc {
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&elm {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
+};
+
+&aes {
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+ ti,no-reset-on-init;
+};
+
+&timer1 { /* today unused */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer2 { /* used for vxworks primary timer device */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer3 { /* used sysdelay and hal tsc counter*/
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer4 { /* used for PWM beeper */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer5 { /* used for PWM backlight */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer6 { /* used for cpsw end device */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&timer7 { /* used for cpsw end device */
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&wdt2 {
+ status = "okay";
+ ti,no-reset-on-init;
+ ti,no-idle-on-init;
+};
+
+&epwmss0 {
+ status = "okay";
+};
+
+&tscadc {
+ status = "okay";
+
+ tsc {
+ burtouch0: burtouch@0 {
+ status = "okay";
+ compatible = "bur,DdVxSfTouchXXX";
+ bur,hwtree = "IF7";
+ bur,KX0 = <0x0>;
+ bur,KX1 = <0x0>;
+ bur,KX2 = <0x0>;
+ bur,KY0 = <0x0>;
+ bur,KY1 = <0x0>;
+ bur,KY2 = <0x0>;
+ };
+ };
+};
+
+&dcan0 {
+ status = "okay";
+};
+
+&dcan1 {
+ status = "okay";
+};
+
+&sham {
+ status = "disabled";
+};
+
+&aes {
+ status = "disabled";
+};
+
+&rng {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source
+ *
+ * Copyright 2018-2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160AQDS Board";
+ compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160ARDB device tree source
+ *
+ * Author: Priyanka Jain <priyanka.jain@nxp.com>
+ * Sriram Dash <sriram.dash@nxp.com>
+ *
+ * Copyright 2018 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160ARDB Board";
+ compatible = "fsl,lx2160ardb", "fsl,lx2160a";
+
+};
+
+&esdhc0 {
+ status = "okay";
+};
+
+&esdhc1 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
- interrupts = <0 240 0x4>; /* Level high type */
+ interrupts = <0 26 0x4>; /* Level high type */
num-cs = <6>;
};
interrupts = <0 81 0x4>; /* Level high type */
dr_mode = "host";
};
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <0 63 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ non-removable;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ sata0: sata@3200000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 133 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata1: sata@3210000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3210000 0x0 0x10000>;
+ interrupts = <0 136 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata2: sata@3220000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3220000 0x0 0x10000>;
+ interrupts = <0 97 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
+
+ sata3: sata@3230000 {
+ compatible = "fsl,ls2080a-ahci";
+ reg = <0x0 0x3230000 0x0 0x10000>;
+ interrupts = <0 100 4>;
+ clocks = <&clockgen 4 3>;
+ status = "disabled";
+
+ };
};
* Logic PD - http://www.logicpd.com
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart1;
* Logic PD - http://www.logicpd.com
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart1;
clock-frequency = <400000>;
};
-&mmc1 {
- cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */
-};
-
&mmc2 {
status = "disabled";
};
* Logic PD - http://www.logicpd.com
*/
+#include "omap3-u-boot.dtsi"
+
&i2c1 {
clock-frequency = <400000>;
};
* Logic PD - http://www.logicpd.com
*/
+#include "omap3-u-boot.dtsi"
+
&i2c1 {
clock-frequency = <400000>;
};
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart3;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart3;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart3;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart1;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
* (C) Copyright 2017 Derald D. Woods <woods.technical@gmail.com>
*/
+#include "omap3-u-boot.dtsi"
+
/ {
chosen {
stdout-path = &uart1;
};
};
-
-&uart1 {
- reg-shift = <2>;
-};
-
-&uart2 {
- reg-shift = <2>;
-};
-
-&uart3 {
- reg-shift = <2>;
-};
--- /dev/null
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap5-u-boot.dtsi"
+ */
+
+/{
+ ocp@68000000 {
+ u-boot,dm-spl;
+
+ bandgap@48002524 {
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&uart1 {
+ u-boot,dm-spl;
+ reg-shift = <2>;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+ reg-shift = <2>;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+ reg-shift = <2>;
+};
+
+&mmc1 {
+ u-boot,dm-spl;
+};
+
+&mmc2 {
+ u-boot,dm-spl;
+};
+
+&l4_core {
+ u-boot,dm-spl;
+};
+
+&scm {
+ u-boot,dm-spl;
+};
+
+&scm_conf {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
};
spi@7000d400 {
- spi-deactivate-delay = <200>;
+ spi-deactivate-delay = <500>;
spi-max-frequency = <3000000>;
cros_ec: cros-ec@0 {
usb@7d000000 { /* Rear external USB port. */
status = "okay";
+ dr_mode = "otg";
nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
};
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
-#define CONFIG_FSL_TZASC_400
#endif
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
-#define CONFIG_FSL_TZASC_400
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#ifndef CONFIG_ARCH_LX2160A
#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#else
+#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
+#endif
#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
#ifdef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
/*
* LayerScape Internal Memory Map
*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#define FSL_CHASSIS3_SRDS3_REGSR 29
+#define FSL_CHASSIS3_RCWSR12_REGSR 12
+#define FSL_CHASSIS3_RCWSR13_REGSR 13
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK 0x07000000
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK 0x00000038
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
+#define FSL_CHASSIS3_IIC5_PMUX_MASK 0x00000E00
+#define FSL_CHASSIS3_IIC5_PMUX_SHIFT 9
#elif defined(CONFIG_ARCH_LS1088A)
#define FSL_CHASSIS3_EC1_REGSR 26
#define FSL_CHASSIS3_EC2_REGSR 26
/* Invalidate all ways */
writel(way_mask, op_reg);
/* Wait for all ways to be invalidated */
- while (readl(op_reg) && way_mask)
+ while (readl(op_reg) & way_mask)
;
pl310_cache_sync();
}
isb sy
4: ldp x0, x1, [sp, #16]
bl __asm_flush_dcache_range
+ bl __asm_flush_l3_dcache
5: ldp x29, x30, [sp],#32
ret
ENDPROC(relocate_code)
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
-int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
- const u8 phymode));
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
return 0;
}
-#ifdef CONFIG_ETH_DESIGNWARE
-static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
-{
- if (!phymode)
- return -EINVAL;
-
- if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- return 0;
- }
-
- if (!strcmp(phymode, "rgmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- return 0;
- }
-
- if (!strcmp(phymode, "rmii")) {
- *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- return 0;
- }
-
- return -EINVAL;
-}
-
-int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
- const u8 phymode))
-{
- const void *fdt = gd->fdt_blob;
- struct fdtdec_phandle_args args;
- const char *phy_mode;
- u32 phy_modereg;
- int nodes[2]; /* Max. two GMACs */
- int ret, count;
- int i, node;
-
- count = fdtdec_find_aliases_for_id(fdt, "ethernet",
- COMPAT_ALTERA_SOCFPGA_DWMAC,
- nodes, ARRAY_SIZE(nodes));
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
- "#reset-cells", 1, 0,
- &args);
- if (ret || (args.args_count != 1)) {
- debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
- continue;
- }
-
- phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
- ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
- if (ret) {
- debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
- continue;
- }
-
- resetfn(args.args[0], phy_modereg);
- }
-
- return 0;
-}
-#endif
-
#ifndef CONFIG_SPL_BUILD
static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
},
};
-/*
- * DesignWare Ethernet initialization
- */
-#ifdef CONFIG_ETH_DESIGNWARE
-static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
-{
- u32 physhift, reset;
-
- if (of_reset_id == EMAC0_RESET) {
- physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
- reset = SOCFPGA_RESET(EMAC0);
- } else if (of_reset_id == EMAC1_RESET) {
- physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
- reset = SOCFPGA_RESET(EMAC1);
- } else {
- printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
- return;
- }
-
- /* configure to PHY interface select choosed */
- clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
- phymode << physhift);
-
- /* Release the EMAC controller from reset */
- socfpga_per_reset(reset, 0);
-}
-
-static int socfpga_eth_reset(void)
-{
- /* Put all GMACs into RESET state. */
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
- return socfpga_eth_reset_common(gen5_dwmac_reset);
-};
-#else
-static int socfpga_eth_reset(void)
-{
- return 0;
-};
-#endif
-
static const struct {
const u16 pn;
const char *name;
env_set("bootmode", bsel_str[bsel].mode);
if (fpga_id >= 0)
env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
- return socfpga_eth_reset();
+ return 0;
}
#endif
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
+config TARGET_SIFIVE_FU540
+ bool "Support SiFive FU540 Board"
+
endchoice
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+source "board/sifive/fu540/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
-source "arch/riscv/cpu/qemu/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config GENERIC_RISCV
+ bool
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply SIFIVE_CLINT if RISCV_MMODE
+ imply CMD_CPU
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+obj-y += dram.o
+obj-y += cpu.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
+
+/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
+static const struct udevice_id riscv_virtio_soc_ids[] = {
+ { .compatible = "riscv-virtio-soc" },
+ { }
+};
+
+U_BOOT_DRIVER(riscv_virtio_soc) = {
+ .name = "riscv_virtio_soc",
+ .id = UCLASS_SIMPLE_BUS,
+ .of_match = riscv_virtio_soc_ids,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+ /*
+ * Ensure that we run from first 4GB so that all
+ * addresses used by U-Boot are 32bit addresses.
+ *
+ * This in-turn ensures that 32bit DMA capable
+ * devices work fine because DMA mapping APIs will
+ * provide 32bit DMA addresses only.
+ */
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+#endif
+ return gd->ram_top;
+}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
-
-config QEMU_RISCV
- bool
- select ARCH_EARLY_INIT_R
- imply CPU
- imply CPU_RISCV
- imply RISCV_TIMER
- imply SIFIVE_CLINT if RISCV_MMODE
- imply CMD_CPU
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
-
-obj-y += dram.o
-obj-y += cpu.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <dm.h>
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
- disable_interrupts();
-
- cache_flush();
-
- return 0;
-}
-
-/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
-static const struct udevice_id riscv_virtio_soc_ids[] = {
- { .compatible = "riscv-virtio-soc" },
- { }
-};
-
-U_BOOT_DRIVER(riscv_virtio_soc) = {
- .name = "riscv_virtio_soc",
- .id = UCLASS_SIMPLE_BUS,
- .of_match = riscv_virtio_soc_ids,
- .flags = DM_FLAG_PRE_RELOC,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
- */
-
-#include <common.h>
-#include <fdtdec.h>
-
-int dram_init(void)
-{
- return fdtdec_setup_mem_size_base();
-}
-
-int dram_init_banksize(void)
-{
- return fdtdec_setup_memory_banksize();
-}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __ASM_RISCV_ARCH_CLK_H
+#define __ASM_RISCV_ARCH_CLK_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
#define _ASM_CONFIG_H_
#define CONFIG_LMB
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include <linux/dma-direction.h>
+
+#define dma_mapping_error(x, y) 0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+ free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
#clock-cells = <0>;
clock-frequency = <1234>;
};
+
+ clk_fixed_factor: clk-fixed-factor {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <2>;
+ clocks = <&clk_fixed>;
+ };
};
clk_sandbox: clk-sbox {
i2s: i2s {
compatible = "sandbox,i2s";
#sound-dai-cells = <1>;
+ sandbox,silent; /* Don't emit sounds while testing */
};
misc-test {
compatible = "sandbox,mmc";
};
+ pch {
+ compatible = "sandbox,pch";
+ };
+
pci0: pci-controller0 {
compatible = "sandbox,pci";
device_type = "pci";
ulong next_tag; /* Next address tag to allocate */
struct list_head mapmem_head; /* struct sandbox_mapmem_entry */
bool hwspinlock; /* Hardware Spinlock status */
+
+ /*
+ * This struct is getting large.
+ *
+ * Consider putting test data in driver-private structs, like
+ * sandbox_pch.c.
+ *
+ * If you add new members, please put them above this comment.
+ */
};
/* Minimum space we guarantee in the state FDT when calling read/write*/
*/
int sandbox_get_sound_sum(struct udevice *dev);
+/**
+ * sandbox_set_allow_beep() - Set whether the 'beep' interface is supported
+ *
+ * @dev: Device to update
+ * @allow: true to allow the start_beep() method, false to disallow it
+ */
+void sandbox_set_allow_beep(struct udevice *dev, bool allow);
+
+/**
+ * sandbox_get_beep_frequency() - Get the frequency of the current beep
+ *
+ * @dev: Device to check
+ * @return frequency of beep, if there is an active beep, else 0
+ */
+int sandbox_get_beep_frequency(struct udevice *dev);
+
+/**
+ * sandbox_get_pch_spi_protect() - Get the PCI SPI protection status
+ *
+ * @dev: Device to check
+ * @return 0 if not protected, 1 if protected
+ */
+int sandbox_get_pch_spi_protect(struct udevice *dev);
+
#endif
#
# Copyright (c) 2016 Google, Inc
+obj-y += adsp.o
obj-y += cpu.o
obj-y += iobp.o
obj-y += lpc.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Support for Intel Application Digital Signal Processor
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot file of the same name
+ */
+
+#define LOG_CATEGORY UCLASS_SYSCON
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/cpu.h>
+#include <asm/intel_regs.h>
+#include <asm/arch/adsp.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/rcb.h>
+
+enum pci_type_t {
+ LYNX_POINT,
+ WILDCAT_POINT,
+};
+
+struct broadwell_adsp_priv {
+ bool adsp_d3_pg_enable;
+ bool adsp_sram_pg_enable;
+ bool sio_acpi_mode;
+};
+
+static int broadwell_adsp_probe(struct udevice *dev)
+{
+ struct broadwell_adsp_priv *priv = dev_get_priv(dev);
+ enum pci_type_t type;
+ u32 bar0, bar1;
+ u32 tmp32;
+
+ /* Find BAR0 and BAR1 */
+ bar0 = dm_pci_read_bar32(dev, 0);
+ if (!bar0)
+ return -EINVAL;
+ bar1 = dm_pci_read_bar32(dev, 1);
+ if (!bar1)
+ return -EINVAL;
+
+ /*
+ * Set LTR value in DSP shim LTR control register to 3ms
+ * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
+ */
+ type = dev_get_driver_data(dev);
+ tmp32 = type == WILDCAT_POINT ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
+ writel(ADSP_SHIM_LTRC_VALUE, bar0 + tmp32);
+
+ /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
+ dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
+
+ /* Program ADSP IOBP VDLDAT1 to 0x040100 */
+ pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE);
+
+ /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */
+ dm_pci_read_config32(dev, ADSP_PCI_VDRTCTL0, &tmp32);
+ if (type == WILDCAT_POINT) {
+ if (priv->adsp_d3_pg_enable) {
+ tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT;
+ if (priv->adsp_sram_pg_enable)
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ else
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT;
+ } else {
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT;
+ }
+ } else {
+ if (priv->adsp_d3_pg_enable) {
+ tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT;
+ if (priv->adsp_sram_pg_enable)
+ tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ else
+ tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT;
+ } else {
+ tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT;
+ }
+ }
+ dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32);
+
+ /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */
+ setbits_le32(RCB_REG(0x3350), 1 << 10);
+
+ /* Set DSP IOBP PMCTL 0x1e0=0x3f */
+ pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE);
+
+ if (priv->sio_acpi_mode) {
+ /* Configure for ACPI mode */
+ log_info("ADSP: Enable ACPI Mode IRQ3\n");
+
+ /* Set interrupt de-assert/assert opcode override to IRQ3 */
+ pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3);
+
+ /* Enable IRQ3 in RCBA */
+ setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
+
+ /* Set ACPI Interrupt Enable Bit */
+ pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD,
+ ADSP_PCICFGCTL_ACPIIE);
+
+ /* Put ADSP in D3hot */
+ clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
+ } else {
+ log_info("ADSP: Enable PCI Mode IRQ23\n");
+
+ /* Configure for PCI mode */
+ dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
+
+ /* Clear ACPI Interrupt Enable Bit */
+ pch_iobp_update(ADSP_IOBP_PCICFGCTL,
+ ~(ADSP_PCICFGCTL_SPCBAD |
+ ADSP_PCICFGCTL_ACPIIE), 0);
+ }
+
+ return 0;
+}
+
+static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev)
+{
+ struct broadwell_adsp_priv *priv = dev_get_priv(dev);
+
+ priv->adsp_d3_pg_enable = dev_read_bool(dev, "intel,adsp-d3-pg-enable");
+ priv->adsp_sram_pg_enable = dev_read_bool(dev,
+ "intel,adsp-sram-pg-enable");
+ priv->sio_acpi_mode = dev_read_bool(dev, "intel,sio-acpi-mode");
+
+ return 0;
+}
+
+static const struct udevice_id broadwell_adsp_ids[] = {
+ { .compatible = "intel,wildcatpoint-adsp", .data = WILDCAT_POINT },
+ { }
+};
+
+U_BOOT_DRIVER(broadwell_adsp_drv) = {
+ .name = "adsp",
+ .id = UCLASS_SYSCON,
+ .ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata,
+ .of_match = broadwell_adsp_ids,
+ .bind = dm_scan_fdt_dev,
+ .probe = broadwell_adsp_probe,
+};
+
+static struct pci_device_id broadwell_adsp_supported[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP) },
+ { },
+};
+
+U_BOOT_PCI_DEVICE(broadwell_adsp_drv, broadwell_adsp_supported);
#include <asm/arch/pch.h>
#include <asm/arch/pm.h>
#include <asm/arch/rcb.h>
+#include <asm/arch/serialio.h>
#include <asm/arch/spi.h>
+#include <dm/uclass-internal.h>
#define BIOS_CTRL 0xdc
cpu_set_power_limits(28);
}
+/* Enable LTR Auto Mode for D21:F1-F6 */
+static void serialio_d21_ltr(u32 bar0)
+{
+ /* 1. Program BAR0 + 808h[2] = 0b */
+ clrbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_LTR_MODE_MASK);
+
+ /* 2. Program BAR0 + 804h[1:0] = 00b */
+ clrbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT);
+
+ /* 3. Program BAR0 + 804h[1:0] = 11b */
+ setbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT);
+
+ /* 4. Program BAR0 + 814h[31:0] = 00000000h */
+ writel(0, bar0 + SIO_REG_AUTO_LTR);
+}
+
+/* Select I2C voltage of 1.8V or 3.3V */
+static void serialio_i2c_voltage_sel(u32 bar0, uint voltage)
+{
+ clrsetbits_le32(bar0 + SIO_REG_PPR_GEN, SIO_REG_PPR_GEN_VOLTAGE_MASK,
+ SIO_REG_PPR_GEN_VOLTAGE(voltage));
+}
+
+/* Put Serial IO D21:F0-F6 device into desired mode */
+static void serialio_d21_mode(int sio_index, int int_pin, bool acpi_mode)
+{
+ u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT;
+
+ /* Snoop select 1 */
+ portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1);
+
+ /* Set interrupt pin */
+ portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin);
+
+ if (acpi_mode) {
+ /* Enable ACPI interrupt mode */
+ portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN;
+ }
+
+ pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl);
+}
+
+/* Init sequence to be run once, done as part of D21:F0 (SDMA) init */
+static void serialio_init_once(bool acpi_mode)
+{
+ if (acpi_mode) {
+ /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA */
+ setbits_le32(RCB_REG(ACPIIRQEN),
+ 1 << 13 | 1 << 7 | 1 << 6 | 1 << 5);
+ }
+
+ /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
+ pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f);
+
+ /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
+ pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
+}
+
+/**
+ * pch_serialio_init() - set up serial I/O devices
+ *
+ * @return 0 if OK, -ve on error
+ */
+static int pch_serialio_init(void)
+{
+ struct udevice *dev, *hda;
+ bool acpi_mode = true;
+ u32 bar0, bar1;
+ int ret;
+
+ ret = uclass_find_first_device(UCLASS_I2C, &dev);
+ if (ret)
+ return ret;
+ bar0 = dm_pci_read_bar32(dev, 0);
+ if (!bar0)
+ return -EINVAL;
+ bar1 = dm_pci_read_bar32(dev, 1);
+ if (!bar1)
+ return -EINVAL;
+
+ serialio_init_once(acpi_mode);
+ serialio_d21_mode(SIO_ID_SDMA, SIO_PIN_INTB, acpi_mode);
+
+ serialio_d21_ltr(bar0);
+ serialio_i2c_voltage_sel(bar0, 1); /* Select 1.8V always */
+ serialio_d21_mode(SIO_ID_I2C0, SIO_PIN_INTC, acpi_mode);
+ setbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
+
+ clrbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);
+
+ setbits_le32(bar0 + SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN);
+
+ /* Manually find the High-definition audio, to turn it off */
+ ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1b, 0), &hda);
+ if (ret)
+ return -ENOENT;
+ dm_pci_clrset_config8(hda, 0x43, 0, 0x6f);
+
+ /* Route I/O buffers to ADSP function */
+ dm_pci_clrset_config8(hda, 0x42, 0, 1 << 7 | 1 << 6);
+ log_debug("HDA disabled, I/O buffers routed to ADSP\n");
+
+ return 0;
+}
+
static int broadwell_pch_init(struct udevice *dev)
{
int ret;
return ret;
pch_pm_init(dev);
pch_cg_init(dev);
+ ret = pch_serialio_init();
+ if (ret)
+ return ret;
systemagent_init();
return 0;
#include <asm/arch/gpio.h>
#include <dt-bindings/gpio/x86-gpio.h>
#include <dm/pinctrl.h>
+#include <dm/uclass-internal.h>
DECLARE_GLOBAL_DATA_PTR;
u32 gpiobase;
int ret;
- ret = uclass_first_device(UCLASS_PCH, &pch);
+ ret = uclass_find_first_device(UCLASS_PCH, &pch);
if (ret)
return ret;
if (!pch)
imply USB_EHCI_HCD
imply USB_XHCI_HCD
imply VIDEO_VESA
+ imply SOUND_IVYBRIDGE
if NORTHBRIDGE_INTEL_IVYBRIDGE
DECLARE_GLOBAL_DATA_PTR;
-#define GPIO_BASE 0x48
-#define BIOS_CTRL 0xdc
+#define GPIO_BASE 0x48
+#define BIOS_CTRL 0xdc
+
+#define RCBA_AUDIO_CONFIG 0x2030
+#define RCBA_AUDIO_CONFIG_HDA BIT(31)
+#define RCBA_AUDIO_CONFIG_MASK 0xfe
#ifndef CONFIG_HAVE_FSP
static int pch_revision_id = -1;
return 0;
}
+static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
+ int size)
+{
+ u32 rcba, val;
+
+ switch (req) {
+ case PCH_REQ_HDA_CONFIG:
+ dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+ val = readl(rcba + RCBA_AUDIO_CONFIG);
+ if (!(val & RCBA_AUDIO_CONFIG_HDA))
+ return -ENOENT;
+
+ return val & RCBA_AUDIO_CONFIG_MASK;
+ default:
+ return -ENOSYS;
+ }
+}
+
static const struct pch_ops bd82x6x_pch_ops = {
.get_spi_base = bd82x6x_pch_get_spi_base,
.set_spi_protect = bd82x6x_set_spi_protect,
.get_gpio_base = bd82x6x_get_gpio_base,
+ .ioctl = bd82x6x_ioctl,
};
static const struct udevice_id bd82x6x_ids[] = {
dm_pci_write_config8(dev, PAM6, 0x33);
}
+/**
+ * sandybridge_init_iommu() - Set up IOMMU so that azalia can be used
+ *
+ * It is not obvious where these values come from. They may be undocumented.
+ */
+static void sandybridge_init_iommu(struct udevice *dev)
+{
+ u32 capid0_a;
+
+ dm_pci_read_config32(dev, 0xe4, &capid0_a);
+ if (capid0_a & (1 << 23)) {
+ log_debug("capid0_a not needed\n");
+ return;
+ }
+
+ /* setup BARs */
+ writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404));
+ writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400));
+ writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414));
+ writel(IOMMU_BASE2 | 1, MCHBAR_REG(0x5410));
+
+ /* lock policies */
+ writel(0x80000000, IOMMU_BASE1 + 0xff0);
+
+ /* Enable azalia sound */
+ writel(0x20000000, IOMMU_BASE2 + 0xff0);
+ writel(0xa0000000, IOMMU_BASE2 + 0xff0);
+}
+
static int bd82x6x_northbridge_early_init(struct udevice *dev)
{
const int chipset_type = SANDYBRIDGE_MOBILE;
sandybridge_setup_northbridge_bars(dev);
+ /* Setup IOMMU BARs */
+ sandybridge_init_iommu(dev);
+
/* Device Enable */
dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
/dts-v1/;
#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/sound/azalia.h>
+#include <pci_ids.h>
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
compatible = "ehci-pci";
};
+ hda@1b,0 {
+ reg = <0x0000d800 0 0 0 0>;
+ compatible = "intel,bd82x6x-hda";
+
+ /* These correspond to the Intel HDA specification */
+ beep-verbs = <
+ 0x00170500 /* power up codec */
+ 0x00270500 /* power up DAC */
+ 0x00b70500 /* power up speaker */
+ 0x00b70740 /* enable speaker out */
+ 0x00b78d00 /* enable EAPD pin */
+ 0x00b70c02 /* set EAPD pin */
+ 0x0143b013>; /* beep volume */
+
+ codecs {
+ creative_codec: creative-ca0132 {
+ vendor-id = <PCI_VENDOR_ID_CREATIVE>;
+ device-id = <PCI_DEVICE_ID_CREATIVE_CA01322>;
+ };
+ intel_hdmi: hdmi {
+ vendor-id = <PCI_VENDOR_ID_INTEL>;
+ device-id = <PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI>;
+ };
+ };
+ };
+
usb_0: usb@1d,0 {
reg = <0x0000e800 0 0 0 0>;
compatible = "ehci-pci";
};
};
+
+&creative_codec {
+ verbs = <
+ /**
+ * Malcolm Setup. These correspond to the Intel HDA
+ * specification.
+ */
+ 0x01570d09 0x01570c23 0x01570a01 0x01570df0
+ 0x01570efe 0x01570775 0x015707d3 0x01570709
+ 0x01570753 0x015707d4 0x015707ef 0x01570775
+ 0x015707d3 0x01570709 0x01570702 0x01570737
+ 0x01570778 0x01553cce 0x015575c9 0x01553dce
+ 0x0155b7c9 0x01570de8 0x01570efe 0x01570702
+ 0x01570768 0x01570762 0x01553ace 0x015546c9
+ 0x01553bce 0x0155e8c9 0x01570d49 0x01570c88
+ 0x01570d20 0x01570e19 0x01570700 0x01571a05
+ 0x01571b29 0x01571a04 0x01571b29 0x01570a01
+
+ /* Pin Widget Verb Table */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */
+ AZALIA_SUBVENDOR(0x0, 0x144dc0c2)
+
+ /*
+ * Pin Complex (NID 0x0B) Port-G Analog Unknown
+ * Speaker at Int N/A
+ */
+ AZALIA_PIN_CFG(0x0, 0x0b, 0x901700f0)
+
+ /* Pin Complex (NID 0x0C) N/C */
+ AZALIA_PIN_CFG(0x0, 0x0c, 0x70f000f0)
+
+ /* Pin Complex (NID 0x0D) N/C */
+ AZALIA_PIN_CFG(0x0, 0x0d, 0x70f000f0)
+
+ /* Pin Complex (NID 0x0E) N/C */
+ AZALIA_PIN_CFG(0x0, 0x0e, 0x70f000f0)
+
+ /* Pin Complex (NID 0x0F) N/C */
+ AZALIA_PIN_CFG(0x0, 0x0f, 0x70f000f0)
+
+ /* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */
+ AZALIA_PIN_CFG(0x0, 0x10, 0x032110f0)
+
+ /* Pin Complex (NID 0x11) Port-B Click Mic */
+ AZALIA_PIN_CFG(0x0, 0x11, 0x90a700f0)
+
+ /* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
+ AZALIA_PIN_CFG(0x0, 0x12, 0x03a110f0)
+
+ /* Pin Complex (NID 0x13) What you hear */
+ AZALIA_PIN_CFG(0x0, 0x13, 0x90d600f0)>;
+};
+
+&intel_hdmi {
+ verbs = <
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(0x3, 0x80860101)
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010)
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020)
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)>;
+};
intel,pre-graphics-delay = <200>;
};
- me@16,0 {
- reg = <0x0000b000 0 0 0 0>;
- compatible = "intel,me";
- u-boot,dm-pre-reloc;
+ adsp@13,0 {
+ reg = <0x00009800 0 0 0 0>;
+ compatible = "intel,wildcatpoint-adsp";
+ intel,adsp-d3-pg-enable = <0>;
+ intel,adsp-sram-pg-enable = <0>;
+ intel,sio-acpi-mode;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2s: shim {
+ compatible = "intel,broadwell-i2s";
+ #sound-dai-cells = <1>;
+ reg = <0xfb000 0xfc000 0xfd000>;
+ };
};
usb_1: usb@14,0 {
compatible = "xhci-pci";
};
+ i2c0: i2c@15,1 {
+ reg = <0x0000a900 0 0 0 0>;
+ compatible = "snps,designware-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rt5677: rt5677@2c {
+ compatible = "realtek,rt5677";
+ #sound-dai-cells = <1>;
+ reg = <0x2c>;
+ };
+ };
+
+ me@16,0 {
+ reg = <0x0000b000 0 0 0 0>;
+ compatible = "intel,me";
+ u-boot,dm-pre-reloc;
+ };
+
usb_0: usb@1d,0 {
status = "disabled";
reg = <0x0000e800 0 0 0 0>;
};
};
+ sound {
+ compatible = "google,samus-sound";
+ codec-enable-gpio = <&gpio_b 11 GPIO_ACTIVE_HIGH>;
+ cpu {
+ sound-dai = <&i2s 0>;
+ };
+
+ codec {
+ sound-dai = <&rt5677 0>;
+ };
+ };
+
};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Support for Intel Application Digital Signal Processor
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot file of the same name
+ */
+
+#ifndef __ASM_ARCH_BROADWELL_ADSP_H
+#define __ASM_ARCH_BROADWELL_ADSP_H
+
+#define ADSP_PCI_IRQ 23
+#define ADSP_ACPI_IRQ 3
+#define ADSP_ACPI_IRQEN BIT(3)
+
+#define ADSP_SHIM_BASE_LPT 0xe7000
+#define ADSP_SHIM_BASE_WPT 0xfb000
+#define ADSP_SHIM_LTRC 0xe0
+#define ADSP_SHIM_LTRC_VALUE 0x3003
+#define ADSP_SHIM_IMC 0x28
+#define ADSP_SHIM_IPCD 0x40
+
+#define ADSP_PCI_VDRTCTL0 0xa0
+#define ADSP_VDRTCTL0_D3PGD_LPT BIT(1)
+#define ADSP_VDRTCTL0_D3PGD_WPT BIT(0)
+#define ADSP_VDRTCTL0_D3SRAMPGD_LPT BIT(2)
+#define ADSP_VDRTCTL0_D3SRAMPGD_WPT BIT(1)
+#define ADSP_PCI_VDRTCTL1 0xa4
+#define ADSP_PCI_VDRTCTL2 0xa8
+#define ADSP_VDRTCTL2_VALUE 0x00000fff
+
+#define ADSP_IOBP_VDLDAT1 0xd7000624
+#define ADSP_VDLDAT1_VALUE 0x00040100
+#define ADSP_IOBP_VDLDAT2 0xd7000628
+#define ADSP_IOBP_ACPI_IRQ3 0xd9d8
+#define ADSP_IOBP_ACPI_IRQ3I 0xd8d9
+#define ADSP_IOBP_ACPI_IRQ4 0xdbda
+#define ADSP_IOBP_PMCTL 0xd70001e0
+#define ADSP_PMCTL_VALUE 0x3f
+#define ADSP_IOBP_PCICFGCTL 0xd7000500
+#define ADSP_PCICFGCTL_PCICD BIT(0)
+#define ADSP_PCICFGCTL_ACPIIE BIT(1)
+#define ADSP_PCICFGCTL_SPCBAD BIT(7)
+
+#endif /* __ASM_ARCH_BROADWELL_ADSP_H */
#define SATA_DTLE_EDGE_SHIFT 16
/* Power Management */
+#define PCH_PCS 0x84
+#define PCH_PCS_PS_D3HOT 3
+
#define GEN_PMCON_1 0xa0
#define SMI_LOCK (1 << 4)
#define GEN_PMCON_2 0xa2
#ifndef __asm_arch_rcba_h
#define __asm_arch_rcba_h
+#define ACPIIRQEN 0x31e0 /* 32bit */
+
#define PMSYNC_CONFIG 0x33c4 /* 32bit */
#define PMSYNC_CONFIG2 0x33cc /* 32bit */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Serial IO defintiions (taken from coreboot file of same name)
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __ARCH_BROADWELL_SERIALIO_H_
+#define __ARCH_BROADWELL_SERIALIO_H_
+
+/* Serial IO IOBP Registers */
+#define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */
+#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN BIT(5)
+#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS BIT(4)
+#define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */
+#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13)
+#define SIO_IOBP_GPIODF 0xcb000154
+#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN BIT(4)
+#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN BIT(3)
+#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN BIT(2)
+#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN BIT(1)
+#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN BIT(0)
+#define SIO_IOBP_GPIODF_UART0_BYTE_ACCESS BIT(10)
+#define SIO_IOBP_GPIODF_UART1_BYTE_ACCESS BIT(11)
+#define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */
+#define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */
+#define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */
+#define SIO_IOBP_PORTCTRL5 0xcb000258 /* SPI0 D21:F3 */
+#define SIO_IOBP_PORTCTRL6 0xcb000260 /* SPI1 D21:F4 */
+#define SIO_IOBP_PORTCTRL7 0xcb000268 /* UART0 D21:F5 */
+#define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */
+#define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8))
+/* PORTCTRL 2-8 have the same layout */
+#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN BIT(21)
+#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS BIT(20)
+#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18)
+#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2)
+#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT BIT(1)
+#define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */
+#define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */
+#define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */
+#define SIO_IOBP_FUNCDIS3 0xce00aac7 /* SPI0 D21:F3 */
+#define SIO_IOBP_FUNCDIS4 0xce00ab07 /* SPI1 D21:F4 */
+#define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */
+#define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */
+#define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */
+#define SIO_IOBP_FUNCDIS_DIS BIT(8)
+
+/* Serial IO Devices */
+#define SIO_ID_SDMA 0 /* D21:F0 */
+#define SIO_ID_I2C0 1 /* D21:F1 */
+#define SIO_ID_I2C1 2 /* D21:F2 */
+#define SIO_ID_SPI0 3 /* D21:F3 */
+#define SIO_ID_SPI1 4 /* D21:F4 */
+#define SIO_ID_UART0 5 /* D21:F5 */
+#define SIO_ID_UART1 6 /* D21:F6 */
+#define SIO_ID_SDIO 7 /* D23:F0 */
+
+#define SIO_REG_PPR_CLOCK 0x800
+#define SIO_REG_PPR_CLOCK_EN BIT(0)
+#define SIO_REG_PPR_CLOCK_UPDATE BIT(31)
+#define SIO_REG_PPR_CLOCK_M_DIV 0x25a
+#define SIO_REG_PPR_CLOCK_N_DIV 0x7fff
+#define SIO_REG_PPR_RST 0x804
+#define SIO_REG_PPR_RST_ASSERT 0x3
+#define SIO_REG_PPR_GEN 0x808
+#define SIO_REG_PPR_GEN_LTR_MODE_MASK BIT(2)
+#define SIO_REG_PPR_GEN_VOLTAGE_MASK BIT(3)
+#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3)
+#define SIO_REG_AUTO_LTR 0x814
+
+#define SIO_REG_SDIO_PPR_GEN 0x1008
+#define SIO_REG_SDIO_PPR_SW_LTR 0x1010
+#define SIO_REG_SDIO_PPR_CMD12 0x3c
+#define SIO_REG_SDIO_PPR_CMD12_B30 BIT(30)
+
+#define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */
+#define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */
+#define SIO_PIN_INTC 3 /* IRQ7 in ACPI mode */
+#define SIO_PIN_INTD 4 /* IRQ13 in ACPI mode */
+
+#endif /* __ARCH_BROADWELL_SERIALIO_H_ */
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
+#define IOMMU_BASE1 0xfed90000ULL
+#define IOMMU_BASE2 0xfed91000ULL
+
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
#define MCHBAR 0x48
/* The clock frequency of the i8253/i8254 PIT */
#define PIT_TICK_RATE 1193182
+/**
+ * i8254_enable_beep() - Start a beep using the PCAT timer
+ *
+ * This starts beeping using the legacy i8254 timer. The beep may be silenced
+ * after a delay with i8254_disable_beep().
+ *
+ * @frequency_hz: Frequency of beep in Hz
+ * @return 0 if OK, -EINVAL if frequency_hz is 0
+ */
+int i8254_enable_beep(uint frequency_hz);
+
+/**
+ * i8254_disable_beep() - Disable the bepper
+ *
+ * This stops any existing beep
+ */
+void i8254_disable_beep(void);
+
#endif /* _ASMI386_I8954_H_ */
* memory location directly.
*/
-#define readb(addr) (*(volatile unsigned char *) (addr))
-#define readw(addr) (*(volatile unsigned short *) (addr))
-#define readl(addr) (*(volatile unsigned int *) (addr))
-#define readq(addr) (*(volatile unsigned long long *) (addr))
+#define readb(addr) (*(volatile u8 *)(uintptr_t)(addr))
+#define readw(addr) (*(volatile u16 *)(uintptr_t)(addr))
+#define readl(addr) (*(volatile u32 *)(uintptr_t)(addr))
+#define readq(addr) (*(volatile u64 *)(uintptr_t)(addr))
#define __raw_readb readb
#define __raw_readw readw
#define __raw_readl readl
#define __raw_readq readq
-#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b))
-#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b))
-#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b))
-#define writeq(b,addr) (*(volatile unsigned long long *) (addr) = (b))
+#define writeb(b, addr) (*(volatile u8 *)(addr) = (b))
+#define writew(b, addr) (*(volatile u16 *)(addr) = (b))
+#define writel(b, addr) (*(volatile u32 *)(addr) = (b))
+#define writeq(b, addr) (*(volatile u64 *)(addr) = (b))
#define __raw_writeb writeb
#define __raw_writew writew
#define __raw_writel writel
#include <asm/io.h>
#include <asm/i8254.h>
-#define TIMER1_VALUE 18 /* 15.6us */
-#define TIMER2_VALUE 0x0a8e /* 440Hz */
+#define TIMER1_VALUE 18 /* 15.6us */
+#define BEEP_FREQUENCY_HZ 440
+#define SYSCTL_PORTB 0x61
+#define PORTB_BEEP_ENABLE 0x3
+
+static void i8254_set_beep_freq(uint frequency_hz)
+{
+ uint countdown;
+
+ countdown = PIT_TICK_RATE / frequency_hz;
+
+ outb(countdown & 0xff, PIT_BASE + PIT_T2);
+ outb((countdown >> 8) & 0xff, PIT_BASE + PIT_T2);
+}
int i8254_init(void)
{
*/
outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3,
PIT_BASE + PIT_COMMAND);
- outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2);
- outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2);
+ i8254_set_beep_freq(BEEP_FREQUENCY_HZ);
+
+ return 0;
+}
+
+int i8254_enable_beep(uint frequency_hz)
+{
+ if (!frequency_hz)
+ return -EINVAL;
+
+ i8254_set_beep_freq(frequency_hz);
+ setio_8(SYSCTL_PORTB, PORTB_BEEP_ENABLE);
return 0;
}
+
+void i8254_disable_beep(void)
+{
+ clrio_8(SYSCTL_PORTB, PORTB_BEEP_ENABLE);
+}
F: board/BuR/brxre1/
F: include/configs/brxre1.h
F: configs/brxre1_defconfig
+F: arch/arm/dts/am335x-brxre1.dts
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
+#include <dm.h>
#include <i2c.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
DECLARE_GLOBAL_DATA_PTR;
+static int rstctrl_rw(u8 reg, unsigned char rnw, void *pdat, int size)
+{
+ struct udevice *i2cdev;
+ int rc;
+
+ rc = i2c_get_chip_for_busnum(0, RSTCTRL_ADDR, 1, &i2cdev);
+ if (rc >= 0) {
+ if (rnw)
+ rc = dm_i2c_read(i2cdev, reg, pdat, size);
+ else
+ rc = dm_i2c_write(i2cdev, reg, pdat, size);
+ } else {
+ printf("%s: cannot get udevice for chip 0x%02x!\n",
+ __func__, RSTCTRL_ADDR);
+ }
+
+ return rc;
+}
+
#if defined(CONFIG_SPL_BUILD)
/* TODO: check ram-timing ! */
static const struct ddr_data ddr3_data = {
void am33xx_spl_board_init(void)
{
- unsigned int oldspeed;
unsigned short buf;
+ int rc;
struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
};
do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
/* power-OFF LCD-Display */
- gpio_direction_output(LCD_PWR, 0);
+ if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
+ printf("cannot request gpio for LCD_PWR!\n");
+ else if (gpio_direction_output(LCD_PWR, 0) != 0)
+ printf("cannot set direction output on LCD_PWR!\n");
/* setup I2C */
enable_i2c_pin_mux();
- i2c_set_bus_num(0);
- i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
- /* power-ON 3V3 via Resetcontroller */
- oldspeed = i2c_get_bus_speed();
- if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
- buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
- i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
- (uint8_t *)&buf, sizeof(buf));
- i2c_set_bus_speed(oldspeed);
- } else {
- puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
- }
+ /* power-ON 3V3 via Resetcontroller */
+ buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
+ rc = rstctrl_rw(RSTCTRL_CTRLREG, 0, (uint8_t *)&buf, sizeof(buf));
+ if (rc != 0)
+ printf("ERROR: cannot write to resetc (turn on PWR_nEN)\n");
pmicsetup(0, 0);
}
*/
int board_init(void)
{
- gpmc_init();
+ if (power_tps65217_init(0))
+ printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
+
return 0;
}
unsigned int cnt = 3;
unsigned short buf = 0xAAAA;
unsigned char scratchreg = 0;
- unsigned int oldspeed;
+ int rc;
/* try to read out some boot-instruction from resetcontroller */
- oldspeed = i2c_get_bus_speed();
- if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
- i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
- &scratchreg, sizeof(scratchreg));
- i2c_set_bus_speed(oldspeed);
- } else {
- puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
- }
+ rc = rstctrl_rw(RSTCTRL_SCRATCHREG, 1, &scratchreg, sizeof(scratchreg));
+ if (rc != 0)
+ printf("ERROR: read scratchregister (resetc) failed!\n");
- if (gpio_get_value(ESC_KEY)) {
+ if (gpio_request(ESC_KEY, "boot-key") != 0) {
+ printf("cannot request boot-key!\n");
+ } else if (gpio_get_value(ESC_KEY)) {
do {
lcd_position_cursor(1, 8);
switch (cnt) {
break;
}
/* write bootinfo into scratchregister of resetcontroller */
- oldspeed = i2c_get_bus_speed();
- if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
- i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
- (uint8_t *)&buf, sizeof(buf));
- i2c_set_bus_speed(oldspeed);
- } else {
- puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
- }
+ rc = rstctrl_rw(RSTCTRL_SCRATCHREG, 0, (uint8_t *)&buf, sizeof(buf));
+ if (rc != 0)
+ printf("ERROR: write scratchregister (resetc) failed!\n");
+
/* setup othbootargs for bootvx-command (vxWorks bootline) */
char othbootargs[128];
snprintf(othbootargs, sizeof(othbootargs),
void lcdpower(int on)
{
u32 pin, swval, i;
+ char buf[16] = { 0 };
pin = env_get_ulong("ds1_pwr", 16, ~0UL);
for (i = 0; i < 3; i++) {
if (pin != 0) {
+ snprintf(buf, sizeof(buf), "ds1_pwr#%d", i);
+ if (gpio_request(pin & 0x7F, buf) != 0) {
+ printf("%s: not able to request gpio %s",
+ __func__, buf);
+ continue;
+ }
swval = pin & 0x80 ? 0 : 1;
if (on)
gpio_direction_output(pin & 0x7F, swval);
-if ARCH_BCM63158
+if TARGET_BCM963158
config SYS_VENDOR
default "broadcom"
U-Boot > nand erase.part bootloader
U-Boot > nand write 0xc0700000 bootloader
+On the DA850-EVM, NAND can also be written with SW7:7-8 ON and
+
+ sudo mono sfh_OMAP-L138.exe -targetType AM1808 -p /dev/ttyUSB0 \
+ -flash_noubl -flashType NAND ~/src/u-boot/u-boot.ais
+
+To boot the DA850-EVM from NAND, SW7:5 should be switched on and all others
+off.
+
Flashing the images to MMC
==========================
If the boot pins are set to boot from mmc, the RBL will try to load the
*/
#include <common.h>
+#include <i2c.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
-#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
default "emulation"
config SYS_CPU
- default "qemu"
+ default "generic"
config SYS_CONFIG_NAME
default "qemu-riscv"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select QEMU_RISCV
+ select GENERIC_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
+obj-$(CONFIG_EMC2305) += emc2305.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "emc2305.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void set_fan_speed(u8 data)
+{
+ u8 index;
+ u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
+ I2C_EMC2305_FAN2,
+ I2C_EMC2305_FAN3,
+ I2C_EMC2305_FAN4,
+ I2C_EMC2305_FAN5};
+
+ for (index = 0; index < NUM_OF_FANS; index++) {
+ if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {
+ printf("Error: failed to change fan speed @%x\n",
+ Fan[index]);
+ }
+ }
+}
+
+void emc2305_init(void)
+{
+ u8 data;
+
+ data = I2C_EMC2305_CMD;
+ if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)
+ printf("Error: failed to configure EMC2305\n");
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EMC2305_H_
+#define __EMC2305_H_
+
+#define I2C_EMC2305_CONF 0x20
+#define I2C_EMC2305_FAN1 0x30
+#define I2C_EMC2305_FAN2 0x40
+#define I2C_EMC2305_FAN3 0x50
+#define I2C_EMC2305_FAN4 0x60
+#define I2C_EMC2305_FAN5 0x70
+
+#define NUM_OF_FANS 5
+
+void emc2305_init(void);
+void set_fan_speed(u8 data);
+
+#endif /* __EMC2305_H_ */
#ifdef QIXIS_LBMAP_SD
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
+#ifdef NON_EXTENDED_DUTCFG
+ QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_SD);
+#else
set_lbmap(QIXIS_LBMAP_SD);
set_rcw_src(QIXIS_RCW_SRC_SD);
+#endif
QIXIS_WRITE(rcfg_ctl, 0x20);
QIXIS_WRITE(rcfg_ctl, 0x21);
#else
--- /dev/null
+if TARGET_LX2160ARDB
+
+config SYS_BOARD
+ default "lx2160a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "lx2160ardb"
+
+source "board/freescale/common/Kconfig"
+endif
+
+if TARGET_LX2160AQDS
+
+config SYS_BOARD
+ default "lx2160a"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_SOC
+ default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+ default "lx2160aqds"
+
+source "board/freescale/common/Kconfig"
+endif
+
--- /dev/null
+LX2160ARDB BOARD
+M: Priyanka Jain <priyanka.jain@nxp.com>
+S: Maintained
+F: board/freescale/lx2160a/
+F: include/configs/lx2160a_common.h
+F: include/configs/lx2160ardb.h
+F: configs/lx2160ardb_tfa_defconfig
+F: arch/arm/dts/fsl-lx2160a-rdb.dts
+
+LX2160ARDB_SECURE_BOOT BOARD
+M: Udit Agarwal <udit.agarwal@nxp.com>
+S: Maintained
+F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+
+LX2160AQDS BOARD
+M: Pankaj Bansal <pankaj.bansal@nxp.com>
+S: Maintained
+F: board/freescale/lx2160a/eth_lx2160aqds.h
+F: include/configs/lx2160aqds.h
+F: configs/lx2160aqds_tfa_defconfig
+F: arch/arm/dts/fsl-lx2160a-qds.dts
+
+LX2160AQDS_SECURE_BOOT BOARD
+M: Udit Agarwal <udit.agarwal@nxp.com>
+S: Maintained
+F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
--- /dev/null
+#
+# Copyright 2018 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += lx2160a.o
+obj-y += ddr.o
+obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o
+obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o
--- /dev/null
+Overview
+--------
+The LX2160A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LX2160A
+Layerscape Architecture processor and its personalities.
+
+LX2160A SoC Overview
+--------------------------------------
+For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
+
+LX2160ARDB board Overview
+----------------------
+DDR Memory
+ Two ports of 72-bits (8-bits ECC) DDR4.
+ Each port supports four chip-selects and two DIMM
+ connectors. Data rate upto 3.2 GT/s.
+
+SERDES ports
+ Thress serdes controllers (24 lanes)
+ Serdes1: Supports two USXGMII connectors, each connected through
+ Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi
+ IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi
+ CS4223 phy.
+
+ Serdes2: Supports one PCIe x4 (Gen1/2/3/4) connector, four SATA 3.0
+ connectors
+
+ Serdes3: Supports one PCIe x8 (Gen1/2/3/4) connector
+
+eSDHC
+ eSDHC1: Supports a SD connector for connecting SD cards
+ eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC
+
+Octal SPI (XSPI)
+ Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator
+ for off-board emulation
+
+I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer
+ Serial Ports
+
+USB 3.0
+ Two high speed USB 3.0 ports. First USB 3.0 port configured as
+ Host with Type-A connector, second USB 3.0 port configured as OTG
+ with micro-AB connector
+
+Serial Ports Two UART ports
+Ethernet Two RGMII interfaces
+Debug ARM JTAG support
+
+Booting Options
+---------------
+a) Flexspi boot
+b) SD boot
+
+Memory map for Flexspi flash
+----------------------------
+Image Flash Offset
+bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000
+fip.bin (bl31 + bl33(u-boot) +
+ header for Secure-boot(secure-boot only)) 0x00100000
+Boot firmware Environment 0x00500000
+DDR PHY Firmware (fip_ddr_all.bin) 0x00800000
+DPAA2 MC Firmware 0x00A00000
+DPAA2 DPL 0x00D00000
+DPAA2 DPC 0x00E00000
+Kernel.itb 0x01000000
+
+Memory map for sd card
+----------------------------
+Image SD card Offset
+bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008
+fip.bin (bl31 + bl33(u-boot) +
+ header for Secure-boot(secure-boot only)) 0x00800
+Boot firmware Environment 0x02800
+DDR PHY Firmware (fip_ddr_all.bin) 0x04000
+DPAA2 MC Firmware 0x05000
+DPAA2 DPL 0x06800
+DPAA2 DPC 0x07000
+Kernel.itb 0x08000
+
+LX2160AQDS board Overview
+----------------------
+Various Mezzanine cards and their connection for different SERDES protocols is
+as below:
+
+SERDES1 |CARDS
+-----------------------------------------------------------------------
+1 |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+3 |Mezzanine:X-M11-USXGMII (29828)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+7 |Mezzanine:X-M11-USXGMII (29828)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+8 |Mezzanine:X-M12-XFI (29829)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M12-XFI (29829)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+13 |Mezzanine:X-M8-100G (29734)
+ |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M8-100G (29734)
+ |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT2(J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+15 |Mezzanine:X-M8-100G (29734)
+ |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+17 |Mezzanine:X-M13-25G (32133)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J110)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+19 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108)
+ |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125)
+ |Mezzanine:X-M7-40G (29738)
+ |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+20 |Mezzanine:X-M7-40G (29738)
+ |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108)
+ |Connect I/O cable to IO_SLOT1(J108)
+ |Mezzanine:X-M7-40G (29738)
+ |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT2 (J111)
+ |Connect I/O cable to IO_SLOT2(J113)
+------------------------------------------------------------------------
+
+
+SERDES2 |CARDS
+-----------------------------------------------------------------------
+2 |Mezzanine:X-M6-PCIE-X8 (29737) *
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+ |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117)
+ |Connect I/O cable to IO_SLOT3(J116)
+------------------------------------------------------------------------
+3 |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+ |Connect I/O cable to IO_SLOT3(J116)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+ |Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+5 |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+ |Connect I/O cable to IO_SLOT3(J116)
+ |Mezzanine:X-M5-SATA (29687)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+ |Connect I/O cable to IO_SLOT4(J119)
+------------------------------------------------------------------------
+11 |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114)
+ |Connect I/O cable to IO_SLOT7(J127)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117)
+ |Connect I/O cable to IO_SLOT8(J131)
+------------------------------------------------------------------------
+
+
+SERDES3 |CARDS
+-----------------------------------------------------------------------
+2 |Mezzanine:X-M6-PCIE-X8 (29737) *
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
+ |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT6 (J123)
+ |Connect I/O cable to IO_SLOT5(J122)
+-------------------------------------------------------------------------
+3 |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT5 (J120)
+ |Connect I/O cable to IO_SLOT5(J122)
+ |Mezzanine:X-M4-PCIE-SGMII (29733)
+ |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT6 (J123)
+ |Connect I/O cable to IO_SLOT6(J125)
+-------------------------------------------------------------------------
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_initdram(void)
+{
+ gd->ram_size = tfa_get_dram_size();
+
+ if (!gd->ram_size)
+ gd->ram_size = fsl_ddr_sdram_size();
+
+ return 0;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#include "../common/qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EMI_NONE 0
+#define EMI1 1 /* Mdio Bus 1 */
+#define EMI2 2 /* Mdio Bus 2 */
+
+#if defined(CONFIG_FSL_MC_ENET)
+enum io_slot {
+ IO_SLOT_NONE = 0,
+ IO_SLOT_1,
+ IO_SLOT_2,
+ IO_SLOT_3,
+ IO_SLOT_4,
+ IO_SLOT_5,
+ IO_SLOT_6,
+ IO_SLOT_7,
+ IO_SLOT_8,
+ EMI1_RGMII1,
+ EMI1_RGMII2,
+ IO_SLOT_MAX
+};
+
+struct lx2160a_qds_mdio {
+ enum io_slot ioslot : 4;
+ u8 realbusnum : 4;
+ struct mii_dev *realbus;
+};
+
+/* structure explaining the phy configuration on 8 lanes of a serdes*/
+struct serdes_phy_config {
+ u8 serdes; /* serdes protocol */
+ struct phy_config {
+ u8 dpmacid;
+ /* -1 terminated array */
+ int phy_address[WRIOP_MAX_PHY_NUM + 1];
+ u8 mdio_bus;
+ enum io_slot ioslot;
+ } phy_config[SRDS_MAX_LANES];
+};
+
+/* Table defining the phy configuration on 8 lanes of a serdes.
+ * Various assumptions have been made while defining this table.
+ * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
+ * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
+ * And also that this card is connected to IO Slot 1 (could have been connected
+ * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
+ * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
+ * used in serdes1 protocol 19 (could have selected MDIO 2)
+ * To override these settings "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ * This table has limited serdes protocol entries. It can be expanded as per
+ * requirement.
+ */
+static const struct serdes_phy_config serdes1_phy_config[] = {
+ {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+ EMI1, IO_SLOT_1} } },
+ {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
+ EMI1, IO_SLOT_2},
+ {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_2},
+ {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_2},
+ {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_2} } },
+ {8, {} },
+ {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_2} } },
+ {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1} } },
+ {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1} } },
+ {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_2},
+ {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_6},
+ {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
+ EMI1, IO_SLOT_6} } },
+ {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_1},
+ {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
+ EMI1, IO_SLOT_2} } }
+};
+
+static const struct serdes_phy_config serdes2_phy_config[] = {
+ {2, {} },
+ {3, {} },
+ {5, {} },
+ {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_7},
+ {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
+ EMI1, IO_SLOT_8},
+ {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
+ EMI1, IO_SLOT_8},
+ {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
+ EMI1, IO_SLOT_8} } },
+};
+
+static const struct serdes_phy_config serdes3_phy_config[] = {
+ {2, {} },
+ {3, {} }
+};
+
+static inline
+const struct phy_config *get_phy_config(u8 serdes,
+ const struct serdes_phy_config *table,
+ u8 table_size)
+{
+ int i;
+
+ for (i = 0; i < table_size; i++) {
+ if (table[i].serdes == serdes)
+ return table[i].phy_config;
+ }
+
+ return NULL;
+}
+
+/* BRDCFG4 controls EMI routing for the board.
+ * Bits Function
+ * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
+ * EMI1 00= On-board PHY #1
+ * 01= On-board PHY #2
+ * 10= (reserved)
+ * 11= Slots 1..8 multiplexer and translator.
+ * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
+ * EMI1X 000= Slot #1
+ * 001= Slot #2
+ * 010= Slot #3
+ * 011= Slot #4
+ * 100= Slot #5
+ * 101= Slot #6
+ * 110= Slot #7
+ * 111= Slot #8
+ * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
+ * EMI2 000= Slot #1 (secondary EMI)
+ * 001= Slot #2 (secondary EMI)
+ * 010= Slot #3 (secondary EMI)
+ * 011= Slot #4 (secondary EMI)
+ * 100= Slot #5 (secondary EMI)
+ * 101= Slot #6 (secondary EMI)
+ * 110= Slot #7 (secondary EMI)
+ * 111= Slot #8 (secondary EMI)
+ */
+static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
+{
+ switch (realbusnum) {
+ case EMI1:
+ switch (ioslot) {
+ case EMI1_RGMII1:
+ return 0;
+ case EMI1_RGMII2:
+ return 0x40;
+ default:
+ return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
+ }
+ break;
+ case EMI2:
+ return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
+ default:
+ return -1;
+ }
+}
+
+static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
+{
+ u8 brdcfg4, mux_val, reg;
+
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ reg = brdcfg4;
+ mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+
+ switch (priv->realbusnum) {
+ case EMI1:
+ brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
+ brdcfg4 |= mux_val;
+ break;
+ case EMI2:
+ brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
+ brdcfg4 |= mux_val;
+ break;
+ }
+
+ if (brdcfg4 ^ reg)
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+}
+
+static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
+ int devad, int regnum)
+{
+ struct lx2160a_qds_mdio *priv = bus->priv;
+
+ lx2160a_qds_mux_mdio(priv);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct lx2160a_qds_mdio *priv = bus->priv;
+
+ lx2160a_qds_mux_mdio(priv);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
+{
+ struct lx2160a_qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
+{
+ struct lx2160a_qds_mdio *pmdio;
+ struct mii_dev *bus;
+ /*should be within MDIO_NAME_LEN*/
+ char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
+
+ if (realbusnum == EMI2) {
+ if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
+ printf("invalid ioslot %d\n", ioslot);
+ return NULL;
+ }
+ } else if (realbusnum == EMI1) {
+ if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
+ printf("invalid ioslot %d\n", ioslot);
+ return NULL;
+ }
+ } else {
+ printf("not supported real mdio bus %d\n", realbusnum);
+ return NULL;
+ }
+
+ if (ioslot == EMI1_RGMII1)
+ strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
+ else if (ioslot == EMI1_RGMII2)
+ strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
+ else
+ sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
+ realbusnum, ioslot);
+ bus = miiphy_get_dev_by_name(dummy_mdio_name);
+
+ if (bus)
+ return bus;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("Failed to allocate %s bus\n", dummy_mdio_name);
+ return NULL;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate %s private data\n", dummy_mdio_name);
+ free(bus);
+ return NULL;
+ }
+
+ switch (realbusnum) {
+ case EMI1:
+ pmdio->realbus =
+ miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ break;
+ case EMI2:
+ pmdio->realbus =
+ miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ break;
+ }
+
+ if (!pmdio->realbus) {
+ printf("No real mdio bus num %d found\n", realbusnum);
+ free(bus);
+ free(pmdio);
+ return NULL;
+ }
+
+ pmdio->realbusnum = realbusnum;
+ pmdio->ioslot = ioslot;
+ bus->read = lx2160a_qds_mdio_read;
+ bus->write = lx2160a_qds_mdio_write;
+ bus->reset = lx2160a_qds_mdio_reset;
+ strcpy(bus->name, dummy_mdio_name);
+ bus->priv = pmdio;
+
+ if (!mdio_register(bus))
+ return bus;
+
+ printf("No bus with name %s\n", dummy_mdio_name);
+ free(bus);
+ free(pmdio);
+ return NULL;
+}
+
+static inline void do_phy_config(const struct phy_config *phy_config)
+{
+ struct mii_dev *bus;
+ int i, phy_num, phy_address;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (!phy_config[i].dpmacid)
+ continue;
+
+ for (phy_num = 0;
+ phy_num < ARRAY_SIZE(phy_config[i].phy_address);
+ phy_num++) {
+ phy_address = phy_config[i].phy_address[phy_num];
+ if (phy_address == -1)
+ break;
+ wriop_set_phy_address(phy_config[i].dpmacid,
+ phy_num, phy_address);
+ }
+ /*Register the muxing front-ends to the MDIO buses*/
+ bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
+ phy_config[i].ioslot);
+ if (!bus)
+ printf("could not get bus for mdio %d ioslot %d\n",
+ phy_config[i].mdio_bus,
+ phy_config[i].ioslot);
+ else
+ wriop_set_mdio(phy_config[i].dpmacid, bus);
+ }
+}
+
+static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
+ char *env_dpmac)
+{
+ const char *ret;
+ size_t len;
+ u8 realbusnum, ioslot;
+ struct mii_dev *bus;
+ int phy_num;
+ char *phystr = "phy00";
+
+ /*search phy in dpmac arg*/
+ for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
+ sprintf(phystr, "phy%d", phy_num + 1);
+ ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
+ if (!ret) {
+ /*look for phy instead of phy1*/
+ if (!phy_num)
+ ret = hwconfig_subarg_f(arg_dpmacid, "phy",
+ &len, env_dpmac);
+ if (!ret)
+ continue;
+ }
+
+ if (len != 4 || strncmp(ret, "0x", 2))
+ printf("invalid phy format in %s variable.\n"
+ "specify phy%d for %s in hex format e.g. 0x12\n",
+ env_dpmac, phy_num + 1, arg_dpmacid);
+ else
+ wriop_set_phy_address(dpmac, phy_num,
+ simple_strtoul(ret, NULL, 16));
+ }
+
+ /*search mdio in dpmac arg*/
+ ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
+ if (ret)
+ realbusnum = *ret - '0';
+ else
+ realbusnum = EMI_NONE;
+
+ if (realbusnum) {
+ /*search io in dpmac arg*/
+ ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
+ if (ret)
+ ioslot = *ret - '0';
+ else
+ ioslot = IO_SLOT_NONE;
+ /*Register the muxing front-ends to the MDIO buses*/
+ bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
+ if (!bus)
+ printf("could not get bus for mdio %d ioslot %d\n",
+ realbusnum, ioslot);
+ else
+ wriop_set_mdio(dpmac, bus);
+ }
+}
+
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ struct memac_mdio_info mdio_info;
+ struct memac_mdio_controller *regs;
+ int i;
+ const char *ret;
+ char *env_dpmac;
+ char dpmacid[] = "dpmac00", srds[] = "00_00_00";
+ size_t len;
+ struct mii_dev *bus;
+ const struct phy_config *phy_config;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1, srds_s2, srds_s3;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ srds_s2 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+ srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+
+ srds_s3 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
+ srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
+
+ sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
+
+ regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = regs;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /*Register the EMI 1*/
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ mdio_info.regs = regs;
+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /*Register the EMI 2*/
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ /* "dpmac" environment variable can be used after
+ * defining "dpmac_override" in hwconfig environment variable.
+ */
+ if (hwconfig("dpmac_override")) {
+ env_dpmac = env_get("dpmac");
+ if (env_dpmac) {
+ ret = hwconfig_arg_f("srds", &len, env_dpmac);
+ if (ret) {
+ if (strncmp(ret, srds, strlen(srds))) {
+ printf("SERDES configuration changed.\n"
+ "previous: %.*s, current: %s.\n"
+ "update dpmac variable.\n",
+ (int)len, ret, srds);
+ }
+ } else {
+ printf("SERDES configuration not found.\n"
+ "Please add srds:%s in dpmac variable\n",
+ srds);
+ }
+
+ for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
+ /* Look for dpmac1 to dpmac24(current max) arg
+ * in dpmac environment variable
+ */
+ sprintf(dpmacid, "dpmac%d", i);
+ ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
+ if (ret)
+ do_dpmac_config(i, dpmacid, env_dpmac);
+ }
+ } else {
+ printf("Warning: environment dpmac not found.\n"
+ "DPAA network interfaces may not work\n");
+ }
+ } else {
+ /*Look for phy config for serdes1 in phy config table*/
+ phy_config = get_phy_config(srds_s1, serdes1_phy_config,
+ ARRAY_SIZE(serdes1_phy_config));
+ if (!phy_config) {
+ printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
+ __func__, srds_s1);
+ } else {
+ do_phy_config(phy_config);
+ }
+ phy_config = get_phy_config(srds_s2, serdes2_phy_config,
+ ARRAY_SIZE(serdes2_phy_config));
+ if (!phy_config) {
+ printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
+ __func__, srds_s2);
+ } else {
+ do_phy_config(phy_config);
+ }
+ phy_config = get_phy_config(srds_s3, serdes3_phy_config,
+ ARRAY_SIZE(serdes3_phy_config));
+ if (!phy_config) {
+ printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
+ __func__, srds_s3);
+ } else {
+ do_phy_config(phy_config);
+ }
+ }
+
+ if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
+ bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
+ if (!bus)
+ printf("could not get bus for RGMII1\n");
+ else
+ wriop_set_mdio(WRIOP1_DPMAC17, bus);
+ }
+
+ if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
+ wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
+ bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
+ if (!bus)
+ printf("could not get bus for RGMII2\n");
+ else
+ wriop_set_mdio(WRIOP1_DPMAC18, bus);
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+#ifdef CONFIG_PHY_AQUANTIA
+ /*
+ * Export functions to be used by AQ firmware
+ * upload application
+ */
+ gd->jt->strcpy = strcpy;
+ gd->jt->mdelay = mdelay;
+ gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+ gd->jt->phy_find_by_mask = phy_find_by_mask;
+ gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+ gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+#if defined(CONFIG_FSL_MC_ENET)
+int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
+{
+ int offset;
+ int ret;
+ char dpmac_str[] = "dpmacs@00";
+ const char *phy_string;
+
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
+
+ if (offset < 0) {
+ printf("dpmacs node not found in device tree\n");
+ return offset;
+ }
+
+ sprintf(dpmac_str, "dpmac@%x", dpmac_id);
+ debug("dpmac_str = %s\n", dpmac_str);
+
+ offset = fdt_subnode_offset(fdt, offset, dpmac_str);
+ if (offset < 0) {
+ printf("%s node not found in device tree\n", dpmac_str);
+ return offset;
+ }
+
+ ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
+ if (ret)
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+ phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
+ ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
+ phy_string);
+ if (ret)
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+
+ return ret;
+}
+
+int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
+{
+ char mdio_ioslot_str[] = "mdio@00";
+ char mdio_mux_str[] = "mdio-mux-0";
+ struct lx2160a_qds_mdio *priv;
+ int offset, mux_val;
+
+ /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
+ if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
+ strlen("LX2160A_QDS_MDIO")))
+ return -1;
+
+ /*Get the real MDIO bus num and ioslot info from bus's priv data*/
+ priv = mii_dev->priv;
+
+ debug("real_bus_num = %d, ioslot = %d\n",
+ priv->realbusnum, priv->ioslot);
+
+ sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
+ offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
+ if (offset < 0) {
+ printf("%s node not found under node %s in device tree\n",
+ mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
+ return offset;
+ }
+
+ mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
+ sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
+
+ offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
+ if (offset < 0) {
+ printf("%s node not found in device tree\n", mdio_ioslot_str);
+ return offset;
+ }
+
+ return offset;
+}
+
+int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
+ struct phy_device *phy_dev, int phandle)
+{
+ char phy_node_name[] = "ethernet-phy@00";
+ char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
+ int ret;
+
+ sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
+ debug("phy_node_name = %s\n", phy_node_name);
+
+ *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
+ if (*subnodeoffset <= 0) {
+ printf("Could not add subnode %s\n", phy_node_name);
+ return *subnodeoffset;
+ }
+
+ sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
+ phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
+ debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
+
+ ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
+ phy_id_compatible_str);
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+
+ if (phy_dev->is_c45) {
+ ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+ "ethernet-phy-ieee802.3-c45");
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+ } else {
+ ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
+ "ethernet-phy-ieee802.3-c22");
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+ }
+
+ ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+
+ ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
+ if (ret) {
+ printf("%d@%s %d\n", __LINE__, __func__, ret);
+ goto out;
+ }
+
+out:
+ if (ret)
+ fdt_del_node(fdt, *subnodeoffset);
+
+ return ret;
+}
+
+int fdt_fixup_board_phy(void *fdt)
+{
+ int fpga_offset, offset, subnodeoffset;
+ struct mii_dev *mii_dev;
+ struct list_head *mii_devs, *entry;
+ int ret, dpmac_id, phandle, i;
+ struct phy_device *phy_dev;
+ char ethname[ETH_NAME_LEN];
+ phy_interface_t phy_iface;
+
+ ret = 0;
+ /* we know FPGA is connected to i2c0, therefore search path directly,
+ * instead of compatible property, as it saves time
+ */
+ fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
+
+ if (fpga_offset < 0)
+ fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
+
+ if (fpga_offset < 0) {
+ printf("i2c@2000000/fpga node not found in device tree\n");
+ return fpga_offset;
+ }
+
+ phandle = fdt_alloc_phandle(fdt);
+ mii_devs = mdio_get_list_head();
+
+ list_for_each(entry, mii_devs) {
+ mii_dev = list_entry(entry, struct mii_dev, link);
+ debug("mii_dev name : %s\n", mii_dev->name);
+ offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
+ if (offset < 0)
+ continue;
+
+ // Look for phy devices attached to MDIO bus muxing front end
+ // and create their entries with compatible being the device id
+ for (i = 0; i < PHY_MAX_ADDR; i++) {
+ phy_dev = mii_dev->phymap[i];
+ if (!phy_dev)
+ continue;
+
+ // TODO: use sscanf instead of loop
+ dpmac_id = WRIOP1_DPMAC1;
+ while (dpmac_id < NUM_WRIOP_PORTS) {
+ phy_iface = wriop_get_enet_if(dpmac_id);
+ snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
+ dpmac_id,
+ phy_string_for_interface(phy_iface));
+ if (strcmp(ethname, phy_dev->dev->name) == 0)
+ break;
+ dpmac_id++;
+ }
+ if (dpmac_id == NUM_WRIOP_PORTS)
+ continue;
+
+ ret = fdt_create_phy_node(fdt, offset, i,
+ &subnodeoffset,
+ phy_dev, phandle);
+ if (ret)
+ break;
+
+ ret = fdt_fixup_dpmac_phy_handle(fdt,
+ dpmac_id, phandle);
+ if (ret) {
+ fdt_del_node(fdt, subnodeoffset);
+ break;
+ }
+ phandle++;
+ }
+
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+#endif // CONFIG_FSL_MC_ENET
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <malloc.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <exports.h>
+#include <asm/arch/fsl_serdes.h>
+#include <fsl-mc/fsl_mc.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
+{
+ int phy_reg;
+ u32 phy_id;
+
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
+ phy_id = (phy_reg & 0xffff) << 16;
+
+ phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
+ phy_id |= (phy_reg & 0xffff);
+
+ if (phy_id == PHY_UID_IN112525_S03)
+ return true;
+ else
+ return false;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ struct memac_mdio_info mdio_info;
+ struct memac_mdio_controller *reg;
+ int i, interface;
+ struct mii_dev *dev;
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_le32(&gur->rcwsr[28]) &
+ FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
+
+ /* Register the EMI 1 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
+ mdio_info.regs = reg;
+ mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
+
+ /* Register the EMI 2 */
+ fm_memac_mdio_init(bis, &mdio_info);
+
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ switch (srds_s1) {
+ case 19:
+ wriop_set_phy_address(WRIOP1_DPMAC2, 0,
+ CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0,
+ AQR107_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0,
+ AQR107_PHY_ADDR2);
+ if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
+ wriop_set_phy_address(WRIOP1_DPMAC5, 0,
+ INPHI_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC6, 0,
+ INPHI_PHY_ADDR1);
+ }
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC18, 0,
+ RGMII_PHY_ADDR2);
+ break;
+
+ case 18:
+ wriop_set_phy_address(WRIOP1_DPMAC7, 0,
+ CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC8, 0,
+ CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC9, 0,
+ CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC10, 0,
+ CORTINA_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC3, 0,
+ AQR107_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC4, 0,
+ AQR107_PHY_ADDR2);
+ if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
+ wriop_set_phy_address(WRIOP1_DPMAC5, 0,
+ INPHI_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC6, 0,
+ INPHI_PHY_ADDR1);
+ }
+ wriop_set_phy_address(WRIOP1_DPMAC17, 0,
+ RGMII_PHY_ADDR1);
+ wriop_set_phy_address(WRIOP1_DPMAC18, 0,
+ RGMII_PHY_ADDR2);
+ break;
+
+ default:
+ printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
+ srds_s1);
+ goto next;
+ }
+
+ for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_XGMII:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ case PHY_INTERFACE_MODE_25G_AUI:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ case PHY_INTERFACE_MODE_XLAUI:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+ for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
+ interface = wriop_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
+ wriop_set_mdio(i, dev);
+ break;
+ default:
+ break;
+ }
+ }
+
+next:
+ cpu_eth_init(bis);
+#endif /* CONFIG_FSL_MC_ENET */
+
+#ifdef CONFIG_PHY_AQUANTIA
+ /*
+ * Export functions to be used by AQ firmware
+ * upload application
+ */
+ gd->jt->strcpy = strcpy;
+ gd->jt->mdelay = mdelay;
+ gd->jt->mdio_get_current_dev = mdio_get_current_dev;
+ gd->jt->phy_find_by_mask = phy_find_by_mask;
+ gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
+ gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
+#endif
+ return pci_eth_init(bis);
+}
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#if defined(CONFIG_FSL_MC_ENET)
+ mc_env_boot();
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+int fdt_fixup_board_phy(void *fdt)
+{
+ int mdio_offset;
+ int ret;
+ struct mii_dev *dev;
+
+ ret = 0;
+
+ dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
+ if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
+ mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
+
+ if (mdio_offset < 0)
+ mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
+
+ if (mdio_offset < 0) {
+ printf("mdio@0x8B9700 node not found in dts\n");
+ return mdio_offset;
+ }
+
+ ret = fdt_setprop_string(fdt, mdio_offset, "status",
+ "disabled");
+ if (ret) {
+ printf("Could not set disable mdio@0x8B97000 %s\n",
+ fdt_strerror(ret));
+ return ret;
+ }
+ }
+
+ return ret;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <i2c.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ddr.h>
+#include <fsl_sec.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <efi_loader.h>
+#include <asm/arch/mmu.h>
+#include <hwconfig.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include "../common/qixis.h"
+#include "../common/vid.h"
+#include <fsl_immap.h>
+
+#ifdef CONFIG_EMC2305
+#include "../common/emc2305.h"
+#endif
+
+#ifdef CONFIG_TARGET_LX2160AQDS
+#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
+#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
+#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
+#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
+#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
+#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
+#define SDHC1_BASE_PMUX_DSPI 2
+#define SDHC2_BASE_PMUX_DSPI 2
+#define IIC5_PMUX_SPI3 3
+#endif /* CONFIG_TARGET_LX2160AQDS */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct pl01x_serial_platdata serial0 = {
+#if CONFIG_CONS_INDEX == 0
+ .base = CONFIG_SYS_SERIAL0,
+#elif CONFIG_CONS_INDEX == 1
+ .base = CONFIG_SYS_SERIAL1,
+#else
+#error "Unsupported console index value."
+#endif
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial0) = {
+ .name = "serial_pl01x",
+ .platdata = &serial0,
+};
+
+static struct pl01x_serial_platdata serial1 = {
+ .base = CONFIG_SYS_SERIAL1,
+ .type = TYPE_PL011,
+};
+
+U_BOOT_DEVICE(nxp_serial1) = {
+ .name = "serial_pl01x",
+ .platdata = &serial1,
+};
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void uart_get_clock(void)
+{
+ serial0.clock = get_serial_clock();
+ serial1.clock = get_serial_clock();
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+ i2c_early_init_f();
+#endif
+ /* get required clock for UART IP */
+ uart_get_clock();
+
+#ifdef CONFIG_EMC2305
+ select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
+ emc2305_init();
+ set_fan_speed(I2C_EMC2305_PWM);
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+#endif
+
+ fsl_lsch3_early_init_f();
+ return 0;
+}
+
+#if defined(CONFIG_TARGET_LX2160AQDS)
+void esdhc_dspi_status_fixup(void *blob)
+{
+ const char esdhc0_path[] = "/soc/esdhc@2140000";
+ const char esdhc1_path[] = "/soc/esdhc@2150000";
+ const char dspi0_path[] = "/soc/dspi@2100000";
+ const char dspi1_path[] = "/soc/dspi@2110000";
+ const char dspi2_path[] = "/soc/dspi@2120000";
+
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 sdhc1_base_pmux;
+ u32 sdhc2_base_pmux;
+ u32 iic5_pmux;
+
+ /* Check RCW field sdhc1_base_pmux to enable/disable
+ * esdhc0/dspi0 DT node
+ */
+ sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+ & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
+ sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
+
+ if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
+ do_fixup_by_path(blob, dspi0_path, "status", "okay",
+ sizeof("okay"), 1);
+ do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ } else {
+ do_fixup_by_path(blob, esdhc0_path, "status", "okay",
+ sizeof("okay"), 1);
+ do_fixup_by_path(blob, dspi0_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ }
+
+ /* Check RCW field sdhc2_base_pmux to enable/disable
+ * esdhc1/dspi1 DT node
+ */
+ sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
+ & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
+ sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
+
+ if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
+ do_fixup_by_path(blob, dspi1_path, "status", "okay",
+ sizeof("okay"), 1);
+ do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ } else {
+ do_fixup_by_path(blob, esdhc1_path, "status", "okay",
+ sizeof("okay"), 1);
+ do_fixup_by_path(blob, dspi1_path, "status", "disabled",
+ sizeof("disabled"), 1);
+ }
+
+ /* Check RCW field IIC5 to enable dspi2 DT node */
+ iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+ & FSL_CHASSIS3_IIC5_PMUX_MASK;
+ iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
+
+ if (iic5_pmux == IIC5_PMUX_SPI3) {
+ do_fixup_by_path(blob, dspi2_path, "status", "okay",
+ sizeof("okay"), 1);
+ }
+}
+#endif
+
+int esdhc_status_fixup(void *blob, const char *compat)
+{
+#if defined(CONFIG_TARGET_LX2160AQDS)
+ /* Enable esdhc and dspi DT nodes based on RCW fields */
+ esdhc_dspi_status_fixup(blob);
+#else
+ /* Enable both esdhc DT nodes for LX2160ARDB */
+ do_fixup_by_compat(blob, compat, "status", "okay",
+ sizeof("okay"), 1);
+#endif
+ return 0;
+}
+
+#if defined(CONFIG_VID)
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return select_i2c_ch_pca9547(channel);
+}
+
+int init_func_vid(void)
+{
+ if (adjust_vdd(0) < 0)
+ printf("core voltage not adjusted\n");
+
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ enum boot_src src = get_boot_src();
+ char buf[64];
+ u8 sw;
+#ifdef CONFIG_TARGET_LX2160AQDS
+ int clock;
+ static const char *const freq[] = {"100", "125", "156.25",
+ "161.13", "322.26", "", "", "",
+ "", "", "", "", "", "", "",
+ "100 separate SSCG"};
+#endif
+
+ cpu_name(buf);
+#ifdef CONFIG_TARGET_LX2160AQDS
+ printf("Board: %s-QDS, ", buf);
+#else
+ printf("Board: %s-RDB, ", buf);
+#endif
+
+ sw = QIXIS_READ(arch);
+ printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
+
+ if (src == BOOT_SOURCE_SD_MMC) {
+ puts("SD\n");
+ } else {
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
+ switch (sw) {
+ case 0:
+ case 4:
+ puts("FlexSPI DEV#0\n");
+ break;
+ case 1:
+ puts("FlexSPI DEV#1\n");
+ break;
+ case 2:
+ case 3:
+ puts("FlexSPI EMU\n");
+ break;
+ default:
+ printf("invalid setting, xmap: %d\n", sw);
+ break;
+ }
+ }
+#ifdef CONFIG_TARGET_LX2160AQDS
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ puts("SERDES1 Reference : ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = sw >> 4;
+ printf("Clock1 = %sMHz ", freq[clock]);
+ clock = sw & 0x0f;
+ printf("Clock2 = %sMHz", freq[clock]);
+
+ sw = QIXIS_READ(brdcfg[3]);
+ puts("\nSERDES2 Reference : ");
+ clock = sw >> 4;
+ printf("Clock1 = %sMHz ", freq[clock]);
+ clock = sw & 0x0f;
+ printf("Clock2 = %sMHz", freq[clock]);
+
+ sw = QIXIS_READ(brdcfg[12]);
+ puts("\nSERDES3 Reference : ");
+ clock = sw >> 4;
+ printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
+#else
+ printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+
+ puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
+ puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_TARGET_LX2160AQDS
+/*
+ * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
+ */
+u8 qixis_esdhc_detect_quirk(void)
+{
+ /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
+ * SDHC1 Card ID:
+ * Specifies the type of card installed in the SDHC1 adapter slot.
+ * 000= (reserved)
+ * 001= eMMC V4.5 adapter is installed.
+ * 010= SD/MMC 3.3V adapter is installed.
+ * 011= eMMC V4.4 adapter is installed.
+ * 100= eMMC V5.0 adapter is installed.
+ * 101= MMC card/Legacy (3.3V) adapter is installed.
+ * 110= SDCard V2/V3 adapter installed.
+ * 111= no adapter is installed.
+ */
+ return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
+ QIXIS_ESDHC_NO_ADAPTER);
+}
+
+int config_board_mux(void)
+{
+ u8 reg11, reg5, reg13;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 sdhc1_base_pmux;
+ u32 sdhc2_base_pmux;
+ u32 iic5_pmux;
+
+ /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
+ * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
+ * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
+ * Qixis and remote systems are isolated from the I2C1 bus.
+ * Processor connections are still available.
+ * SPI2 CS2_B controls EN25S64 SPI memory device.
+ * SPI3 CS2_B controls EN25S64 SPI memory device.
+ * EC2 connects to PHY #2 using RGMII protocol.
+ * CLK_OUT connects to FPGA for clock measurement.
+ */
+
+ reg5 = QIXIS_READ(brdcfg[5]);
+ reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
+ QIXIS_WRITE(brdcfg[5], reg5);
+
+ /* Check RCW field sdhc1_base_pmux
+ * esdhc0 : sdhc1_base_pmux = 0
+ * dspi0 : sdhc1_base_pmux = 2
+ */
+ sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+ & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
+ sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
+
+ if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
+ reg11 = QIXIS_READ(brdcfg[11]);
+ reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
+ QIXIS_WRITE(brdcfg[11], reg11);
+ } else {
+ /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
+ * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
+ * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
+ */
+ reg11 = QIXIS_READ(brdcfg[11]);
+ reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
+ QIXIS_WRITE(brdcfg[11], reg11);
+ }
+
+ /* Check RCW field sdhc2_base_pmux
+ * esdhc1 : sdhc2_base_pmux = 0 (default)
+ * dspi1 : sdhc2_base_pmux = 2
+ */
+ sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
+ & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
+ sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
+
+ if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
+ reg13 = QIXIS_READ(brdcfg[13]);
+ reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
+ QIXIS_WRITE(brdcfg[13], reg13);
+ } else {
+ reg13 = QIXIS_READ(brdcfg[13]);
+ reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
+ QIXIS_WRITE(brdcfg[13], reg13);
+ }
+
+ /* Check RCW field IIC5 to enable dspi2 DT nodei
+ * dspi2: IIC5 = 3
+ */
+ iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
+ & FSL_CHASSIS3_IIC5_PMUX_MASK;
+ iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
+
+ if (iic5_pmux == IIC5_PMUX_SPI3) {
+ /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
+ reg11 = QIXIS_READ(brdcfg[11]);
+ reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
+ QIXIS_WRITE(brdcfg[11], reg11);
+
+ /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
+ * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
+ * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
+ */
+ reg11 = QIXIS_READ(brdcfg[11]);
+ reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
+ QIXIS_WRITE(brdcfg[11], reg11);
+ } else {
+ /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
+ reg11 = QIXIS_READ(brdcfg[11]);
+ reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
+ QIXIS_WRITE(brdcfg[11], reg11);
+
+ /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
+ * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
+ * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
+ */
+ reg11 = QIXIS_READ(brdcfg[11]);
+ reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
+ QIXIS_WRITE(brdcfg[11], reg11);
+ }
+
+ return 0;
+}
+#else
+int config_board_mux(void)
+{
+ return 0;
+}
+#endif
+
+unsigned long get_board_sys_clk(void)
+{
+#ifdef CONFIG_TARGET_LX2160AQDS
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x03) {
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ }
+ return 100000000;
+#else
+ return 100000000;
+#endif
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+#ifdef CONFIG_TARGET_LX2160AQDS
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 100000000;
+#else
+ return 100000000;
+#endif
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_ENV_IS_NOWHERE
+ gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+#ifdef CONFIG_FSL_CAAM
+ sec_init();
+#endif
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ int i;
+ u64 ddr_size = 0;
+
+ puts("\nDDR ");
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ ddr_size += gd->bd->bi_dram[i].size;
+ print_size(ddr_size, "");
+ print_ddr_info(0);
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ config_board_mux();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+extern int fdt_fixup_board_phy(void *fdt);
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/soc/fsl-mc");
+
+ if (offset < 0)
+ offset = fdt_path_offset(fdt, "/fsl-mc");
+
+ if (offset < 0) {
+ printf("%s: fsl-mc node not found in device tree (error %d)\n",
+ __func__, offset);
+ return;
+ }
+
+ if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0)) {
+ fdt_status_okay(fdt, offset);
+ fdt_fixup_board_phy(fdt);
+ } else {
+ fdt_status_fail(fdt, offset);
+ }
+}
+
+void board_quiesce_devices(void)
+{
+ fsl_mc_ldpaa_exit(gd->bd);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ int i;
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the three GPP DDR banks */
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+#ifdef CONFIG_RESV_RAM
+ /* reduce size if reserved memory is within this bank */
+ if (gd->arch.resv_ram >= base[0] &&
+ gd->arch.resv_ram < base[0] + size[0])
+ size[0] = gd->arch.resv_ram - base[0];
+ else if (gd->arch.resv_ram >= base[1] &&
+ gd->arch.resv_ram < base[1] + size[1])
+ size[1] = gd->arch.resv_ram - base[1];
+ else if (gd->arch.resv_ram >= base[2] &&
+ gd->arch.resv_ram < base[2] + size[2])
+ size[2] = gd->arch.resv_ram - base[2];
+#endif
+
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+
+#ifdef CONFIG_USB
+ fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fsl_mc_fixup_iommu_map_entry(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+
+ return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+ int i, nr_of_cfgsw;
+
+ QIXIS_WRITE(cms[0], 0x00);
+ nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+ puts("DIP switch settings dump:\n");
+ for (i = 1; i <= nr_of_cfgsw; i++) {
+ QIXIS_WRITE(cms[0], i);
+ printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+ }
+}
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
#define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
-/* This is only needed until SPL gets OF support */
-#ifdef CONFIG_SPL_BUILD
-static const struct ns16550_platdata omap3logic_serial = {
- .base = OMAP34XX_UART1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(omap3logic_uart) = {
- "omap_serial",
- &omap3logic_serial
-};
-
-static const struct omap_hsmmc_plat omap3_logic_mmc0_platdata = {
- .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
- .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
- .cfg.f_min = 400000,
- .cfg.f_max = 52000000,
- .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
- .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
-};
-
-U_BOOT_DEVICE(omap3_logic_mmc0) = {
- .name = "omap_hsmmc",
- .platdata = &omap3_logic_mmc0_platdata,
-};
-
-#endif
-
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
--- /dev/null
+if TARGET_SIFIVE_FU540
+
+config SYS_BOARD
+ default "fu540"
+
+config SYS_VENDOR
+ default "sifive"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "sifive-fu540"
+
+config SYS_TEXT_BASE
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select GENERIC_RISCV
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CLK_SIFIVE
+ imply CLK_SIFIVE_FU540_PRCI
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply NET_RANDOM_ETHADDR
+ imply PHY_LIB
+ imply PHY_MSCC
+ imply SIFIVE_SERIAL
+
+endif
--- /dev/null
+SiFive FU540 BOARD
+M: Paul Walmsley <paul.walmsley@sifive.com>
+M: Palmer Dabbelt <palmer@sifive.com>
+M: Anup Patel <anup.patel@wdc.com>
+M: Atish Patra <atish.patra@wdc.com>
+S: Maintained
+F: board/sifive/fu540/
+F: include/configs/sifive-fu540.h
+F: configs/sifive_fu540_defconfig
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += fu540.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+
+int board_init(void)
+{
+ /* For now nothing to do here. */
+
+ return 0;
+}
char env_setting[64];
} expansion_config;
-static const struct ns16550_platdata beagle_serial = {
- .base = OMAP34XX_UART3,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(beagle_uart) = {
- "ns16550_serial",
- &beagle_serial
-};
-
/*
* Routine: board_init
* Description: Early hardware init.
DECLARE_GLOBAL_DATA_PTR;
-static const struct ns16550_platdata omap3_evm_serial = {
- .base = OMAP34XX_UART1,
- .reg_shift = 2,
- .clock = V_NS16550_CLK,
- .fcr = UART_FCR_DEFVAL,
-};
-
-U_BOOT_DEVICE(omap3_evm_uart) = {
- "ns16550_serial",
- &omap3_evm_serial
-};
-
static u32 omap3_evm_version;
u32 get_omap3_evm_rev(void)
}
}
#endif /* CONFIG_PCI_TEGRA */
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
+ gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
+}
gpio_direction_output(RGB_BACKLIGHTPWM_OE, 0);
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
+ gpio_direction_output(RGB_BACKLIGHT_GP, 0);
+}
#endif /* defined(CONFIG_VIDEO_IPUV3) */
int board_early_init_f(void)
#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
}
#endif /* CONFIG_PCI_TEGRA */
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_request(TEGRA_GPIO(V, 2), "BKL1_ON");
+ gpio_direction_output(TEGRA_GPIO(V, 2), 0);
+}
gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
gpio_direction_output(RGB_BACKLIGHT_GP, 1);
}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_direction_output(RGB_BACKLIGHTPWM_GP, 1);
+ gpio_direction_output(RGB_BACKLIGHT_GP, 0);
+}
#endif /* defined(CONFIG_VIDEO_IPUV3) */
int board_early_init_f(void)
}
#endif
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_direction_output(GPIO_PWM_A, 1);
+ gpio_direction_output(GPIO_BL_ON, 0);
+}
+
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
pinmux_tristate_disable(PMUX_PINGRP_SDC);
}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_request(TEGRA_GPIO(T, 4), "BL_ON");
+ gpio_direction_output(TEGRA_GPIO(T, 4), 0);
+}
#endif
udelay(5);
gpio_set_value(TEGRA_GPIO(DD, 0), 1);
}
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_request(TEGRA_GPIO(V, 2), "BL_ON");
+ gpio_direction_output(TEGRA_GPIO(V, 2), 0);
+}
#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
-#define USB_PEN_GPIO 83
+#define USB_PEN_GPIO 83
#define USB_CDET_GPIO 102
+#define PTC0_GPIO_45 45
static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
/* AXI */
}
}
#endif
+
+/*
+ * Backlight off before OS handover
+ */
+void board_preboot_os(void)
+{
+ gpio_request(PTC0_GPIO_45, "BL_ON");
+ gpio_direction_output(PTC0_GPIO_45, 0);
+}
be deleted. This command shows the variables that have special
flags.
+config CMD_NVEDIT_EFI
+ bool "env [set|print] -e - set/print UEFI variables"
+ depends on EFI_LOADER
+ default y
+ imply HEXDUMP
+ help
+ UEFI variables are encoded as some form of U-Boot variables.
+ If enabled, we are allowed to set/print UEFI variables using
+ "env" command with "-e" option without knowing details.
+
endmenu
menu "Memory commands"
displayed on a simple board-specific display. Implement
display_putc() to use it.
+config CMD_EFIDEBUG
+ bool "efidebug - display/configure UEFI environment"
+ depends on EFI_LOADER
+ default n
+ help
+ Enable the 'efidebug' command which provides a subset of UEFI
+ shell utility with simplified functionality. It will be useful
+ particularly for managing boot parameters as well as examining
+ various EFI status for debugging.
+
config CMD_LED
bool "led"
+ depends on LED
default y if LED
help
Enable the 'led' command which allows for control of LEDs supported
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
obj-$(CONFIG_CMD_EEPROM) += eeprom.o
obj-$(CONFIG_EFI_STUB) += efi.o
+obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o
obj-$(CONFIG_CMD_ELF) += elf.o
obj-$(CONFIG_HUSH_PARSER) += exit.o
obj-$(CONFIG_CMD_EXT4) += ext4.o
obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
obj-$(CONFIG_CMD_NAND) += nand.o
obj-$(CONFIG_CMD_NET) += net.o
+obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o
obj-$(CONFIG_CMD_ONENAND) += onenand.o
obj-$(CONFIG_CMD_OSD) += osd.o
obj-$(CONFIG_CMD_PART) += part.o
ifdef CONFIG_PCI
obj-$(CONFIG_CMD_PCI) += pci.o
endif
-obj-y += pcmcia.o
+obj-$(CONFIG_CMD_PCMCIA) += pcmcia.o
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
obj-$(CONFIG_CMD_PXE) += pxe.o
obj-$(CONFIG_CMD_WOL) += wol.o
return ret;
}
-static efi_status_t efi_do_enter(
- efi_handle_t image_handle, struct efi_system_table *st,
- EFIAPI efi_status_t (*entry)(
- efi_handle_t image_handle,
- struct efi_system_table *st))
-{
- efi_status_t ret = EFI_LOAD_ERROR;
-
- if (entry)
- ret = entry(image_handle, st);
- st->boottime->exit(image_handle, ret, 0, NULL);
- return ret;
-}
-
/*
* efi_carve_out_dt_rsv() - Carve out DT reserved memory ranges
*
struct efi_loaded_image_obj *image_obj = NULL;
struct efi_loaded_image *loaded_image_info = NULL;
- EFIAPI efi_status_t (*entry)(efi_handle_t image_handle,
- struct efi_system_table *st);
-
/*
* Special case for efi payload not loaded from disk, such as
* 'bootefi hello' or for example payload loaded directly into
goto err_prepare;
/* Load the EFI payload */
- entry = efi_load_pe(image_obj, efi, loaded_image_info);
- if (!entry) {
- ret = EFI_LOAD_ERROR;
+ ret = efi_load_pe(image_obj, efi, loaded_image_info);
+ if (ret != EFI_SUCCESS)
goto err_prepare;
- }
if (memdp) {
struct efi_device_path_memory *mdp = (void *)memdp;
"{ro,boot}(blob)0000000000000000");
/* Call our payload! */
- debug("%s: Jumping to 0x%p\n", __func__, entry);
-
- if (setjmp(&image_obj->exit_jmp)) {
- ret = image_obj->exit_status;
- goto err_prepare;
- }
-
- ret = efi_do_enter(&image_obj->header, &systab, entry);
+ debug("%s: Jumping to 0x%p\n", __func__, image_obj->entry);
+ ret = EFI_CALL(efi_start_image(&image_obj->header, NULL, NULL));
err_prepare:
/* image has returned, loaded-image obj goes *poof*: */
/**
* bootefi_test_prepare() - prepare to run an EFI test
*
- * This sets things up so we can call EFI functions. This involves preparing
- * the 'gd' pointer and setting up the load ed image data structures.
+ * Prepare to run a test as if it were provided by a loaded image.
*
- * @image_objp: loaded_image_infop: Pointer to a struct which will hold the
- * loaded image object. This struct will be inited by this function before
- * use.
- * @loaded_image_infop: Pointer to a struct which will hold the loaded image
- * info. This struct will be inited by this function before use.
- * @path: File path to the test being run (often just the test name with a
- * backslash before it
- * @test_func: Address of the test function that is being run
- * @load_options_path: U-Boot environment variable to use as load options
- * @return 0 if OK, -ve on error
+ * @image_objp: pointer to be set to the loaded image handle
+ * @loaded_image_infop: pointer to be set to the loaded image protocol
+ * @path: dummy file path used to construct the device path
+ * set in the loaded image protocol
+ * @load_options_path: name of a U-Boot environment variable. Its value is
+ * set as load options in the loaded image protocol.
+ * Return: status code
*/
static efi_status_t bootefi_test_prepare
(struct efi_loaded_image_obj **image_objp,
- struct efi_loaded_image **loaded_image_infop, const char *path,
- ulong test_func, const char *load_options_path)
+ struct efi_loaded_image **loaded_image_infop, const char *path,
+ const char *load_options_path)
{
+ efi_status_t ret;
+
/* Construct a dummy device path */
- bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
- (uintptr_t)test_func,
- (uintptr_t)test_func);
+ bootefi_device_path = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE, 0, 0);
if (!bootefi_device_path)
return EFI_OUT_OF_RESOURCES;
+
bootefi_image_path = efi_dp_from_file(NULL, 0, path);
- if (!bootefi_image_path)
- return EFI_OUT_OF_RESOURCES;
+ if (!bootefi_image_path) {
+ ret = EFI_OUT_OF_RESOURCES;
+ goto failure;
+ }
- return bootefi_run_prepare(load_options_path, bootefi_device_path,
- bootefi_image_path, image_objp,
- loaded_image_infop);
+ ret = bootefi_run_prepare(load_options_path, bootefi_device_path,
+ bootefi_image_path, image_objp,
+ loaded_image_infop);
+ if (ret == EFI_SUCCESS)
+ return ret;
+
+ efi_free_pool(bootefi_image_path);
+ bootefi_image_path = NULL;
+failure:
+ efi_free_pool(bootefi_device_path);
+ bootefi_device_path = NULL;
+ return ret;
}
#endif /* CONFIG_CMD_BOOTEFI_SELFTEST */
struct efi_loaded_image_obj *image_obj;
struct efi_loaded_image *loaded_image_info;
- if (bootefi_test_prepare(&image_obj, &loaded_image_info,
- "\\selftest", (uintptr_t)&efi_selftest,
- "efi_selftest"))
+ r = bootefi_test_prepare(&image_obj, &loaded_image_info,
+ "\\selftest", "efi_selftest");
+ if (r != EFI_SUCCESS)
return CMD_RET_FAILURE;
/* Execute the test */
- r = efi_selftest(&image_obj->header, &systab);
+ r = EFI_CALL(efi_selftest(&image_obj->header, &systab));
bootefi_run_finish(image_obj, loaded_image_info);
return r != EFI_SUCCESS;
} else
int len, val;
char *ptr;
- ptr = strchr (datestr,'.');
- len = strlen (datestr);
+ ptr = strchr(datestr, '.');
+ len = strlen(datestr);
/* Set seconds */
if (ptr) {
int sec;
- *ptr++ = '\0';
+ ptr++;
if ((len - (ptr - datestr)) != 2)
return (-1);
- len = strlen (datestr);
+ len -= 3;
if (cnvrt2 (ptr, &sec))
return (-1);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UEFI Shell-like command
+ *
+ * Copyright (c) 2018 AKASHI Takahiro, Linaro Limited
+ */
+
+#include <charset.h>
+#include <common.h>
+#include <command.h>
+#include <efi_loader.h>
+#include <environment.h>
+#include <exports.h>
+#include <malloc.h>
+#include <search.h>
+#include <linux/ctype.h>
+
+#define BS systab.boottime
+#define RT systab.runtime
+
+/**
+ * efi_get_device_handle_info() - get information of UEFI device
+ *
+ * @handle: Handle of UEFI device
+ * @dev_path_text: Pointer to text of device path
+ * Return: 0 on success, -1 on failure
+ *
+ * Currently return a formatted text of device path.
+ */
+static int efi_get_device_handle_info(efi_handle_t handle, u16 **dev_path_text)
+{
+ struct efi_device_path *dp;
+ efi_status_t ret;
+
+ ret = EFI_CALL(BS->open_protocol(handle, &efi_guid_device_path,
+ (void **)&dp, NULL /* FIXME */, NULL,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL));
+ if (ret == EFI_SUCCESS) {
+ *dev_path_text = efi_dp_str(dp);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+#define EFI_HANDLE_WIDTH ((int)sizeof(efi_handle_t) * 2)
+
+static const char spc[] = " ";
+static const char sep[] = "================";
+
+/**
+ * do_efi_show_devices() - show UEFI devices
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "devices" sub-command.
+ * Show all UEFI devices and their information.
+ */
+static int do_efi_show_devices(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ efi_handle_t *handles;
+ efi_uintn_t num, i;
+ u16 *dev_path_text;
+ efi_status_t ret;
+
+ ret = EFI_CALL(BS->locate_handle_buffer(ALL_HANDLES, NULL, NULL,
+ &num, &handles));
+ if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+
+ if (!num)
+ return CMD_RET_SUCCESS;
+
+ printf("Device%.*s Device Path\n", EFI_HANDLE_WIDTH - 6, spc);
+ printf("%.*s ====================\n", EFI_HANDLE_WIDTH, sep);
+ for (i = 0; i < num; i++) {
+ if (!efi_get_device_handle_info(handles[i], &dev_path_text)) {
+ printf("%p %ls\n", handles[i], dev_path_text);
+ efi_free_pool(dev_path_text);
+ }
+ }
+
+ EFI_CALL(BS->free_pool(handles));
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * efi_get_driver_handle_info() - get information of UEFI driver
+ *
+ * @handle: Handle of UEFI device
+ * @driver_name: Driver name
+ * @image_path: Pointer to text of device path
+ * Return: 0 on success, -1 on failure
+ *
+ * Currently return no useful information as all UEFI drivers are
+ * built-in..
+ */
+static int efi_get_driver_handle_info(efi_handle_t handle, u16 **driver_name,
+ u16 **image_path)
+{
+ struct efi_handler *handler;
+ struct efi_loaded_image *image;
+ efi_status_t ret;
+
+ /*
+ * driver name
+ * TODO: support EFI_COMPONENT_NAME2_PROTOCOL
+ */
+ *driver_name = NULL;
+
+ /* image name */
+ ret = efi_search_protocol(handle, &efi_guid_loaded_image, &handler);
+ if (ret != EFI_SUCCESS) {
+ *image_path = NULL;
+ return 0;
+ }
+
+ image = handler->protocol_interface;
+ *image_path = efi_dp_str(image->file_path);
+
+ return 0;
+}
+
+/**
+ * do_efi_show_drivers() - show UEFI drivers
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "drivers" sub-command.
+ * Show all UEFI drivers and their information.
+ */
+static int do_efi_show_drivers(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ efi_handle_t *handles;
+ efi_uintn_t num, i;
+ u16 *driver_name, *image_path_text;
+ efi_status_t ret;
+
+ ret = EFI_CALL(BS->locate_handle_buffer(
+ BY_PROTOCOL, &efi_guid_driver_binding_protocol,
+ NULL, &num, &handles));
+ if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+
+ if (!num)
+ return CMD_RET_SUCCESS;
+
+ printf("Driver%.*s Name Image Path\n",
+ EFI_HANDLE_WIDTH - 6, spc);
+ printf("%.*s ==================== ====================\n",
+ EFI_HANDLE_WIDTH, sep);
+ for (i = 0; i < num; i++) {
+ if (!efi_get_driver_handle_info(handles[i], &driver_name,
+ &image_path_text)) {
+ if (image_path_text)
+ printf("%p %-20ls %ls\n", handles[i],
+ driver_name, image_path_text);
+ else
+ printf("%p %-20ls <built-in>\n",
+ handles[i], driver_name);
+ EFI_CALL(BS->free_pool(driver_name));
+ EFI_CALL(BS->free_pool(image_path_text));
+ }
+ }
+
+ EFI_CALL(BS->free_pool(handles));
+
+ return CMD_RET_SUCCESS;
+}
+
+static const struct {
+ const char *text;
+ const efi_guid_t guid;
+} guid_list[] = {
+ {
+ "Device Path",
+ DEVICE_PATH_GUID,
+ },
+ {
+ "Device Path To Text",
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL_GUID,
+ },
+ {
+ "Device Path Utilities",
+ EFI_DEVICE_PATH_UTILITIES_PROTOCOL_GUID,
+ },
+ {
+ "Unicode Collation 2",
+ EFI_UNICODE_COLLATION_PROTOCOL2_GUID,
+ },
+ {
+ "Driver Binding",
+ EFI_DRIVER_BINDING_PROTOCOL_GUID,
+ },
+ {
+ "Simple Text Input",
+ EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID,
+ },
+ {
+ "Simple Text Input Ex",
+ EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL_GUID,
+ },
+ {
+ "Simple Text Output",
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID,
+ },
+ {
+ "Block IO",
+ BLOCK_IO_GUID,
+ },
+ {
+ "Simple File System",
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID,
+ },
+ {
+ "Loaded Image",
+ LOADED_IMAGE_PROTOCOL_GUID,
+ },
+ {
+ "GOP",
+ EFI_GOP_GUID,
+ },
+};
+
+/**
+ * get_guid_text - get string of protocol guid
+ * @guid: Protocol guid
+ * Return: String
+ *
+ * Return string for display to represent the protocol.
+ */
+static const char *get_guid_text(const efi_guid_t *guid)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(guid_list); i++)
+ if (!guidcmp(&guid_list[i].guid, guid))
+ break;
+
+ if (i != ARRAY_SIZE(guid_list))
+ return guid_list[i].text;
+ else
+ return NULL;
+}
+
+/**
+ * do_efi_show_handles() - show UEFI handles
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "dh" sub-command.
+ * Show all UEFI handles and their information, currently all protocols
+ * added to handle.
+ */
+static int do_efi_show_handles(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ efi_handle_t *handles;
+ efi_guid_t **guid;
+ efi_uintn_t num, count, i, j;
+ const char *guid_text;
+ efi_status_t ret;
+
+ ret = EFI_CALL(BS->locate_handle_buffer(ALL_HANDLES, NULL, NULL,
+ &num, &handles));
+ if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+
+ if (!num)
+ return CMD_RET_SUCCESS;
+
+ printf("Handle%.*s Protocols\n", EFI_HANDLE_WIDTH - 6, spc);
+ printf("%.*s ====================\n", EFI_HANDLE_WIDTH, sep);
+ for (i = 0; i < num; i++) {
+ printf("%p", handles[i]);
+ ret = EFI_CALL(BS->protocols_per_handle(handles[i], &guid,
+ &count));
+ if (ret || !count) {
+ putc('\n');
+ continue;
+ }
+
+ for (j = 0; j < count; j++) {
+ if (j)
+ printf(", ");
+ else
+ putc(' ');
+
+ guid_text = get_guid_text(guid[j]);
+ if (guid_text)
+ puts(guid_text);
+ else
+ printf("%pUl", guid[j]);
+ }
+ putc('\n');
+ }
+
+ EFI_CALL(BS->free_pool(handles));
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_efi_show_images() - show UEFI images
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "images" sub-command.
+ * Show all UEFI loaded images and their information.
+ */
+static int do_efi_show_images(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ efi_print_image_infos(NULL);
+
+ return CMD_RET_SUCCESS;
+}
+
+static const char * const efi_mem_type_string[] = {
+ [EFI_RESERVED_MEMORY_TYPE] = "RESERVED",
+ [EFI_LOADER_CODE] = "LOADER CODE",
+ [EFI_LOADER_DATA] = "LOADER DATA",
+ [EFI_BOOT_SERVICES_CODE] = "BOOT CODE",
+ [EFI_BOOT_SERVICES_DATA] = "BOOT DATA",
+ [EFI_RUNTIME_SERVICES_CODE] = "RUNTIME CODE",
+ [EFI_RUNTIME_SERVICES_DATA] = "RUNTIME DATA",
+ [EFI_CONVENTIONAL_MEMORY] = "CONVENTIONAL",
+ [EFI_UNUSABLE_MEMORY] = "UNUSABLE MEM",
+ [EFI_ACPI_RECLAIM_MEMORY] = "ACPI RECLAIM MEM",
+ [EFI_ACPI_MEMORY_NVS] = "ACPI NVS",
+ [EFI_MMAP_IO] = "IO",
+ [EFI_MMAP_IO_PORT] = "IO PORT",
+ [EFI_PAL_CODE] = "PAL",
+};
+
+static const struct efi_mem_attrs {
+ const u64 bit;
+ const char *text;
+} efi_mem_attrs[] = {
+ {EFI_MEMORY_UC, "UC"},
+ {EFI_MEMORY_UC, "UC"},
+ {EFI_MEMORY_WC, "WC"},
+ {EFI_MEMORY_WT, "WT"},
+ {EFI_MEMORY_WB, "WB"},
+ {EFI_MEMORY_UCE, "UCE"},
+ {EFI_MEMORY_WP, "WP"},
+ {EFI_MEMORY_RP, "RP"},
+ {EFI_MEMORY_XP, "WP"},
+ {EFI_MEMORY_NV, "NV"},
+ {EFI_MEMORY_MORE_RELIABLE, "REL"},
+ {EFI_MEMORY_RO, "RO"},
+ {EFI_MEMORY_RUNTIME, "RT"},
+};
+
+/**
+ * print_memory_attributes() - print memory map attributes
+ * @attributes: Attribute value
+ *
+ * Print memory map attributes
+ */
+static void print_memory_attributes(u64 attributes)
+{
+ int sep, i;
+
+ for (sep = 0, i = 0; i < ARRAY_SIZE(efi_mem_attrs); i++)
+ if (attributes & efi_mem_attrs[i].bit) {
+ if (sep) {
+ putc('|');
+ } else {
+ putc(' ');
+ sep = 1;
+ }
+ puts(efi_mem_attrs[i].text);
+ }
+}
+
+#define EFI_PHYS_ADDR_WIDTH (int)(sizeof(efi_physical_addr_t) * 2)
+
+/**
+ * do_efi_show_memmap() - show UEFI memory map
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "memmap" sub-command.
+ * Show UEFI memory map.
+ */
+static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct efi_mem_desc *memmap = NULL, *map;
+ efi_uintn_t map_size = 0;
+ const char *type;
+ int i;
+ efi_status_t ret;
+
+ ret = EFI_CALL(BS->get_memory_map(&map_size, memmap, NULL, NULL, NULL));
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ map_size += sizeof(struct efi_mem_desc); /* for my own */
+ ret = EFI_CALL(BS->allocate_pool(EFI_LOADER_DATA,
+ map_size, (void *)&memmap));
+ if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+ ret = EFI_CALL(BS->get_memory_map(&map_size, memmap,
+ NULL, NULL, NULL));
+ }
+ if (ret != EFI_SUCCESS) {
+ EFI_CALL(BS->free_pool(memmap));
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Type Start%.*s End%.*s Attributes\n",
+ EFI_PHYS_ADDR_WIDTH - 5, spc, EFI_PHYS_ADDR_WIDTH - 3, spc);
+ printf("================ %.*s %.*s ==========\n",
+ EFI_PHYS_ADDR_WIDTH, sep, EFI_PHYS_ADDR_WIDTH, sep);
+ for (i = 0, map = memmap; i < map_size / sizeof(*map); map++, i++) {
+ if (map->type < EFI_MAX_MEMORY_TYPE)
+ type = efi_mem_type_string[map->type];
+ else
+ type = "(unknown)";
+
+ printf("%-16s %.*llx-%.*llx", type,
+ EFI_PHYS_ADDR_WIDTH,
+ map->physical_start,
+ EFI_PHYS_ADDR_WIDTH,
+ map->physical_start + map->num_pages * EFI_PAGE_SIZE);
+
+ print_memory_attributes(map->attribute);
+ putc('\n');
+ }
+
+ EFI_CALL(BS->free_pool(memmap));
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_efi_boot_add() - set UEFI load option
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "boot add" sub-command.
+ * Create or change UEFI load option.
+ * - boot add <id> <label> <interface> <devnum>[:<part>] <file> <options>
+ */
+static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ int id;
+ char *endp;
+ char var_name[9];
+ u16 var_name16[9], *p;
+ efi_guid_t guid;
+ size_t label_len, label_len16;
+ u16 *label;
+ struct efi_device_path *device_path = NULL, *file_path = NULL;
+ struct efi_load_option lo;
+ void *data = NULL;
+ efi_uintn_t size;
+ int ret;
+
+ if (argc < 6 || argc > 7)
+ return CMD_RET_USAGE;
+
+ id = (int)simple_strtoul(argv[1], &endp, 16);
+ if (*endp != '\0' || id > 0xffff)
+ return CMD_RET_FAILURE;
+
+ sprintf(var_name, "Boot%04X", id);
+ p = var_name16;
+ utf8_utf16_strncpy(&p, var_name, 9);
+
+ guid = efi_global_variable_guid;
+
+ /* attributes */
+ lo.attributes = LOAD_OPTION_ACTIVE; /* always ACTIVE */
+
+ /* label */
+ label_len = strlen(argv[2]);
+ label_len16 = utf8_utf16_strnlen(argv[2], label_len);
+ label = malloc((label_len16 + 1) * sizeof(u16));
+ if (!label)
+ return CMD_RET_FAILURE;
+ lo.label = label; /* label will be changed below */
+ utf8_utf16_strncpy(&label, argv[2], label_len);
+
+ /* file path */
+ ret = efi_dp_from_name(argv[3], argv[4], argv[5], &device_path,
+ &file_path);
+ if (ret != EFI_SUCCESS) {
+ printf("Cannot create device path for \"%s %s\"\n",
+ argv[3], argv[4]);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+ lo.file_path = file_path;
+ lo.file_path_length = efi_dp_size(file_path)
+ + sizeof(struct efi_device_path); /* for END */
+
+ /* optional data */
+ lo.optional_data = (u8 *)(argc == 6 ? "" : argv[6]);
+
+ size = efi_serialize_load_option(&lo, (u8 **)&data);
+ if (!size) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ ret = EFI_CALL(RT->set_variable(var_name16, &guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, data));
+ ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
+out:
+ free(data);
+ efi_free_pool(device_path);
+ efi_free_pool(file_path);
+ free(lo.label);
+
+ return ret;
+}
+
+/**
+ * do_efi_boot_rm() - delete UEFI load options
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "boot rm" sub-command.
+ * Delete UEFI load options.
+ * - boot rm <id> ...
+ */
+static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ efi_guid_t guid;
+ int id, i;
+ char *endp;
+ char var_name[9];
+ u16 var_name16[9];
+ efi_status_t ret;
+
+ if (argc == 1)
+ return CMD_RET_USAGE;
+
+ guid = efi_global_variable_guid;
+ for (i = 1; i < argc; i++, argv++) {
+ id = (int)simple_strtoul(argv[1], &endp, 16);
+ if (*endp != '\0' || id > 0xffff)
+ return CMD_RET_FAILURE;
+
+ sprintf(var_name, "Boot%04X", id);
+ utf8_utf16_strncpy((u16 **)&var_name16, var_name, 9);
+
+ ret = EFI_CALL(RT->set_variable(var_name16, &guid, 0, 0, NULL));
+ if (ret) {
+ printf("cannot remove Boot%04X", id);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * show_efi_boot_opt_data() - dump UEFI load option
+ *
+ * @id: Load option number
+ * @data: Value of UEFI load option variable
+ *
+ * Decode the value of UEFI load option variable and print information.
+ */
+static void show_efi_boot_opt_data(int id, void *data)
+{
+ struct efi_load_option lo;
+ char *label, *p;
+ size_t label_len16, label_len;
+ u16 *dp_str;
+
+ efi_deserialize_load_option(&lo, data);
+
+ label_len16 = u16_strlen(lo.label);
+ label_len = utf16_utf8_strnlen(lo.label, label_len16);
+ label = malloc(label_len + 1);
+ if (!label)
+ return;
+ p = label;
+ utf16_utf8_strncpy(&p, lo.label, label_len16);
+
+ printf("Boot%04X:\n", id);
+ printf("\tattributes: %c%c%c (0x%08x)\n",
+ /* ACTIVE */
+ lo.attributes & LOAD_OPTION_ACTIVE ? 'A' : '-',
+ /* FORCE RECONNECT */
+ lo.attributes & LOAD_OPTION_FORCE_RECONNECT ? 'R' : '-',
+ /* HIDDEN */
+ lo.attributes & LOAD_OPTION_HIDDEN ? 'H' : '-',
+ lo.attributes);
+ printf("\tlabel: %s\n", label);
+
+ dp_str = efi_dp_str(lo.file_path);
+ printf("\tfile_path: %ls\n", dp_str);
+ efi_free_pool(dp_str);
+
+ printf("\tdata: %s\n", lo.optional_data);
+
+ free(label);
+}
+
+/**
+ * show_efi_boot_opt() - dump UEFI load option
+ *
+ * @id: Load option number
+ *
+ * Dump information defined by UEFI load option.
+ */
+static void show_efi_boot_opt(int id)
+{
+ char var_name[9];
+ u16 var_name16[9], *p;
+ efi_guid_t guid;
+ void *data = NULL;
+ efi_uintn_t size;
+ int ret;
+
+ sprintf(var_name, "Boot%04X", id);
+ p = var_name16;
+ utf8_utf16_strncpy(&p, var_name, 9);
+ guid = efi_global_variable_guid;
+
+ size = 0;
+ ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL));
+ if (ret == (int)EFI_BUFFER_TOO_SMALL) {
+ data = malloc(size);
+ ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
+ data));
+ }
+ if (ret == EFI_SUCCESS)
+ show_efi_boot_opt_data(id, data);
+ else if (ret == EFI_NOT_FOUND)
+ printf("Boot%04X: not found\n", id);
+
+ free(data);
+}
+
+/**
+ * show_efi_boot_dump() - dump all UEFI load options
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "boot dump" sub-command.
+ * Dump information of all UEFI load options defined.
+ * - boot dump
+ */
+static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ char regex[256];
+ char * const regexlist[] = {regex};
+ char *variables = NULL, *boot, *value;
+ int len;
+ int id;
+
+ if (argc > 1)
+ return CMD_RET_USAGE;
+
+ snprintf(regex, 256, "efi_.*-.*-.*-.*-.*_Boot[0-9A-F]+");
+
+ /* TODO: use GetNextVariableName? */
+ len = hexport_r(&env_htab, '\n', H_MATCH_REGEX | H_MATCH_KEY,
+ &variables, 0, 1, regexlist);
+
+ if (!len)
+ return CMD_RET_SUCCESS;
+
+ if (len < 0)
+ return CMD_RET_FAILURE;
+
+ boot = variables;
+ while (*boot) {
+ value = strstr(boot, "Boot") + 4;
+ id = (int)simple_strtoul(value, NULL, 16);
+ show_efi_boot_opt(id);
+ boot = strchr(boot, '\n');
+ if (!*boot)
+ break;
+ boot++;
+ }
+ free(variables);
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * show_efi_boot_order() - show order of UEFI load options
+ *
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Show order of UEFI load options defined by BootOrder variable.
+ */
+static int show_efi_boot_order(void)
+{
+ efi_guid_t guid;
+ u16 *bootorder = NULL;
+ efi_uintn_t size;
+ int num, i;
+ char var_name[9];
+ u16 var_name16[9], *p16;
+ void *data;
+ struct efi_load_option lo;
+ char *label, *p;
+ size_t label_len16, label_len;
+ efi_status_t ret;
+
+ guid = efi_global_variable_guid;
+ size = 0;
+ ret = EFI_CALL(RT->get_variable(L"BootOrder", &guid, NULL, &size,
+ NULL));
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ bootorder = malloc(size);
+ ret = EFI_CALL(RT->get_variable(L"BootOrder", &guid, NULL,
+ &size, bootorder));
+ }
+ if (ret == EFI_NOT_FOUND) {
+ printf("BootOrder not defined\n");
+ ret = CMD_RET_SUCCESS;
+ goto out;
+ } else if (ret != EFI_SUCCESS) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ num = size / sizeof(u16);
+ for (i = 0; i < num; i++) {
+ sprintf(var_name, "Boot%04X", bootorder[i]);
+ p16 = var_name16;
+ utf8_utf16_strncpy(&p16, var_name, 9);
+
+ size = 0;
+ ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
+ NULL));
+ if (ret != EFI_BUFFER_TOO_SMALL) {
+ printf("%2d: Boot%04X: (not defined)\n",
+ i + 1, bootorder[i]);
+ continue;
+ }
+
+ data = malloc(size);
+ if (!data) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+ ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
+ data));
+ if (ret != EFI_SUCCESS) {
+ free(data);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ efi_deserialize_load_option(&lo, data);
+
+ label_len16 = u16_strlen(lo.label);
+ label_len = utf16_utf8_strnlen(lo.label, label_len16);
+ label = malloc(label_len + 1);
+ if (!label) {
+ free(data);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+ p = label;
+ utf16_utf8_strncpy(&p, lo.label, label_len16);
+ printf("%2d: Boot%04X: %s\n", i + 1, bootorder[i], label);
+ free(label);
+
+ free(data);
+ }
+out:
+ free(bootorder);
+
+ return ret;
+}
+
+/**
+ * do_efi_boot_next() - manage UEFI BootNext variable
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "boot next" sub-command.
+ * Set BootNext variable.
+ * - boot next <id>
+ */
+static int do_efi_boot_next(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ u16 bootnext;
+ efi_uintn_t size;
+ char *endp;
+ efi_guid_t guid;
+ efi_status_t ret;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ bootnext = (u16)simple_strtoul(argv[1], &endp, 16);
+ if (*endp != '\0' || bootnext > 0xffff) {
+ printf("invalid value: %s\n", argv[1]);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ guid = efi_global_variable_guid;
+ size = sizeof(u16);
+ ret = EFI_CALL(RT->set_variable(L"BootNext", &guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, &bootnext));
+ ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
+out:
+ return ret;
+}
+
+/**
+ * do_efi_boot_order() - manage UEFI BootOrder variable
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "boot order" sub-command.
+ * Show order of UEFI load options, or change it in BootOrder variable.
+ * - boot order [<id> ...]
+ */
+static int do_efi_boot_order(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ u16 *bootorder = NULL;
+ efi_uintn_t size;
+ int id, i;
+ char *endp;
+ efi_guid_t guid;
+ efi_status_t ret;
+
+ if (argc == 1)
+ return show_efi_boot_order();
+
+ argc--;
+ argv++;
+
+ size = argc * sizeof(u16);
+ bootorder = malloc(size);
+ if (!bootorder)
+ return CMD_RET_FAILURE;
+
+ for (i = 0; i < argc; i++) {
+ id = (int)simple_strtoul(argv[i], &endp, 16);
+ if (*endp != '\0' || id > 0xffff) {
+ printf("invalid value: %s\n", argv[i]);
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ bootorder[i] = (u16)id;
+ }
+
+ guid = efi_global_variable_guid;
+ ret = EFI_CALL(RT->set_variable(L"BootOrder", &guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, bootorder));
+ ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
+out:
+ free(bootorder);
+
+ return ret;
+}
+
+static cmd_tbl_t cmd_efidebug_boot_sub[] = {
+ U_BOOT_CMD_MKENT(add, CONFIG_SYS_MAXARGS, 1, do_efi_boot_add, "", ""),
+ U_BOOT_CMD_MKENT(rm, CONFIG_SYS_MAXARGS, 1, do_efi_boot_rm, "", ""),
+ U_BOOT_CMD_MKENT(dump, CONFIG_SYS_MAXARGS, 1, do_efi_boot_dump, "", ""),
+ U_BOOT_CMD_MKENT(next, CONFIG_SYS_MAXARGS, 1, do_efi_boot_next, "", ""),
+ U_BOOT_CMD_MKENT(order, CONFIG_SYS_MAXARGS, 1, do_efi_boot_order,
+ "", ""),
+};
+
+/**
+ * do_efi_boot_opt() - manage UEFI load options
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "boot" sub-command.
+ * See above for details of sub-commands.
+ */
+static int do_efi_boot_opt(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ cmd_tbl_t *cp;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ argc--; argv++;
+
+ cp = find_cmd_tbl(argv[0], cmd_efidebug_boot_sub,
+ ARRAY_SIZE(cmd_efidebug_boot_sub));
+ if (!cp)
+ return CMD_RET_USAGE;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+static cmd_tbl_t cmd_efidebug_sub[] = {
+ U_BOOT_CMD_MKENT(boot, CONFIG_SYS_MAXARGS, 1, do_efi_boot_opt, "", ""),
+ U_BOOT_CMD_MKENT(devices, CONFIG_SYS_MAXARGS, 1, do_efi_show_devices,
+ "", ""),
+ U_BOOT_CMD_MKENT(drivers, CONFIG_SYS_MAXARGS, 1, do_efi_show_drivers,
+ "", ""),
+ U_BOOT_CMD_MKENT(dh, CONFIG_SYS_MAXARGS, 1, do_efi_show_handles,
+ "", ""),
+ U_BOOT_CMD_MKENT(images, CONFIG_SYS_MAXARGS, 1, do_efi_show_images,
+ "", ""),
+ U_BOOT_CMD_MKENT(memmap, CONFIG_SYS_MAXARGS, 1, do_efi_show_memmap,
+ "", ""),
+};
+
+/**
+ * do_efidebug() - display and configure UEFI environment
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success,
+ * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug command which allows us to display and
+ * configure UEFI environment.
+ * See above for details of sub-commands.
+ */
+static int do_efidebug(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ cmd_tbl_t *cp;
+ efi_status_t r;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ argc--; argv++;
+
+ /* Initialize UEFI drivers */
+ r = efi_init_obj_list();
+ if (r != EFI_SUCCESS) {
+ printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ r & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
+
+ cp = find_cmd_tbl(argv[0], cmd_efidebug_sub,
+ ARRAY_SIZE(cmd_efidebug_sub));
+ if (!cp)
+ return CMD_RET_USAGE;
+
+ return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char efidebug_help_text[] =
+ " - UEFI Shell-like interface to configure UEFI environment\n"
+ "\n"
+ "efidebug boot add <bootid> <label> <interface> <devnum>[:<part>] <file path> [<load options>]\n"
+ " - set UEFI BootXXXX variable\n"
+ " <load options> will be passed to UEFI application\n"
+ "efidebug boot rm <bootid#1> [<bootid#2> [<bootid#3> [...]]]\n"
+ " - delete UEFI BootXXXX variables\n"
+ "efidebug boot dump\n"
+ " - dump all UEFI BootXXXX variables\n"
+ "efidebug boot next <bootid>\n"
+ " - set UEFI BootNext variable\n"
+ "efidebug boot order [<bootid#1> [<bootid#2> [<bootid#3> [...]]]]\n"
+ " - set/show UEFI boot order\n"
+ "\n"
+ "efidebug devices\n"
+ " - show uefi devices\n"
+ "efidebug drivers\n"
+ " - show uefi drivers\n"
+ "efidebug dh\n"
+ " - show uefi handles\n"
+ "efidebug images\n"
+ " - show loaded images\n"
+ "efidebug memmap\n"
+ " - show uefi memory map\n";
+#endif
+
+U_BOOT_CMD(
+ efidebug, 10, 0, do_efidebug,
+ "Configure UEFI environment",
+ efidebug_help_text
+);
if (phdr->p_filesz != phdr->p_memsz)
memset(dst + phdr->p_filesz, 0x00,
phdr->p_memsz - phdr->p_filesz);
- flush_cache((unsigned long)dst, phdr->p_filesz);
+ flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
+ roundup(phdr->p_memsz, ARCH_DMA_MINALIGN));
++phdr;
}
if (phdr->p_filesz != phdr->p_memsz)
memset(dst + phdr->p_filesz, 0x00,
phdr->p_memsz - phdr->p_filesz);
- flush_cache((unsigned long)dst, phdr->p_filesz);
+ flush_cache(rounddown((unsigned long)dst, ARCH_DMA_MINALIGN),
+ roundup(phdr->p_memsz, ARCH_DMA_MINALIGN));
++phdr;
}
static int do_load_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+#ifdef CONFIG_CMD_BOOTEFI
efi_set_bootdev(argv[1], (argc > 2) ? argv[2] : "",
(argc > 4) ? argv[4] : "");
+#endif
return do_load(cmdtp, flag, argc, argv, FS_TYPE_ANY);
}
};
static void gpio_get_description(struct udevice *dev, const char *bank_name,
- int offset, int *flagsp)
+ int offset, int *flagsp, bool show_all)
{
char buf[80];
int ret;
ret = gpio_get_function(dev, offset, NULL);
if (ret < 0)
goto err;
- if (!(*flagsp & FLAG_SHOW_ALL) && ret == GPIOF_UNUSED)
+ if (!show_all && !(*flagsp & FLAG_SHOW_ALL) && ret == GPIOF_UNUSED)
return;
if ((*flagsp & FLAG_SHOW_BANK) && bank_name) {
if (*flagsp & FLAG_SHOW_NEWLINE) {
banklen = bank_name ? strlen(bank_name) : 0;
if (!gpio_name || !bank_name ||
- !strncmp(gpio_name, bank_name, banklen)) {
+ !strncasecmp(gpio_name, bank_name, banklen)) {
const char *p = NULL;
int offset;
if (gpio_name && *p) {
offset = simple_strtoul(p, NULL, 10);
gpio_get_description(dev, bank_name, offset,
- &flags);
+ &flags, true);
} else {
for (offset = 0; offset < num_bits; offset++) {
gpio_get_description(dev, bank_name,
- offset, &flags);
+ offset, &flags, false);
}
}
}
int rcode = 0;
int env_flag = H_HIDE_DOT;
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+ if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e')
+ return do_env_print_efi(cmdtp, flag, --argc, ++argv);
+#endif
+
if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'a') {
argc--;
argv++;
ENTRY e, *ep;
debug("Initial value for argc=%d\n", argc);
+
+#if CONFIG_IS_ENABLED(CMD_NVEDIT_EFI)
+ if (argc > 1 && argv[1][0] == '-' && argv[1][1] == 'e')
+ return do_env_set_efi(NULL, flag, --argc, ++argv);
+#endif
+
while (argc > 1 && **(argv + 1) == '-') {
char *arg = *++argv;
"env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] - import environment\n"
#endif
"env print [-a | name ...] - print environment\n"
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+ "env print -e [name ...] - print UEFI environment\n"
+#endif
#if defined(CONFIG_CMD_RUN)
"env run var [...] - run commands in an environment variable\n"
#endif
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
"env save - save environment\n"
+#endif
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+ "env set -e name [arg ...] - set UEFI variable; unset if 'arg' not specified\n"
#endif
"env set [-f] name [arg ...]\n";
#endif
printenv, CONFIG_SYS_MAXARGS, 1, do_env_print,
"print environment variables",
"[-a]\n - print [all] values of all environment variables\n"
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+ "printenv -e [name ...]\n"
+ " - print UEFI variable 'name' or all the variables\n"
+#endif
"printenv name ...\n"
" - print value of environment variable 'name'",
var_complete
U_BOOT_CMD_COMPLETE(
setenv, CONFIG_SYS_MAXARGS, 0, do_env_set,
"set environment variables",
- "[-f] name value ...\n"
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+ "-e name [value ...]\n"
+ " - set UEFI variable 'name' to 'value' ...'\n"
+ " - delete UEFI variable 'name' if 'value' not specified\n"
+#endif
+ "setenv [-f] name value ...\n"
" - [forcibly] set environment variable 'name' to 'value ...'\n"
"setenv [-f] name\n"
" - [forcibly] delete environment variable 'name'",
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Integrate UEFI variables to u-boot env interface
+ *
+ * Copyright (c) 2018 AKASHI Takahiro, Linaro Limited
+ */
+
+#include <charset.h>
+#include <common.h>
+#include <command.h>
+#include <efi_loader.h>
+#include <exports.h>
+#include <hexdump.h>
+#include <malloc.h>
+#include <linux/kernel.h>
+
+/*
+ * From efi_variable.c,
+ *
+ * Mapping between UEFI variables and u-boot variables:
+ *
+ * efi_$guid_$varname = {attributes}(type)value
+ */
+
+static const struct {
+ u32 mask;
+ char *text;
+} efi_var_attrs[] = {
+ {EFI_VARIABLE_NON_VOLATILE, "NV"},
+ {EFI_VARIABLE_BOOTSERVICE_ACCESS, "BS"},
+ {EFI_VARIABLE_RUNTIME_ACCESS, "RT"},
+ {EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS, "AW"},
+ {EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS, "AT"},
+};
+
+/**
+ * efi_dump_single_var() - show information about a UEFI variable
+ *
+ * @name: Name of the variable
+ * @guid: Vendor GUID
+ *
+ * Show information encoded in one UEFI variable
+ */
+static void efi_dump_single_var(u16 *name, efi_guid_t *guid)
+{
+ u32 attributes;
+ u8 *data;
+ efi_uintn_t size;
+ int count, i;
+ efi_status_t ret;
+
+ data = NULL;
+ size = 0;
+ ret = EFI_CALL(efi_get_variable(name, guid, &attributes, &size, data));
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ data = malloc(size);
+ if (!data)
+ goto out;
+
+ ret = EFI_CALL(efi_get_variable(name, guid, &attributes, &size,
+ data));
+ }
+ if (ret == EFI_NOT_FOUND) {
+ printf("Error: \"%ls\" not defined\n", name);
+ goto out;
+ }
+ if (ret != EFI_SUCCESS)
+ goto out;
+
+ printf("%ls:", name);
+ for (count = 0, i = 0; i < ARRAY_SIZE(efi_var_attrs); i++)
+ if (attributes & efi_var_attrs[i].mask) {
+ if (count)
+ putc('|');
+ else
+ putc(' ');
+ count++;
+ puts(efi_var_attrs[i].text);
+ }
+ printf(", DataSize = 0x%zx\n", size);
+ print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, data, size, true);
+
+ return;
+out:
+ free(data);
+}
+
+/**
+ * efi_dump_vars() - show information about named UEFI variables
+ *
+ * @argc: Number of arguments (variables)
+ * @argv: Argument (variable name) array
+ * Return: CMD_RET_SUCCESS on success, or CMD_RET_RET_FAILURE
+ *
+ * Show information encoded in named UEFI variables
+ */
+static int efi_dump_vars(int argc, char * const argv[])
+{
+ u16 *var_name16, *p;
+ efi_uintn_t buf_size, size;
+
+ buf_size = 128;
+ var_name16 = malloc(buf_size);
+ if (!var_name16)
+ return CMD_RET_FAILURE;
+
+ for (; argc > 0; argc--, argv++) {
+ size = (utf8_utf16_strlen(argv[0]) + 1) * sizeof(u16);
+ if (buf_size < size) {
+ buf_size = size;
+ p = realloc(var_name16, buf_size);
+ if (!p) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
+ var_name16 = p;
+ }
+
+ p = var_name16;
+ utf8_utf16_strcpy(&p, argv[0]);
+
+ efi_dump_single_var(var_name16,
+ (efi_guid_t *)&efi_global_variable_guid);
+ }
+
+ free(var_name16);
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * efi_dump_vars() - show information about all the UEFI variables
+ *
+ * Return: CMD_RET_SUCCESS on success, or CMD_RET_RET_FAILURE
+ *
+ * Show information encoded in all the UEFI variables
+ */
+static int efi_dump_var_all(void)
+{
+ u16 *var_name16, *p;
+ efi_uintn_t buf_size, size;
+ efi_guid_t guid;
+ efi_status_t ret;
+
+ buf_size = 128;
+ var_name16 = malloc(buf_size);
+ if (!var_name16)
+ return CMD_RET_FAILURE;
+
+ var_name16[0] = 0;
+ for (;;) {
+ size = buf_size;
+ ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16,
+ &guid));
+ if (ret == EFI_NOT_FOUND)
+ break;
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ buf_size = size;
+ p = realloc(var_name16, buf_size);
+ if (!p) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
+ var_name16 = p;
+ ret = EFI_CALL(efi_get_next_variable_name(&size,
+ var_name16,
+ &guid));
+ }
+ if (ret != EFI_SUCCESS) {
+ free(var_name16);
+ return CMD_RET_FAILURE;
+ }
+
+ efi_dump_single_var(var_name16, &guid);
+ }
+
+ free(var_name16);
+
+ return CMD_RET_SUCCESS;
+}
+
+/**
+ * do_env_print_efi() - show information about UEFI variables
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, or CMD_RET_RET_FAILURE
+ *
+ * This function is for "env print -e" or "printenv -e" command:
+ * => env print -e [var [...]]
+ * If one or more variable names are specified, show information
+ * named UEFI variables, otherwise show all the UEFI variables.
+ */
+int do_env_print_efi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ efi_status_t ret;
+
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
+
+ if (argc > 1)
+ /* show specified UEFI variables */
+ return efi_dump_vars(--argc, ++argv);
+
+ /* enumerate and show all UEFI variables */
+ return efi_dump_var_all();
+}
+
+/**
+ * append_value() - encode UEFI variable's value
+ * @bufp: Buffer of encoded UEFI variable's value
+ * @sizep: Size of buffer
+ * @data: data to be encoded into the value
+ * Return: 0 on success, -1 otherwise
+ *
+ * Interpret a given data string and append it to buffer.
+ * Buffer will be realloc'ed if necessary.
+ *
+ * Currently supported formats are:
+ * =0x0123...: Hexadecimal number
+ * =H0123...: Hexadecimal-byte array
+ * ="...", =S"..." or <string>:
+ * String
+ */
+static int append_value(char **bufp, size_t *sizep, char *data)
+{
+ char *tmp_buf = NULL, *new_buf = NULL, *value;
+ unsigned long len = 0;
+
+ if (!strncmp(data, "=0x", 2)) { /* hexadecimal number */
+ union {
+ u8 u8;
+ u16 u16;
+ u32 u32;
+ u64 u64;
+ } tmp_data;
+ unsigned long hex_value;
+ void *hex_ptr;
+
+ data += 3;
+ len = strlen(data);
+ if ((len & 0x1)) /* not multiple of two */
+ return -1;
+
+ len /= 2;
+ if (len > 8)
+ return -1;
+ else if (len > 4)
+ len = 8;
+ else if (len > 2)
+ len = 4;
+
+ /* convert hex hexadecimal number */
+ if (strict_strtoul(data, 16, &hex_value) < 0)
+ return -1;
+
+ tmp_buf = malloc(len);
+ if (!tmp_buf)
+ return -1;
+
+ if (len == 1) {
+ tmp_data.u8 = hex_value;
+ hex_ptr = &tmp_data.u8;
+ } else if (len == 2) {
+ tmp_data.u16 = hex_value;
+ hex_ptr = &tmp_data.u16;
+ } else if (len == 4) {
+ tmp_data.u32 = hex_value;
+ hex_ptr = &tmp_data.u32;
+ } else {
+ tmp_data.u64 = hex_value;
+ hex_ptr = &tmp_data.u64;
+ }
+ memcpy(tmp_buf, hex_ptr, len);
+ value = tmp_buf;
+
+ } else if (!strncmp(data, "=H", 2)) { /* hexadecimal-byte array */
+ data += 2;
+ len = strlen(data);
+ if (len & 0x1) /* not multiple of two */
+ return -1;
+
+ len /= 2;
+ tmp_buf = malloc(len);
+ if (!tmp_buf)
+ return -1;
+
+ if (hex2bin((u8 *)tmp_buf, data, len) < 0)
+ return -1;
+
+ value = tmp_buf;
+ } else { /* string */
+ if (!strncmp(data, "=\"", 2) || !strncmp(data, "=S\"", 3)) {
+ if (data[1] == '"')
+ data += 2;
+ else
+ data += 3;
+ value = data;
+ len = strlen(data) - 1;
+ if (data[len] != '"')
+ return -1;
+ } else {
+ value = data;
+ len = strlen(data);
+ }
+ }
+
+ new_buf = realloc(*bufp, *sizep + len);
+ if (!new_buf)
+ goto out;
+
+ memcpy(new_buf + *sizep, value, len);
+ *bufp = new_buf;
+ *sizep += len;
+
+out:
+ free(tmp_buf);
+
+ return 0;
+}
+
+/**
+ * do_env_print_efi() - set UEFI variable
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, or CMD_RET_RET_FAILURE
+ *
+ * This function is for "env set -e" or "setenv -e" command:
+ * => env set -e var [value ...]]
+ * Encode values specified and set given UEFI variable.
+ * If no value is specified, delete the variable.
+ */
+int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *var_name, *value = NULL;
+ efi_uintn_t size = 0;
+ u16 *var_name16 = NULL, *p;
+ size_t len;
+ efi_guid_t guid;
+ efi_status_t ret;
+
+ if (argc == 1)
+ return CMD_RET_USAGE;
+
+ /* Initialize EFI drivers */
+ ret = efi_init_obj_list();
+ if (ret != EFI_SUCCESS) {
+ printf("Error: Cannot initialize UEFI sub-system, r = %lu\n",
+ ret & ~EFI_ERROR_MASK);
+ return CMD_RET_FAILURE;
+ }
+
+ var_name = argv[1];
+ if (argc == 2) {
+ /* delete */
+ value = NULL;
+ size = 0;
+ } else { /* set */
+ argc -= 2;
+ argv += 2;
+
+ for ( ; argc > 0; argc--, argv++)
+ if (append_value(&value, &size, argv[0]) < 0) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+ }
+
+ len = utf8_utf16_strnlen(var_name, strlen(var_name));
+ var_name16 = malloc((len + 1) * 2);
+ if (!var_name16) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+ p = var_name16;
+ utf8_utf16_strncpy(&p, var_name, len + 1);
+
+ guid = efi_global_variable_guid;
+ ret = EFI_CALL(efi_set_variable(var_name16, &guid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, value));
+ ret = (ret == EFI_SUCCESS ? CMD_RET_SUCCESS : CMD_RET_FAILURE);
+out:
+ free(value);
+ free(var_name16);
+
+ return ret;
+}
This is the string of commands that will be used as bootcmd and if
AUTOBOOT is set, automatically run.
+config USE_PREBOOT
+ bool "Enable preboot"
+ help
+ When this option is enabled, the existence of the environment
+ variable "preboot" will be checked immediately before starting the
+ CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
+ entering interactive mode.
+
+ This feature is especially useful when "preboot" is automatically
+ generated or modified. For example, the boot code can modify the
+ "preboot" when a user holds down a certain combination of keys.
+
+config PREBOOT
+ string "preboot default value"
+ depends on USE_PREBOOT
+ help
+ This is the default of "preboot" environment variable.
+
menu "Console"
config MENU
All Messages with a loglevel smaller than the console loglevel will
be compiled in. The loglevels are defined as follows:
- 0 (KERN_EMERG) system is unusable
- 1 (KERN_ALERT) action must be taken immediately
- 2 (KERN_CRIT) critical conditions
- 3 (KERN_ERR) error conditions
- 4 (KERN_WARNING) warning conditions
- 5 (KERN_NOTICE) normal but significant condition
- 6 (KERN_INFO) informational
- 7 (KERN_DEBUG) debug-level messages
+ 0 - emergency
+ 1 - alert
+ 2 - critical
+ 3 - error
+ 4 - warning
+ 5 - note
+ 6 - info
+ 7 - debug
+ 8 - debug content
+ 9 - debug hardware I/O
config SPL_LOGLEVEL
int
higher than this will be ignored. If possible log statements below
this level will be discarded at build time. Levels:
- 0 - panic
- 1 - critical
- 2 - error
- 3 - warning
- 4 - note
- 5 - info
- 6 - detail
+ 0 - emergency
+ 1 - alert
+ 2 - critical
+ 3 - error
+ 4 - warning
+ 5 - note
+ 6 - info
7 - debug
+ 8 - debug content
+ 9 - debug hardware I/O
config SPL_LOG_MAX_LEVEL
int "Maximum log level to record in SPL"
higher than this will be ignored. If possible log statements below
this level will be discarded at build time. Levels:
- 0 - panic
- 1 - critical
- 2 - error
- 3 - warning
- 4 - note
- 5 - info
- 6 - detail
+ 0 - emergency
+ 1 - alert
+ 2 - critical
+ 3 - error
+ 4 - warning
+ 5 - note
+ 6 - info
7 - debug
+ 8 - debug content
+ 9 - debug hardware I/O
config TPL_LOG_MAX_LEVEL
int "Maximum log level to record in TPL"
higher than this will be ignored. If possible log statements below
this level will be discarded at build time. Levels:
- 0 - panic
- 1 - critical
- 2 - error
- 3 - warning
- 4 - note
- 5 - info
- 6 - detail
+ 0 - emergency
+ 1 - alert
+ 2 - critical
+ 3 - error
+ 4 - warning
+ 5 - note
+ 6 - info
+ 7 - debug
+ 8 - debug content
+ 9 - debug hardware I/O
+
+config LOG_DEFAULT_LEVEL
+ int "Default logging level to display"
+ default 6
+ help
+ This is the default logging level set when U-Boot starts. It can
+ be adjusted later using the 'log level' command. Note that setting
+ this to a value abnove LOG_MAX_LEVEL will be ineffective, since the
+ higher levels are not compiled in to U-Boot.
+
+ 0 - emergency
+ 1 - alert
+ 2 - critical
+ 3 - error
+ 4 - warning
+ 5 - note
+ 6 - info
7 - debug
+ 8 - debug content
+ 9 - debug hardware I/O
config LOG_CONSOLE
bool "Allow log output to the console"
}
gd->flags |= GD_FLG_LOG_READY;
if (!gd->default_log_level)
- gd->default_log_level = LOGL_INFO;
+ gd->default_log_level = CONFIG_LOG_DEFAULT_LEVEL;
gd->log_fmt = LOGF_DEFAULT;
return 0;
is y. If this is not set, SPL will move on to other available
boot media to find a suitable image.
+config SPL_LEGACY_IMAGE_CRC_CHECK
+ bool "Check CRC of Legacy images"
+ depends on SPL_LEGACY_IMAGE_SUPPORT
+ select SPL_CRC32_SUPPORT
+ help
+ Enable this to check the CRC of Legacy images. While this increases
+ reliability, it affects both code size and boot duration.
+ If disabled, Legacy images are booted if the image magic and size
+ are correct, without further integrity checks.
+
config SPL_SYS_MALLOC_SIMPLE
bool
prompt "Only use malloc_simple functions in the SPL"
config SPL_CRC32_SUPPORT
bool "Support CRC32"
- depends on SPL_FIT
+ default y if SPL_LEGACY_IMAGE_SUPPORT
help
- Enable this to support CRC32 in FIT images within SPL. This is a
- 32-bit checksum value that can be used to verify images. This is
- the least secure type of checksum, suitable for detected
- accidental image corruption. For secure applications you should
- consider SHA1 or SHA256.
+ Enable this to support CRC32 in uImages or FIT images within SPL.
+ This is a 32-bit checksum value that can be used to verify images.
+ For FIT images, this is the least secure type of checksum, suitable
+ for detected accidental image corruption. For secure applications you
+ should consider SHA1 or SHA256.
config SPL_MD5_SUPPORT
bool "Support MD5"
#ifdef CONFIG_SPL_LEGACY_IMAGE_SUPPORT
u32 header_size = sizeof(struct image_header);
+#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
+ /* check uImage header CRC */
+ if (!image_check_hcrc(header)) {
+ puts("SPL: Image header CRC check failed!\n");
+ return -EINVAL;
+ }
+#endif
+
if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) {
/*
* On some system (e.g. powerpc), the load-address and
spl_image->size = image_get_data_size(header) +
header_size;
}
+#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
+ /* store uImage data length and CRC to check later */
+ spl_image->dcrc_data = image_get_load(header);
+ spl_image->dcrc_length = image_get_data_size(header);
+ spl_image->dcrc = image_get_dcrc(header);
+#endif
+
spl_image->os = image_get_os(header);
spl_image->name = image_get_name(header);
debug(SPL_TPL_PROMPT
static int spl_load_image(struct spl_image_info *spl_image,
struct spl_image_loader *loader)
{
+ int ret;
struct spl_boot_device bootdev;
bootdev.boot_device = loader->boot_device;
bootdev.boot_device_name = NULL;
- return loader->load_image(spl_image, &bootdev);
+ ret = loader->load_image(spl_image, &bootdev);
+#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
+ if (!ret && spl_image->dcrc_length) {
+ /* check data crc */
+ ulong dcrc = crc32_wd(0, (unsigned char *)spl_image->dcrc_data,
+ spl_image->dcrc_length, CHUNKSZ_CRC32);
+ if (dcrc != spl_image->dcrc) {
+ puts("SPL: Image data CRC check failed!\n");
+ ret = -EINVAL;
+ }
+ }
+#endif
+ return ret;
}
/**
#if defined(CONFIG_SPL_SYS_MALLOC_SIMPLE) && CONFIG_VAL(SYS_MALLOC_F_LEN)
if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
+ debug("SPL malloc() before relocation used 0x%lx bytes (%ld KB)\n",
+ gd->malloc_ptr, gd->malloc_ptr / 1024);
ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
gd->malloc_base = ptr;
gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
-CONFIG_SPL_SPI_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
CONFIG_SATAPWR="PC3"
+CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="AM3517_EVM # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL_LOAD_FIT=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-# CONFIG_BLK is not set
+CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY=y
CONFIG_PIPE3_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_ARMV7_LPAE=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_IMAGE_POST_PROCESS=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_SCSI_AHCI=y
-# CONFIG_BLK is not set
+CONFIG_DWC_AHCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_PHY=y
CONFIG_PIPE3_PHY=y
CONFIG_OMAP_USB2_PHY=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_PALMAS=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PALMAS=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_WDT_BCM6345=y
-CONFIG_REGEX=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_WDT_BCM6345=y
-CONFIG_REGEX=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
-# CONFIG_NETDEVICES is not set
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_NAND=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
-# CONFIG_NETDEVICES is not set
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
-# CONFIG_NETDEVICES is not set
+CONFIG_DRIVER_TI_CPSW=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM33XX=y
+CONFIG_SYS_MPUCLK=1000
CONFIG_TARGET_BRXRE1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_BOOTDELAY=-2
-# CONFIG_CONSOLE_MUX is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
+# CONFIG_EXPERT is not set
+# CONFIG_FIT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=0
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev 1; run b_default"
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_GO is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_UNZIP=y
+CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
CONFIG_CMD_USB=y
# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-brxre1"
+CONFIG_OF_SPL_REMOVE_PROPS=""
CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
# CONFIG_OMAP_WATCHDOG is not set
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_EFI_LOADER is not set
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
-# CONFIG_REGEX is not set
CONFIG_OF_LIBFDT=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="tegra30-cardhu"
CONFIG_SPL_DM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0xFFF00000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x2400
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SYS_NS16550=y
+CONFIG_SOUND=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_CMD_DHRYSTONE=y
CONFIG_TPM=y
+# CONFIG_EFI_LOADER is not set
CONFIG_X86=y
CONFIG_SYS_TEXT_BASE=0xFFE00000
-CONFIG_SYS_MALLOC_F_LEN=0x1a00
+CONFIG_SYS_MALLOC_F_LEN=0x1c00
CONFIG_DEBUG_UART_BOARD_INIT=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_LOG_DEFAULT_LEVEL=7
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_TPM=y
CONFIG_CMD_TPM_TEST=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_SYS_NS16550=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_SOUND_RT5677=y
CONFIG_SPI=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_MTD=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_DM_PMIC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_GADGET=y
CONFIG_SPL_DM=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
CONFIG_CONSOLE_SCROLL_LINES=5
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_TARGET_DA850EVM=y
CONFIG_DA850_LOWLEVEL=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="USE_NOR,DIRECT_NOR_BOOT"
CONFIG_BOOTDELAY=3
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="edison"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_CPU=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_HOST_ETHER=y
CONFIG_IDENT_STRING="hikey"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=6
+CONFIG_BOOTDELAY=10
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 root=/dev/mmcblk0p9 rw"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_INTERFACE="mmc"
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frwy"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
-# CONFIG_BLK is not set
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AIOT=y
CONFIG_SYS_TEXT_BASE=0x40010000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_MISC_INIT_R=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_MISC_INIT_R=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_STORAGE=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_USB=y
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x40100000
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_MMC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-lpuart"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPI=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_ENV_IS_NOWHERE=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT_VERBOSE=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_TEXT_BASE=0x20100000
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
# CONFIG_SYS_MALLOC_F is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_TEXT_BASE=0x30100000
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SYS_TEXT_BASE=0x20100000
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYS_TEXT_BASE=0x30100000
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_SYS_TEXT_BASE=0x20100000
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SECURE_BOOT=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_SYS_TEXT_BASE=0x20100000
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_TFABOOT=y
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT_VERBOSE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_DM_SCSI=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_SECURE_BOOT=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_E1000=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160AQDS=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_CORTINA=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_SECURE_BOOT=y
+CONFIG_EMC2305=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_CORTINA=y
+CONFIG_E1000=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_SOFTWARE_EXP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_LX2160ARDB=y
+CONFIG_SYS_TEXT_BASE=0x82000000
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_EMC2305=y
+CONFIG_TFABOOT=y
+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+CONFIG_AHCI=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_CACHE=y
+CONFIG_MP=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-rdb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SATA_CEVA=y
+CONFIG_FSL_CAAM=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_PHY_AQUANTIA=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_CORTINA=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-CONFIG_EFI_PARTITION=y
# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_EFI_PARTITION=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS5=y
-CONFIG_BOARD_TYPES=y
CONFIG_IDENT_STRING=" for ODROID-XU3/XU4/HC1/HC2"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_TYPES=y
CONFIG_SYS_PROMPT="ODROID-XU3 # "
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_CMD_DFU=y
CONFIG_ADC=y
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x5000000
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_TARGET_ODROID=y
-CONFIG_BOARD_TYPES=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=8
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_MISC_INIT_R=y
+CONFIG_BOARD_TYPES=y
CONFIG_SYS_PROMPT="Odroid # "
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_THOR_DOWNLOAD=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_S3C24X0=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-35xx-devkit"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+# CONFIG_SPL_POWER_SUPPORT is not set
CONFIG_SYS_PROMPT="OMAP Logic # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
-# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-35xx-devkit"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_BEAGLE=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="BeagleBoard # "
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x280000
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GREEN=2
CONFIG_LED_STATUS_CMD=y
CONFIG_TWL4030_LED=y
+CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SPI=y
+CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_VIDEO_OMAP3=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
-CONFIG_SPL_OF_LIBFDT=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_EVM=y
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x400
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x280000
# CONFIG_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_OF_TRANSLATE=y
# CONFIG_SPL_BLK is not set
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_USB_ETHER=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
-CONFIG_SPL_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP Logic # "
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ARM=y
+# CONFIG_SPL_USE_ARCH_MEMCPY is not set
+# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TI_COMMON_CMD_OPTIONS=y
-# CONFIG_SPL_GPIO_SUPPORT is not set
-CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_OMAP3_LOGIC=y
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+# CONFIG_SPL_FS_EXT4 is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+# CONFIG_SPL_POWER_SUPPORT is not set
CONFIG_SYS_PROMPT="OMAP Logic # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-som-lv-37xx-devkit"
# CONFIG_ENV_IS_IN_FAT is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
-# CONFIG_REGEX is not set
CONFIG_OF_LIBFDT=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881977
-CONFIG_MMC0_CD_PIN="PF6"
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
CONFIG_DFU_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-000"
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_TEGRA186_BPMP_I2C=y
CONFIG_DWC_ETH_QOS=y
CONFIG_E1000=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000-500"
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_TEGRA186_BPMP_I2C=y
CONFIG_DWC_ETH_QOS=y
CONFIG_E1000=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_DM_VIDEO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_S3C24X0=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_DEFAULT_DEVICE_TREE="tegra20-seaboard"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
+CONFIG_SYS_I2C_TEGRA=y
+CONFIG_TEGRA_KEYBOARD=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
--- /dev/null
+CONFIG_RISCV=y
+CONFIG_TARGET_SIFIVE_FU540=y
+CONFIG_RISCV_SMODE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_MII=y
+CONFIG_OF_PRIOR_STAGE=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="tegra30-tec-ng"
CONFIG_SPL_DM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_DM_VIDEO=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_S3C24X0=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_LIB_HW_RAND=y
CONFIG_DFU_MMC=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_S3C24X0=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_THOR=y
-# CONFIG_REGEX is not set
CONFIG_LIB_HW_RAND=y
CONFIG_DEFAULT_DEVICE_TREE="tegra20-trimslice"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SPL_DM=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_RTL8169=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
CONFIG_LOGLEVEL=6
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_NR_DRAM_BANKS=3
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="env exist ${bootdev}preboot && run ${bootdev}preboot"
CONFIG_LOGLEVEL=6
CONFIG_CMD_CONFIG=y
CONFIG_CMD_IMLS=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_I2C_TEGRA=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="NVIDIA"
CONFIG_USB_GADGET_VENDOR_NUM=0x0955
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_TEGRA=y
CONFIG_USB_ULPI_VIEWPORT=y
CONFIG_USB_ULPI=y
CONFIG_USB_KEYBOARD=y
The above have SPL versions also, e.g. CONFIG_SPL_MAX_LOG_LEVEL.
+Temporary logging within a single file
+--------------------------------------
+
+Sometimes it is useful to turn on logging just in one file. You can use this:
+
+ #define LOG_DEBUG
+
+to enable building in of all logging statements in a single file. Put it at
+the top of the file, before any #includes.
+
+To actually get U-Boot to output this you need to also set the default logging
+level - e.g. set CONFIG_LOG_DEFAULT_LEVEL to 7 (LOGL_DEBUG) or more. Otherwise
+debug output is suppressed and will not be generated.
+
+
+Convenience functions
+---------------------
+
+A number of convenience functions are available to shorten the code needed
+for logging:
+
+ log_err(_fmt...)
+ log_warning(_fmt...)
+ log_notice(_fmt...)
+ log_info(_fmt...)
+ log_debug(_fmt...)
+ log_content(_fmt...)
+ log_io(_fmt...)
+
+With these the log level is implicit in the name. The category is set by
+LOG_CATEGORY, which you can only define once per file, above all #includes:
+
+ #define LOG_CATEGORY LOGC_ALLOC
+
+or
+
+ #define LOG_CATEGORY UCLASS_SPI
+
+Remember that all uclasses IDs are log categories too.
+
+
Log commands
------------
log_core(level, format_string, ...) - category LOGC_CORE
log_dt(level, format_string, ...) - category LOGC_DT
-Convenience functions to support a category defined for a single file, for
-example:
-
- #define LOG_CATEGORY UCLASS_USB
-
-all of these can use LOG_CATEGORY as the category, and a log level
-corresponding to the function name:
-
- logc(level, format_string, ...)
-
More logging destinations:
device - goes to a device (e.g. serial)
--- /dev/null
+FU540-C000 RISC-V SoC
+=====================
+The FU540-C000 is the world’s first 4+1 64-bit RISC‑V SoC from SiFive.
+
+The HiFive Unleashed development platform is based on FU540-C000 and capable
+of running Linux.
+
+Mainline support
+================
+The support for following drivers are already enabled:
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+
+TODO:
+1. SPI driver is still missing. So MMC card can't be used in U-Boot as of now.
+2. U-Boot expects the serial console device entry to be present under /chosen
+ DT node. Example:
+ chosen {
+ stdout-path = "/soc/serial@10010000:115200";
+ };
+
+ Without a serial console U-Boot will panic.
+
+Building
+========
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation enviornment variable.
+ a. export ARCH=riscv
+ b. export CROSS_COMPILE=<riscv64 toolchain prefix>
+3. make sifive_fu540_defconfig
+4. make
+
+Flashing
+========
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage (M-mode) firmware/bootloader (e.g OpenSBI or BBL) is required to
+load the u-boot.bin into memory and provide runtime services. The u-boot.bin
+can be given as a payload to the prior stage (M-mode) firmware/bootloader.
+
+The description of steps required to build the firmware is beyond the scope of
+this document. Please refer OpenSBI or BBL documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+(Note: BBL git repo is at https://github.com/riscv/riscv-pk.git)
+
+Once the prior stage firmware/bootloader binary is generated, it should be
+copied to the first partition of the sdcard.
+
+sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
+
+Booting
+=======
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+===========================================
+U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
+
+CPU: rv64imafdc
+Model: sifive,hifive-unleashed-a00
+DRAM: 8 GiB
+In: serial@10010000
+Out: serial@10010000
+Err: serial@10010000
+Net:
+Warning: ethernet@10090000 (eth0) using random MAC address - b6:75:4d:48:50:94
+eth0: ethernet@10090000
+Hit any key to stop autoboot: 0
+=> version
+U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
+
+riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
+GNU ld (GNU Binutils) 2.31.1
+=>
+===============================================================================
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage.
+
+==========================================================================
+=> setenv ethaddr 70:B3:D5:92:F0:C2
+=> setenv ipaddr 10.196.157.189
+=> setenv serverip 10.11.143.218
+=> setenv gatewayip 10.196.156.1
+=> setenv netmask 255.255.252.0
+=> bdinfo
+boot_params = 0x0000000000000000
+DRAM bank = 0x0000000000000000
+-> start = 0x0000000080000000
+-> size = 0x0000000200000000
+relocaddr = 0x00000000fff90000
+reloc off = 0x000000007fd90000
+ethaddr = 70:B3:D5:92:F0:C2
+IP addr = 10.196.157.189
+baudrate = 115200 bps
+=> tftpboot uImage
+ethernet@10090000: PHY present at 0
+ethernet@10090000: Starting autonegotiation...
+ethernet@10090000: Autonegotiation complete
+ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3800)
+Using ethernet@10090000 device
+TFTP from server 10.11.143.218; our IP address is 10.196.157.189; sending through gateway 10.196.156.1
+Filename 'uImage'.
+Load address: 0x80200000
+Loading: #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ #################################################################
+ ##########################################################
+ 2.5 MiB/s
+done
+Bytes transferred = 14939132 (e3f3fc hex)
+=> bootm 0x80200000 - 0x82200000
+## Booting kernel from Legacy Image at 80200000 ...
+ Image Name: Linux
+ Image Type: RISC-V Linux Kernel Image (uncompressed)
+ Data Size: 14939068 Bytes = 14.2 MiB
+ Load Address: 80200000
+ Entry Point: 80200000
+ Verifying Checksum ... OK
+## Flattened Device Tree blob at 82200000
+ Booting using the fdt blob at 0x82200000
+ Loading Kernel Image ... OK
+ Using Device Tree in place at 0000000082200000, end 0000000082205c69
+
+Starting kernel ...
+
+[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+[ 0.000000] Linux version 5.0.0-rc1-00020-g4b51f736 (atish@jedi-01) (gcc version 7.2.0 (GCC)) #262 SMP Mon Jan 21 17:39:27 PST 2019
+[ 0.000000] initrd not found or empty - disabling initrd
+[ 0.000000] Zone ranges:
+[ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
+[ 0.000000] Normal [mem 0x0000000100000000-0x000027ffffffffff]
+[ 0.000000] Movable zone start for each node
+[ 0.000000] Early memory node ranges
+[ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
+[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+[ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
+[ 0.000000] CPU with hartid=0 has a non-okay status of "masked"
+[ 0.000000] CPU with hartid=0 has a non-okay status of "masked"
+[ 0.000000] elf_hwcap is 0x112d
+[ 0.000000] percpu: Embedded 15 pages/cpu @(____ptrval____) s29720 r0 d31720 u61440
+[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
+[ 0.000000] Kernel command line: earlyprintk
+[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
+[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
+[ 0.000000] Sorting __ex_table...
+[ 0.000000] Memory: 8178760K/8386560K available (3309K kernel code, 248K rwdata, 872K rodata, 9381K init, 763K bss, 207800K reserved, 0K cma-reserved)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+[ 0.000000] rcu: Hierarchical RCU implementation.
+[ 0.000000] rcu: RCU event tracing is enabled.
+[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
+[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+[ 0.000000] plic: mapped 53 interrupts to 4 (out of 9) handlers.
+[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+[ 0.000008] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+[ 0.000221] Console: colour dummy device 80x25
+[ 0.000902] printk: console [tty0] enabled
+[ 0.000963] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=10000)
+[ 0.001034] pid_max: default: 32768 minimum: 301
+[ 0.001541] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.001912] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.003542] rcu: Hierarchical SRCU implementation.
+[ 0.004347] smp: Bringing up secondary CPUs ...
+[ 1.040259] CPU1: failed to come online
+[ 2.080483] CPU2: failed to come online
+[ 3.120699] CPU3: failed to come online
+[ 3.120765] smp: Brought up 1 node, 1 CPU
+[ 3.121923] devtmpfs: initialized
+[ 3.124649] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
+[ 3.124727] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.125346] random: get_random_u32 called from bucket_table_alloc+0x72/0x172 with crng_init=0
+[ 3.125578] NET: Registered protocol family 16
+[ 3.126400] sifive-u54-prci 10000000.prci: Registered U54 core clocks
+[ 3.126649] sifive-gemgxl-mgmt 100a0000.cadence-gemgxl-mgmt: Registered clock switch 'cadence-gemgxl-mgmt'
+[ 3.135572] vgaarb: loaded
+[ 3.135858] SCSI subsystem initialized
+[ 3.136193] usbcore: registered new interface driver usbfs
+[ 3.136266] usbcore: registered new interface driver hub
+[ 3.136348] usbcore: registered new device driver usb
+[ 3.136446] pps_core: LinuxPPS API ver. 1 registered
+[ 3.136484] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.136575] PTP clock support registered
+[ 3.137256] clocksource: Switched to clocksource riscv_clocksource
+[ 3.142711] NET: Registered protocol family 2
+[ 3.143322] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes)
+[ 3.143634] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
+[ 3.145799] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
+[ 3.149121] TCP: Hash tables configured (established 65536 bind 65536)
+[ 3.149591] UDP hash table entries: 4096 (order: 5, 131072 bytes)
+[ 3.150094] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
+[ 3.150781] NET: Registered protocol family 1
+[ 3.230693] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+[ 3.241224] io scheduler mq-deadline registered
+[ 3.241269] io scheduler kyber registered
+[ 3.242143] sifive_gpio 10060000.gpio: SiFive GPIO chip registered 16 GPIOs
+[ 3.242357] pwm-sifivem 10020000.pwm: Unable to find controller clock
+[ 3.242439] pwm-sifivem 10021000.pwm: Unable to find controller clock
+[ 3.243228] xilinx-pcie 2000000000.pci: PCIe Link is DOWN
+[ 3.243289] xilinx-pcie 2000000000.pci: host bridge /soc/pci@2000000000 ranges:
+[ 3.243360] xilinx-pcie 2000000000.pci: No bus range found for /soc/pci@2000000000, using [bus 00-ff]
+[ 3.243447] xilinx-pcie 2000000000.pci: MEM 0x40000000..0x5fffffff -> 0x40000000
+[ 3.243591] xilinx-pcie 2000000000.pci: PCI host bridge to bus 0000:00
+[ 3.243636] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.243676] pci_bus 0000:00: root bus resource [mem 0x40000000-0x5fffffff]
+[ 3.276547] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.277689] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 39, base_baud = 0) is a SiFive UART v0
+[ 3.786963] printk: console [ttySIF0] enabled
+[ 3.791504] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 40, base_baud = 0) is a SiFive UART v0
+[ 3.801251] sifive_spi 10040000.spi: mapped; irq=41, cs=1
+[ 3.806362] m25p80 spi0.0: unrecognized JEDEC id bytes: 9d, 70, 19
+[ 3.812084] m25p80: probe of spi0.0 failed with error -2
+[ 3.817453] sifive_spi 10041000.spi: mapped; irq=42, cs=4
+[ 3.823027] sifive_spi 10050000.spi: mapped; irq=43, cs=1
+[ 3.828604] libphy: Fixed MDIO Bus: probed
+[ 3.832623] macb: GEM doesn't support hardware ptp.
+[ 3.837196] libphy: MACB_mii_bus: probed
+[ 4.041156] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
+[ 4.055779] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 12 (70:b3:d5:92:f0:c2)
+[ 4.065780] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+[ 4.072033] ehci-pci: EHCI PCI platform driver
+[ 4.076521] usbcore: registered new interface driver usb-storage
+[ 4.082843] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
+[ 4.127465] mmc_spi spi2.0: SD/MMC host mmc0, no DMA, no WP, no poweroff
+[ 4.133645] usbcore: registered new interface driver usbhid
+[ 4.138980] usbhid: USB HID core driver
+[ 4.143017] NET: Registered protocol family 17
+[ 4.147885] pwm-sifivem 10020000.pwm: SiFive PWM chip registered 4 PWMs
+[ 4.153945] pwm-sifivem 10021000.pwm: SiFive PWM chip registered 4 PWMs
+[ 4.186407] Freeing unused kernel memory: 9380K
+[ 4.190224] This architecture does not have kernel memory protection.
+[ 4.196609] Run /init as init process
+Starting logging: OK
+Starting mdev...
+[ 4.303785] mmc0: host does not support reading read-only switch, assuming write-enable
+[ 4.311109] mmc0: new SDHC card on SPI
+[ 4.317103] mmcblk0: mmc0:0000 SS08G 7.40 GiB
+[ 4.386471] mmcblk0: p1 p2
+sort: /sys/devices/platform/Fixed: No such file or directory
+modprobe: can't change directory to '/lib/modules': No such file or directory
+Initializing random[ 4.759075] random: dd: uninitialized urandom read (512 bytes read)
+ number generator... done.
+Starting network...
+udhcpc (v1.24.2) started
+Sending discover...
+Sending discover...
+[ 7.927510] macb 10090000.ethernet eth0: link up (1000/Full)
+Sending discover...
+Sending select for 10.196.157.190...
+Lease of 10.196.157.190 obtained, lease time 499743
+deleting routers
+adding dns 10.86.1.1
+adding dns 10.86.2.1
+/etc/init.d/S50dropbear
+Starting dropbear sshd: [ 12.772393] random: dropbear: uninitialized urandom read (32 bytes read)
+OK
+
+Welcome to Buildroot
+buildroot login:
images {
kernel {
- description = "U-Boot mainline";
+ description = "U-Boot mainline ";
type = "kernel_noload";
arch = "arm";
os = "linux";
--- /dev/null
+Binding for simple fixed factor rate clock sources.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "fixed-factor-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- clock-div: fixed divider.
+- clock-mult: fixed multiplier.
+- clocks: parent clock.
+
+Optional properties:
+- clock-output-names : From common clock binding.
+
+Example:
+ clock {
+ compatible = "fixed-factor-clock";
+ clocks = <&parentclk>;
+ #clock-cells = <0>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
--- /dev/null
+Texas Instruments' K3 AM654 DDRSS
+=================================
+
+K3 based AM654 devices has DDR memory subsystem that comprises
+Synopys DDR controller, Synopsis DDR phy and wrapper logic to
+integrate these blocks into the device. This DDR subsystem
+provides an interface to external SDRAM devices. This DDRSS driver
+adds support for the initialization of the external SDRAM devices by
+configuring the DDRSS registers and using the buitin PHY
+initialization routines.
+
+DDRSS device node:
+==================
+Required properties:
+--------------------
+- compatible: Shall be: "ti,am654-ddrss"
+- reg-names ss - Map the sub system wrapper logic region
+ ctl - Map the controller region
+ phy - Map the PHY region
+- reg: Contains the register map per reg-names.
+- power-domains: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the DDRSS device id
+ value. This property is as per the binding,
+ doc/device-tree-bindings/power/ti,sci-pm-domain.txt
+- clocks: Must contain an entry for enabling DDR clock. Should
+ be defined as per the appropriate clock bindings consumer
+ usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
+
+
+Optional Properties:
+--------------------
+- clock-frequency: Frequency at which DDR pll should be locked.
+ If not provided, default frequency will be used.
+
+Example (AM65x):
+================
+ memory-controller: memory-controller@298e000 {
+ compatible = "ti,am654-ddrss";
+ reg = <0x0298e000 0x200>,
+ <0x02980000 0x4000>,
+ <0x02988000 0x2000>;
+ reg-names = "ss", "ctl", "phy";
+ clocks = <&k3_clks 20 0>;
+ power-domains = <&k3_pds 20>;
+ u-boot,dm-spl;
+ };
--- /dev/null
+ST, stm32 flexible memory controller Drive
+Required properties:
+- compatible : "st,stm32-fmc"
+- reg : fmc controller base address
+- clocks : fmc controller clock
+u-boot,dm-pre-reloc: flag to initialize memory before relocation.
+
+on-board sdram memory attributes:
+- st,sdram-control : parameters for sdram configuration, in this order:
+ number of columns
+ number of rows
+ memory width
+ number of intenal banks in memory
+ cas latency
+ read burst enable or disable
+ read pipe delay
+
+- st,sdram-timing: timings for sdram, in this order:
+ tmrd
+ txsr
+ tras
+ trc
+ trp
+ trcd
+
+There is device tree include file at :
+include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
+parameters as MACROS.
+
+Example:
+ fmc: fmc@A0000000 {
+ compatible = "st,stm32-fmc";
+ reg = <0xA0000000 0x1000>;
+ clocks = <&rcc 0 64>;
+ u-boot,dm-pre-reloc;
+ };
+
+ &fmc {
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* sdram memory configuration from sdram datasheet */
+ bank1: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+ CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+ TRCD_18>;
+ };
+
+ /* sdram memory configuration from sdram datasheet */
+ bank2: bank@1 {
+ st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
+ CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
+ TRCD_18>;
+ };
+ }
--- /dev/null
+ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
+
+--------------------
+Required properties:
+--------------------
+- compatible : Should be "st,stm32mp1-ddr"
+- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
+- clocks : controller clocks handle
+- clock-names : associated controller clock names
+ the "ddrphyc" clock is used to check the DDR frequency
+ at phy level according the expected value in "mem-speed" field
+
+the next attributes are DDR parameters, they are generated by DDR tools
+included in STM32 Cube tool
+
+info attributes:
+----------------
+- st,mem-name : name for DDR configuration, simple string for information
+- st,mem-speed : DDR expected speed for the setting in MHz
+- st,mem-size : DDR mem size in byte
+
+
+controlleur attributes:
+-----------------------
+- st,ctl-reg : controleur values depending of the DDR type
+ (DDR3/LPDDR2/LPDDR3)
+ for STM32MP15x: 25 values are requested in this order
+ MSTR
+ MRCTRL0
+ MRCTRL1
+ DERATEEN
+ DERATEINT
+ PWRCTL
+ PWRTMG
+ HWLPCTL
+ RFSHCTL0
+ RFSHCTL3
+ CRCPARCTL0
+ ZQCTL0
+ DFITMG0
+ DFITMG1
+ DFILPCFG0
+ DFIUPD0
+ DFIUPD1
+ DFIUPD2
+ DFIPHYMSTR
+ ODTMAP
+ DBG0
+ DBG1
+ DBGCMD
+ POISONCFG
+ PCCFG
+
+- st,ctl-timing : controleur values depending of frequency and timing parameter
+ of DDR
+ for STM32MP15x: 12 values are requested in this order
+ RFSHTMG
+ DRAMTMG0
+ DRAMTMG1
+ DRAMTMG2
+ DRAMTMG3
+ DRAMTMG4
+ DRAMTMG5
+ DRAMTMG6
+ DRAMTMG7
+ DRAMTMG8
+ DRAMTMG14
+ ODTCFG
+
+- st,ctl-map : controleur values depending of address mapping
+ for STM32MP15x: 9 values are requested in this order
+ ADDRMAP1
+ ADDRMAP2
+ ADDRMAP3
+ ADDRMAP4
+ ADDRMAP5
+ ADDRMAP6
+ ADDRMAP9
+ ADDRMAP10
+ ADDRMAP11
+
+- st,ctl-perf : controleur values depending of performance and scheduling
+ for STM32MP15x: 17 values are requested in this order
+ SCHED
+ SCHED1
+ PERFHPR1
+ PERFLPR1
+ PERFWR1
+ PCFGR_0
+ PCFGW_0
+ PCFGQOS0_0
+ PCFGQOS1_0
+ PCFGWQOS0_0
+ PCFGWQOS1_0
+ PCFGR_1
+ PCFGW_1
+ PCFGQOS0_1
+ PCFGQOS1_1
+ PCFGWQOS0_1
+ PCFGWQOS1_1
+
+phyc attributes:
+----------------
+- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
+ for STM32MP15x: 10 values are requested in this order
+ PGCR
+ ACIOCR
+ DXCCR
+ DSGCR
+ DCR
+ ODTCR
+ ZQ0CR1
+ DX0GCR
+ DX1GCR
+ DX2GCR
+ DX3GCR
+
+- st,phy-timing : phy values depending of frequency and timing parameter of DDR
+ for STM32MP15x: 10 values are requested in this order
+ PTR0
+ PTR1
+ PTR2
+ DTPR0
+ DTPR1
+ DTPR2
+ MR0
+ MR1
+ MR2
+ MR3
+
+- st,phy-cal : phy cal depending of calibration or tuning of DDR
+ for STM32MP15x: 12 values are requested in this order
+ DX0DLLCR
+ DX0DQTR
+ DX0DQSTR
+ DX1DLLCR
+ DX1DQTR
+ DX1DQSTR
+ DX2DLLCR
+ DX2DQTR
+ DX2DQSTR
+ DX3DLLCR
+ DX3DQTR
+ DX3DQSTR
+
+Example:
+
+/ {
+ soc {
+ u-boot,dm-spl;
+
+ ddr: ddr@0x5A003000{
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+
+ compatible = "st,stm32mp1-ddr";
+
+ reg = <0x5A003000 0x550
+ 0x5A004000 0x234>;
+
+ clocks = <&rcc_clk AXIDCG>,
+ <&rcc_clk DDRC1>,
+ <&rcc_clk DDRC2>,
+ <&rcc_clk DDRPHYC>,
+ <&rcc_clk DDRCAPB>,
+ <&rcc_clk DDRPHYCAPB>;
+
+ clock-names = "axidcg",
+ "ddrc1",
+ "ddrc2",
+ "ddrphyc",
+ "ddrcapb",
+ "ddrphycapb";
+
+ st,mem-name = "DDR3 2x4Gb 533MHz";
+ st,mem-speed = <533>;
+ st,mem-size = <0x40000000>;
+
+ st,ctl-reg = <
+ 0x00040401 /*MSTR*/
+ 0x00000010 /*MRCTRL0*/
+ 0x00000000 /*MRCTRL1*/
+ 0x00000000 /*DERATEEN*/
+ 0x00800000 /*DERATEINT*/
+ 0x00000000 /*PWRCTL*/
+ 0x00400010 /*PWRTMG*/
+ 0x00000000 /*HWLPCTL*/
+ 0x00210000 /*RFSHCTL0*/
+ 0x00000000 /*RFSHCTL3*/
+ 0x00000000 /*CRCPARCTL0*/
+ 0xC2000040 /*ZQCTL0*/
+ 0x02050105 /*DFITMG0*/
+ 0x00000202 /*DFITMG1*/
+ 0x07000000 /*DFILPCFG0*/
+ 0xC0400003 /*DFIUPD0*/
+ 0x00000000 /*DFIUPD1*/
+ 0x00000000 /*DFIUPD2*/
+ 0x00000000 /*DFIPHYMSTR*/
+ 0x00000001 /*ODTMAP*/
+ 0x00000000 /*DBG0*/
+ 0x00000000 /*DBG1*/
+ 0x00000000 /*DBGCMD*/
+ 0x00000000 /*POISONCFG*/
+ 0x00000010 /*PCCFG*/
+ >;
+
+ st,ctl-timing = <
+ 0x0080008A /*RFSHTMG*/
+ 0x121B2414 /*DRAMTMG0*/
+ 0x000D041B /*DRAMTMG1*/
+ 0x0607080E /*DRAMTMG2*/
+ 0x0050400C /*DRAMTMG3*/
+ 0x07040407 /*DRAMTMG4*/
+ 0x06060303 /*DRAMTMG5*/
+ 0x02020002 /*DRAMTMG6*/
+ 0x00000202 /*DRAMTMG7*/
+ 0x00001005 /*DRAMTMG8*/
+ 0x000D041B /*DRAMTMG1*/4
+ 0x06000600 /*ODTCFG*/
+ >;
+
+ st,ctl-map = <
+ 0x00080808 /*ADDRMAP1*/
+ 0x00000000 /*ADDRMAP2*/
+ 0x00000000 /*ADDRMAP3*/
+ 0x00001F1F /*ADDRMAP4*/
+ 0x07070707 /*ADDRMAP5*/
+ 0x0F070707 /*ADDRMAP6*/
+ 0x00000000 /*ADDRMAP9*/
+ 0x00000000 /*ADDRMAP10*/
+ 0x00000000 /*ADDRMAP11*/
+ >;
+
+ st,ctl-perf = <
+ 0x00001201 /*SCHED*/
+ 0x00001201 /*SCHED*/1
+ 0x01000001 /*PERFHPR1*/
+ 0x08000200 /*PERFLPR1*/
+ 0x08000400 /*PERFWR1*/
+ 0x00010000 /*PCFGR_0*/
+ 0x00000000 /*PCFGW_0*/
+ 0x02100B03 /*PCFGQOS0_0*/
+ 0x00800100 /*PCFGQOS1_0*/
+ 0x01100B03 /*PCFGWQOS0_0*/
+ 0x01000200 /*PCFGWQOS1_0*/
+ 0x00010000 /*PCFGR_1*/
+ 0x00000000 /*PCFGW_1*/
+ 0x02100B03 /*PCFGQOS0_1*/
+ 0x00800000 /*PCFGQOS1_1*/
+ 0x01100B03 /*PCFGWQOS0_1*/
+ 0x01000200 /*PCFGWQOS1_1*/
+ >;
+
+ st,phy-reg = <
+ 0x01442E02 /*PGCR*/
+ 0x10400812 /*ACIOCR*/
+ 0x00000C40 /*DXCCR*/
+ 0xF200001F /*DSGCR*/
+ 0x0000000B /*DCR*/
+ 0x00010000 /*ODTCR*/
+ 0x0000007B /*ZQ0CR1*/
+ 0x0000CE81 /*DX0GCR*/
+ 0x0000CE81 /*DX1GCR*/
+ 0x0000CE81 /*DX2GCR*/
+ 0x0000CE81 /*DX3GCR*/
+ >;
+
+ st,phy-timing = <
+ 0x0022A41B /*PTR0*/
+ 0x047C0740 /*PTR1*/
+ 0x042D9C80 /*PTR2*/
+ 0x369477D0 /*DTPR0*/
+ 0x098A00D8 /*DTPR1*/
+ 0x10023600 /*DTPR2*/
+ 0x00000830 /*MR0*/
+ 0x00000000 /*MR1*/
+ 0x00000208 /*MR2*/
+ 0x00000000 /*MR3*/
+ >;
+
+ st,phy-cal = <
+ 0x40000000 /*DX0DLLCR*/
+ 0xFFFFFFFF /*DX0DQTR*/
+ 0x3DB02000 /*DX0DQSTR*/
+ 0x40000000 /*DX1DLLCR*/
+ 0xFFFFFFFF /*DX1DQTR*/
+ 0x3DB02000 /*DX1DQSTR*/
+ 0x40000000 /*DX2DLLCR*/
+ 0xFFFFFFFF /*DX2DQTR*/
+ 0x3DB02000 /*DX2DQSTR*/
+ 0x40000000 /*DX3DLLCR*/
+ 0xFFFFFFFF /*DX3DQTR*/
+ 0x3DB02000 /*DX3DQSTR*/
+ >;
+
+ status = "okay";
+ };
+ };
+};
+++ /dev/null
-Texas Instruments' K3 AM654 DDRSS
-=================================
-
-K3 based AM654 devices has DDR memory subsystem that comprises
-Synopys DDR controller, Synopsis DDR phy and wrapper logic to
-integrate these blocks into the device. This DDR subsystem
-provides an interface to external SDRAM devices. This DDRSS driver
-adds support for the initialization of the external SDRAM devices by
-configuring the DDRSS registers and using the buitin PHY
-initialization routines.
-
-DDRSS device node:
-==================
-Required properties:
---------------------
-- compatible: Shall be: "ti,am654-ddrss"
-- reg-names ss - Map the sub system wrapper logic region
- ctl - Map the controller region
- phy - Map the PHY region
-- reg: Contains the register map per reg-names.
-- power-domains: Should contain a phandle to a PM domain provider node
- and an args specifier containing the DDRSS device id
- value. This property is as per the binding,
- doc/device-tree-bindings/power/ti,sci-pm-domain.txt
-- clocks: Must contain an entry for enabling DDR clock. Should
- be defined as per the appropriate clock bindings consumer
- usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
-
-
-Optional Properties:
---------------------
-- clock-frequency: Frequency at which DDR pll should be locked.
- If not provided, default frequency will be used.
-
-Example (AM65x):
-================
- memory-controller: memory-controller@298e000 {
- compatible = "ti,am654-ddrss";
- reg = <0x0298e000 0x200>,
- <0x02980000 0x4000>,
- <0x02988000 0x2000>;
- reg-names = "ss", "ctl", "phy";
- clocks = <&k3_clks 20 0>;
- power-domains = <&k3_pds 20>;
- u-boot,dm-spl;
- };
+++ /dev/null
-ST, stm32 flexible memory controller Drive
-Required properties:
-- compatible : "st,stm32-fmc"
-- reg : fmc controller base address
-- clocks : fmc controller clock
-u-boot,dm-pre-reloc: flag to initialize memory before relocation.
-
-on-board sdram memory attributes:
-- st,sdram-control : parameters for sdram configuration, in this order:
- number of columns
- number of rows
- memory width
- number of intenal banks in memory
- cas latency
- read burst enable or disable
- read pipe delay
-
-- st,sdram-timing: timings for sdram, in this order:
- tmrd
- txsr
- tras
- trc
- trp
- trcd
-
-There is device tree include file at :
-include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
-parameters as MACROS.
-
-Example:
- fmc: fmc@A0000000 {
- compatible = "st,stm32-fmc";
- reg = <0xA0000000 0x1000>;
- clocks = <&rcc 0 64>;
- u-boot,dm-pre-reloc;
- };
-
- &fmc {
- pinctrl-0 = <&fmc_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /* sdram memory configuration from sdram datasheet */
- bank1: bank@0 {
- st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
- CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
- TRCD_18>;
- };
-
- /* sdram memory configuration from sdram datasheet */
- bank2: bank@1 {
- st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
- CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
- TRCD_18>;
- };
- }
+++ /dev/null
-ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
-
---------------------
-Required properties:
---------------------
-- compatible : Should be "st,stm32mp1-ddr"
-- reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
-- clocks : controller clocks handle
-- clock-names : associated controller clock names
- the "ddrphyc" clock is used to check the DDR frequency
- at phy level according the expected value in "mem-speed" field
-
-the next attributes are DDR parameters, they are generated by DDR tools
-included in STM32 Cube tool
-
-info attributes:
-----------------
-- st,mem-name : name for DDR configuration, simple string for information
-- st,mem-speed : DDR expected speed for the setting in MHz
-- st,mem-size : DDR mem size in byte
-
-
-controlleur attributes:
------------------------
-- st,ctl-reg : controleur values depending of the DDR type
- (DDR3/LPDDR2/LPDDR3)
- for STM32MP15x: 25 values are requested in this order
- MSTR
- MRCTRL0
- MRCTRL1
- DERATEEN
- DERATEINT
- PWRCTL
- PWRTMG
- HWLPCTL
- RFSHCTL0
- RFSHCTL3
- CRCPARCTL0
- ZQCTL0
- DFITMG0
- DFITMG1
- DFILPCFG0
- DFIUPD0
- DFIUPD1
- DFIUPD2
- DFIPHYMSTR
- ODTMAP
- DBG0
- DBG1
- DBGCMD
- POISONCFG
- PCCFG
-
-- st,ctl-timing : controleur values depending of frequency and timing parameter
- of DDR
- for STM32MP15x: 12 values are requested in this order
- RFSHTMG
- DRAMTMG0
- DRAMTMG1
- DRAMTMG2
- DRAMTMG3
- DRAMTMG4
- DRAMTMG5
- DRAMTMG6
- DRAMTMG7
- DRAMTMG8
- DRAMTMG14
- ODTCFG
-
-- st,ctl-map : controleur values depending of address mapping
- for STM32MP15x: 9 values are requested in this order
- ADDRMAP1
- ADDRMAP2
- ADDRMAP3
- ADDRMAP4
- ADDRMAP5
- ADDRMAP6
- ADDRMAP9
- ADDRMAP10
- ADDRMAP11
-
-- st,ctl-perf : controleur values depending of performance and scheduling
- for STM32MP15x: 17 values are requested in this order
- SCHED
- SCHED1
- PERFHPR1
- PERFLPR1
- PERFWR1
- PCFGR_0
- PCFGW_0
- PCFGQOS0_0
- PCFGQOS1_0
- PCFGWQOS0_0
- PCFGWQOS1_0
- PCFGR_1
- PCFGW_1
- PCFGQOS0_1
- PCFGQOS1_1
- PCFGWQOS0_1
- PCFGWQOS1_1
-
-phyc attributes:
-----------------
-- st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
- for STM32MP15x: 10 values are requested in this order
- PGCR
- ACIOCR
- DXCCR
- DSGCR
- DCR
- ODTCR
- ZQ0CR1
- DX0GCR
- DX1GCR
- DX2GCR
- DX3GCR
-
-- st,phy-timing : phy values depending of frequency and timing parameter of DDR
- for STM32MP15x: 10 values are requested in this order
- PTR0
- PTR1
- PTR2
- DTPR0
- DTPR1
- DTPR2
- MR0
- MR1
- MR2
- MR3
-
-- st,phy-cal : phy cal depending of calibration or tuning of DDR
- for STM32MP15x: 12 values are requested in this order
- DX0DLLCR
- DX0DQTR
- DX0DQSTR
- DX1DLLCR
- DX1DQTR
- DX1DQSTR
- DX2DLLCR
- DX2DQTR
- DX2DQSTR
- DX3DLLCR
- DX3DQTR
- DX3DQSTR
-
-Example:
-
-/ {
- soc {
- u-boot,dm-spl;
-
- ddr: ddr@0x5A003000{
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-
- compatible = "st,stm32mp1-ddr";
-
- reg = <0x5A003000 0x550
- 0x5A004000 0x234>;
-
- clocks = <&rcc_clk AXIDCG>,
- <&rcc_clk DDRC1>,
- <&rcc_clk DDRC2>,
- <&rcc_clk DDRPHYC>,
- <&rcc_clk DDRCAPB>,
- <&rcc_clk DDRPHYCAPB>;
-
- clock-names = "axidcg",
- "ddrc1",
- "ddrc2",
- "ddrphyc",
- "ddrcapb",
- "ddrphycapb";
-
- st,mem-name = "DDR3 2x4Gb 533MHz";
- st,mem-speed = <533>;
- st,mem-size = <0x40000000>;
-
- st,ctl-reg = <
- 0x00040401 /*MSTR*/
- 0x00000010 /*MRCTRL0*/
- 0x00000000 /*MRCTRL1*/
- 0x00000000 /*DERATEEN*/
- 0x00800000 /*DERATEINT*/
- 0x00000000 /*PWRCTL*/
- 0x00400010 /*PWRTMG*/
- 0x00000000 /*HWLPCTL*/
- 0x00210000 /*RFSHCTL0*/
- 0x00000000 /*RFSHCTL3*/
- 0x00000000 /*CRCPARCTL0*/
- 0xC2000040 /*ZQCTL0*/
- 0x02050105 /*DFITMG0*/
- 0x00000202 /*DFITMG1*/
- 0x07000000 /*DFILPCFG0*/
- 0xC0400003 /*DFIUPD0*/
- 0x00000000 /*DFIUPD1*/
- 0x00000000 /*DFIUPD2*/
- 0x00000000 /*DFIPHYMSTR*/
- 0x00000001 /*ODTMAP*/
- 0x00000000 /*DBG0*/
- 0x00000000 /*DBG1*/
- 0x00000000 /*DBGCMD*/
- 0x00000000 /*POISONCFG*/
- 0x00000010 /*PCCFG*/
- >;
-
- st,ctl-timing = <
- 0x0080008A /*RFSHTMG*/
- 0x121B2414 /*DRAMTMG0*/
- 0x000D041B /*DRAMTMG1*/
- 0x0607080E /*DRAMTMG2*/
- 0x0050400C /*DRAMTMG3*/
- 0x07040407 /*DRAMTMG4*/
- 0x06060303 /*DRAMTMG5*/
- 0x02020002 /*DRAMTMG6*/
- 0x00000202 /*DRAMTMG7*/
- 0x00001005 /*DRAMTMG8*/
- 0x000D041B /*DRAMTMG1*/4
- 0x06000600 /*ODTCFG*/
- >;
-
- st,ctl-map = <
- 0x00080808 /*ADDRMAP1*/
- 0x00000000 /*ADDRMAP2*/
- 0x00000000 /*ADDRMAP3*/
- 0x00001F1F /*ADDRMAP4*/
- 0x07070707 /*ADDRMAP5*/
- 0x0F070707 /*ADDRMAP6*/
- 0x00000000 /*ADDRMAP9*/
- 0x00000000 /*ADDRMAP10*/
- 0x00000000 /*ADDRMAP11*/
- >;
-
- st,ctl-perf = <
- 0x00001201 /*SCHED*/
- 0x00001201 /*SCHED*/1
- 0x01000001 /*PERFHPR1*/
- 0x08000200 /*PERFLPR1*/
- 0x08000400 /*PERFWR1*/
- 0x00010000 /*PCFGR_0*/
- 0x00000000 /*PCFGW_0*/
- 0x02100B03 /*PCFGQOS0_0*/
- 0x00800100 /*PCFGQOS1_0*/
- 0x01100B03 /*PCFGWQOS0_0*/
- 0x01000200 /*PCFGWQOS1_0*/
- 0x00010000 /*PCFGR_1*/
- 0x00000000 /*PCFGW_1*/
- 0x02100B03 /*PCFGQOS0_1*/
- 0x00800000 /*PCFGQOS1_1*/
- 0x01100B03 /*PCFGWQOS0_1*/
- 0x01000200 /*PCFGWQOS1_1*/
- >;
-
- st,phy-reg = <
- 0x01442E02 /*PGCR*/
- 0x10400812 /*ACIOCR*/
- 0x00000C40 /*DXCCR*/
- 0xF200001F /*DSGCR*/
- 0x0000000B /*DCR*/
- 0x00010000 /*ODTCR*/
- 0x0000007B /*ZQ0CR1*/
- 0x0000CE81 /*DX0GCR*/
- 0x0000CE81 /*DX1GCR*/
- 0x0000CE81 /*DX2GCR*/
- 0x0000CE81 /*DX3GCR*/
- >;
-
- st,phy-timing = <
- 0x0022A41B /*PTR0*/
- 0x047C0740 /*PTR1*/
- 0x042D9C80 /*PTR2*/
- 0x369477D0 /*DTPR0*/
- 0x098A00D8 /*DTPR1*/
- 0x10023600 /*DTPR2*/
- 0x00000830 /*MR0*/
- 0x00000000 /*MR1*/
- 0x00000208 /*MR2*/
- 0x00000000 /*MR3*/
- >;
-
- st,phy-cal = <
- 0x40000000 /*DX0DLLCR*/
- 0xFFFFFFFF /*DX0DQTR*/
- 0x3DB02000 /*DX0DQSTR*/
- 0x40000000 /*DX1DLLCR*/
- 0xFFFFFFFF /*DX1DQTR*/
- 0x3DB02000 /*DX1DQSTR*/
- 0x40000000 /*DX2DLLCR*/
- 0xFFFFFFFF /*DX2DQTR*/
- 0x3DB02000 /*DX2DQSTR*/
- 0x40000000 /*DX3DLLCR*/
- 0xFFFFFFFF /*DX3DQTR*/
- 0x3DB02000 /*DX3DQSTR*/
- >;
-
- status = "okay";
- };
- };
-};
--- /dev/null
+* Intel High-definition Audio
+
+Configuration is set using 'verbs' which are blocks of 16 bytes of data each
+with a different purpose, a little like a simple instruction set.
+
+Top-level node
+--------------
+
+Required properties:
+- compatible: "intel,hd-audio"
+- beep-verbs: list of verbs to send for a beep
+
+Optional properties
+- intel,beep-nid: Node ID to use for beep (will be detected if not provided)
+
+Required subnodes:
+- codecs: Contains a list of codec nodes
+
+
+* Codec nodes
+
+Required properties:
+- vendor-id: 16-bit vendor ID for audio codec
+- device-id: 16-bit device ID for audio codec
+- verbs: List of verbs, each 4 cells in length
source "drivers/pci/Kconfig"
+source "drivers/pch/Kconfig"
+
source "drivers/pcmcia/Kconfig"
source "drivers/phy/Kconfig"
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_NVME) += nvme/
obj-y += pcmcia/
-obj-$(CONFIG_X86) += pch/
+obj-y += dfu/
+obj-$(CONFIG_PCH) += pch/
obj-y += phy/allwinner/
obj-y += phy/marvell/
obj-y += rtc/
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/sunxi/Kconfig"
+source "drivers/clk/sifive/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
+obj-$(CONFIG_CLK_SIFIVE) += sifive/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Author: Anup Patel <anup.patel@wdc.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+
+struct clk_fixed_factor {
+ struct clk parent;
+ unsigned int div;
+ unsigned int mult;
+};
+
+#define to_clk_fixed_factor(dev) \
+ ((struct clk_fixed_factor *)dev_get_platdata(dev))
+
+static ulong clk_fixed_factor_get_rate(struct clk *clk)
+{
+ uint64_t rate;
+ struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
+
+ if (clk->id != 0)
+ return -EINVAL;
+
+ rate = clk_get_rate(&ff->parent);
+ if (IS_ERR_VALUE(rate))
+ return rate;
+
+ do_div(rate, ff->div);
+
+ return rate * ff->mult;
+}
+
+const struct clk_ops clk_fixed_factor_ops = {
+ .get_rate = clk_fixed_factor_get_rate,
+};
+
+static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ int err;
+ struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+
+ err = clk_get_by_index(dev, 0, &ff->parent);
+ if (err)
+ return err;
+
+ ff->div = dev_read_u32_default(dev, "clock-div", 1);
+ ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id clk_fixed_factor_match[] = {
+ {
+ .compatible = "fixed-factor-clock",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_fixed_factor) = {
+ .name = "fixed_factor_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_fixed_factor_match,
+ .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+ .ops = &clk_fixed_factor_ops,
+};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+ bool
+
+config CLK_SIFIVE
+ bool "SiFive SoC driver support"
+ depends on CLK
+ help
+ SoC drivers for SiFive Linux-capable SoCs.
+
+config CLK_SIFIVE_FU540_PRCI
+ bool "PRCI driver for SiFive FU540 SoCs"
+ depends on CLK_SIFIVE
+ select CLK_ANALOGBITS_WRPLL_CLN28HPC
+ help
+ Supports the Power Reset Clock interface (PRCI) IP block found in
+ FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
+ enable this driver.
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC) += wrpll-cln28hpc.o
+
+obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Copyright (C) 2018 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+
+#include <linux/types.h>
+
+/* DIVQ_VALUES: number of valid DIVQ values */
+#define DIVQ_VALUES 6
+
+/*
+ * Bit definitions for struct analogbits_wrpll_cfg.flags
+ *
+ * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
+ * programmed to enter bypass
+ * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
+ * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
+ * feedback mode
+ * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
+ * feedback mode (not yet supported by this driver)
+ *
+ * The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WRPLL_FLAGS_EXT_FEEDBACK_FLAG are
+ * mutually exclusive. If both bits are set, or both are zero, the struct
+ * analogbits_wrpll_cfg record is uninitialized or corrupt.
+ */
+#define WRPLL_FLAGS_BYPASS_SHIFT 0
+#define WRPLL_FLAGS_BYPASS_MASK BIT(WRPLL_FLAGS_BYPASS_SHIFT)
+#define WRPLL_FLAGS_RESET_SHIFT 1
+#define WRPLL_FLAGS_RESET_MASK BIT(WRPLL_FLAGS_RESET_SHIFT)
+#define WRPLL_FLAGS_INT_FEEDBACK_SHIFT 2
+#define WRPLL_FLAGS_INT_FEEDBACK_MASK BIT(WRPLL_FLAGS_INT_FEEDBACK_SHIFT)
+#define WRPLL_FLAGS_EXT_FEEDBACK_SHIFT 3
+#define WRPLL_FLAGS_EXT_FEEDBACK_MASK BIT(WRPLL_FLAGS_EXT_FEEDBACK_SHIFT)
+
+/**
+ * struct analogbits_wrpll_cfg - WRPLL configuration values
+ * @divr: reference divider value (6 bits), as presented to the PLL signals.
+ * @divf: feedback divider value (9 bits), as presented to the PLL signals.
+ * @divq: output divider value (3 bits), as presented to the PLL signals.
+ * @flags: PLL configuration flags. See above for more information.
+ * @range: PLL loop filter range. See below for more information.
+ * @_output_rate_cache: cached output rates, swept across DIVQ.
+ * @_parent_rate: PLL refclk rate for which values are valid
+ * @_max_r: maximum possible R divider value, given @parent_rate
+ * @_init_r: initial R divider value to start the search from
+ *
+ * @divr, @divq, @divq, @range represent what the PLL expects to see
+ * on its input signals. Thus @divr and @divf are the actual divisors
+ * minus one. @divq is a power-of-two divider; for example, 1 =
+ * divide-by-2 and 6 = divide-by-64. 0 is an invalid @divq value.
+ *
+ * When initially passing a struct analogbits_wrpll_cfg record, the
+ * record should be zero-initialized with the exception of the @flags
+ * field. The only flag bits that need to be set are either
+ * WRPLL_FLAGS_INT_FEEDBACK or WRPLL_FLAGS_EXT_FEEDBACK.
+ *
+ * Field names beginning with an underscore should be considered
+ * private to the wrpll-cln28hpc.c code.
+ */
+struct analogbits_wrpll_cfg {
+ u8 divr;
+ u8 divq;
+ u8 range;
+ u8 flags;
+ u16 divf;
+ u32 _output_rate_cache[DIVQ_VALUES];
+ unsigned long _parent_rate;
+ u8 _max_r;
+ u8 _init_r;
+};
+
+/*
+ * Function prototypes
+ */
+
+int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
+ u32 target_rate,
+ unsigned long parent_rate);
+
+unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c);
+
+unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
+ unsigned long parent_rate);
+
+#endif /* __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Copyright (C) 2018 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * The FU540 PRCI implements clock and reset control for the SiFive
+ * FU540-C000 chip. This driver assumes that it has sole control
+ * over all PRCI resources.
+ *
+ * This driver is based on the PRCI driver written by Wesley Terpstra.
+ *
+ * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
+ * https://github.com/riscv/riscv-linux
+ *
+ * References:
+ * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
+ */
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <clk.h>
+#include <common.h>
+#include <div64.h>
+#include <dm.h>
+#include <errno.h>
+
+#include <linux/math64.h>
+#include <dt-bindings/clk/sifive-fu540-prci.h>
+
+#include "analogbits-wrpll-cln28hpc.h"
+
+/*
+ * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
+ * hfclk and rtcclk
+ */
+#define EXPECTED_CLK_PARENT_COUNT 2
+
+/*
+ * Register offsets and bitmasks
+ */
+
+/* COREPLLCFG0 */
+#define PRCI_COREPLLCFG0_OFFSET 0x4
+#define PRCI_COREPLLCFG0_DIVR_SHIFT 0
+#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
+#define PRCI_COREPLLCFG0_DIVF_SHIFT 6
+#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
+#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
+#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
+#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
+#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
+#define PRCI_COREPLLCFG0_FSE_SHIFT 25
+#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
+#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
+#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+
+/* DDRPLLCFG0 */
+#define PRCI_DDRPLLCFG0_OFFSET 0xc
+#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
+#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
+#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
+#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
+#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
+#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
+#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
+#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
+#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
+#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
+#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
+#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
+
+/* DDRPLLCFG1 */
+#define PRCI_DDRPLLCFG1_OFFSET 0x10
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
+#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
+
+/* GEMGXLPLLCFG0 */
+#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
+#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
+#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
+ (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
+#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
+ (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
+#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
+ (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
+ (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
+#define PRCI_GEMGXLPLLCFG0_FSE_MASK \
+ (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
+#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
+
+/* GEMGXLPLLCFG1 */
+#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 24
+#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
+
+/* CORECLKSEL */
+#define PRCI_CORECLKSEL_OFFSET 0x24
+#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
+#define PRCI_CORECLKSEL_CORECLKSEL_MASK \
+ (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
+
+/* DEVICESRESETREG */
+#define PRCI_DEVICESRESETREG_OFFSET 0x28
+#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0
+#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
+ (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT)
+#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1
+#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
+ (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT)
+#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2
+#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
+ (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT)
+#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3
+#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
+ (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT)
+#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5
+#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
+ (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT)
+
+/* CLKMUXSTATUSREG */
+#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
+#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
+#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
+ (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+
+/*
+ * Private structures
+ */
+
+/**
+ * struct __prci_data - per-device-instance data
+ * @va: base virtual address of the PRCI IP block
+ * @parent: parent clk instance
+ *
+ * PRCI per-device instance data
+ */
+struct __prci_data {
+ void *base;
+ struct clk parent;
+};
+
+/**
+ * struct __prci_wrpll_data - WRPLL configuration and integration data
+ * @c: WRPLL current configuration record
+ * @bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
+ * @no_bypass: fn ptr to code to not bypass the WRPLL (if applicable; else NULL)
+ * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ *
+ * @bypass and @no_bypass are used for WRPLL instances that contain a separate
+ * external glitchless clock mux downstream from the PLL. The WRPLL internal
+ * bypass mux is not glitchless.
+ */
+struct __prci_wrpll_data {
+ struct analogbits_wrpll_cfg c;
+ void (*bypass)(struct __prci_data *pd);
+ void (*no_bypass)(struct __prci_data *pd);
+ u8 cfg0_offs;
+};
+
+struct __prci_clock;
+
+struct __prci_clock_ops {
+ int (*set_rate)(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long parent_rate);
+ unsigned long (*round_rate)(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long *parent_rate);
+ unsigned long (*recalc_rate)(struct __prci_clock *pc,
+ unsigned long parent_rate);
+};
+
+/**
+ * struct __prci_clock - describes a clock device managed by PRCI
+ * @name: user-readable clock name string - should match the manual
+ * @parent_name: parent name for this clock
+ * @ops: struct clk_ops for the Linux clock framework to use for control
+ * @hw: Linux-private clock data
+ * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
+ * @pd: PRCI-specific data associated with this clock (if not NULL)
+ *
+ * PRCI clock data. Used by the PRCI driver to register PRCI-provided
+ * clocks to the Linux clock infrastructure.
+ */
+struct __prci_clock {
+ const char *name;
+ const char *parent_name;
+ const struct __prci_clock_ops *ops;
+ struct __prci_wrpll_data *pwd;
+ struct __prci_data *pd;
+};
+
+/*
+ * Private functions
+ */
+
+/**
+ * __prci_readl() - read from a PRCI register
+ * @pd: PRCI context
+ * @offs: register offset to read from (in bytes, from PRCI base address)
+ *
+ * Read the register located at offset @offs from the base virtual
+ * address of the PRCI register target described by @pd, and return
+ * the value to the caller.
+ *
+ * Context: Any context.
+ *
+ * Return: the contents of the register described by @pd and @offs.
+ */
+static u32 __prci_readl(struct __prci_data *pd, u32 offs)
+{
+ return readl(pd->base + offs);
+}
+
+static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
+{
+ return writel(v, pd->base + offs);
+}
+
+/* WRPLL-related private functions */
+
+/**
+ * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
+ * @c: ptr to a struct analogbits_wrpll_cfg record to write config into
+ * @r: value read from the PRCI PLL configuration register
+ *
+ * Given a value @r read from an FU540 PRCI PLL configuration register,
+ * split it into fields and populate it into the WRPLL configuration record
+ * pointed to by @c.
+ *
+ * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
+ * have the same register layout.
+ *
+ * Context: Any context.
+ */
+static void __prci_wrpll_unpack(struct analogbits_wrpll_cfg *c, u32 r)
+{
+ u32 v;
+
+ v = r & PRCI_COREPLLCFG0_DIVR_MASK;
+ v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
+ c->divr = v;
+
+ v = r & PRCI_COREPLLCFG0_DIVF_MASK;
+ v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
+ c->divf = v;
+
+ v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
+ v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
+ c->divq = v;
+
+ v = r & PRCI_COREPLLCFG0_RANGE_MASK;
+ v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
+ c->range = v;
+
+ c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
+ WRPLL_FLAGS_EXT_FEEDBACK_MASK);
+
+ if (r & PRCI_COREPLLCFG0_FSE_MASK)
+ c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
+ else
+ c->flags |= WRPLL_FLAGS_EXT_FEEDBACK_MASK;
+}
+
+/**
+ * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
+ * @c: pointer to a struct analogbits_wrpll_cfg record containing the PLL's cfg
+ *
+ * Using a set of WRPLL configuration values pointed to by @c,
+ * assemble a PRCI PLL configuration register value, and return it to
+ * the caller.
+ *
+ * Context: Any context. Caller must ensure that the contents of the
+ * record pointed to by @c do not change during the execution
+ * of this function.
+ *
+ * Returns: a value suitable for writing into a PRCI PLL configuration
+ * register
+ */
+static u32 __prci_wrpll_pack(struct analogbits_wrpll_cfg *c)
+{
+ u32 r = 0;
+
+ r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
+ r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
+ r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
+ r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
+ if (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK)
+ r |= PRCI_COREPLLCFG0_FSE_MASK;
+
+ return r;
+}
+
+/**
+ * __prci_wrpll_read_cfg() - read the WRPLL configuration from the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ *
+ * Read the current configuration of the PLL identified by @pwd from
+ * the PRCI identified by @pd, and store it into the local configuration
+ * cache in @pwd.
+ *
+ * Context: Any context. Caller must prevent the records pointed to by
+ * @pd and @pwd from changing during execution.
+ */
+static void __prci_wrpll_read_cfg(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd)
+{
+ __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
+}
+
+/**
+ * __prci_wrpll_write_cfg() - write WRPLL configuration into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @c: WRPLL configuration record to write
+ *
+ * Write the WRPLL configuration described by @c into the WRPLL
+ * configuration register identified by @pwd in the PRCI instance
+ * described by @c. Make a cached copy of the WRPLL's current
+ * configuration so it can be used by other code.
+ *
+ * Context: Any context. Caller must prevent the records pointed to by
+ * @pd and @pwd from changing during execution.
+ */
+static void __prci_wrpll_write_cfg(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ struct analogbits_wrpll_cfg *c)
+{
+ __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
+
+ memcpy(&pwd->c, c, sizeof(struct analogbits_wrpll_cfg));
+}
+
+/* Core clock mux control */
+
+/**
+ * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
+ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
+ *
+ * Switch the CORECLK mux to the HFCLK input source; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_CORECLKSEL_OFFSET register.
+ */
+static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
+ r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
+ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
+}
+
+/**
+ * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
+ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
+ *
+ * Switch the CORECLK mux to the PLL output clock; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_CORECLKSEL_OFFSET register.
+ */
+static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
+ r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
+ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
+}
+
+static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
+ struct __prci_clock *pc,
+ unsigned long parent_rate)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+
+ return analogbits_wrpll_calc_output_rate(&pwd->c, parent_rate);
+}
+
+static unsigned long sifive_fu540_prci_wrpll_round_rate(
+ struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct analogbits_wrpll_cfg c;
+
+ memcpy(&c, &pwd->c, sizeof(c));
+
+ analogbits_wrpll_configure_for_rate(&c, rate, *parent_rate);
+
+ return analogbits_wrpll_calc_output_rate(&c, *parent_rate);
+}
+
+static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+ int r;
+
+ r = analogbits_wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
+ if (r)
+ return -ERANGE;
+
+ if (pwd->bypass)
+ pwd->bypass(pd);
+
+ __prci_wrpll_write_cfg(pd, pwd, &pwd->c);
+
+ udelay(analogbits_wrpll_calc_max_lock_us(&pwd->c));
+
+ if (pwd->no_bypass)
+ pwd->no_bypass(pd);
+
+ return 0;
+}
+
+static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
+ .set_rate = sifive_fu540_prci_wrpll_set_rate,
+ .round_rate = sifive_fu540_prci_wrpll_round_rate,
+ .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+};
+
+static const struct __prci_clock_ops sifive_fu540_prci_wrpll_ro_clk_ops = {
+ .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
+};
+
+/* TLCLKSEL clock integration */
+
+static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
+ struct __prci_clock *pc,
+ unsigned long parent_rate)
+{
+ struct __prci_data *pd = pc->pd;
+ u32 v;
+ u8 div;
+
+ v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
+ v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
+ div = v ? 1 : 2;
+
+ return div_u64(parent_rate, div);
+}
+
+static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
+ .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
+};
+
+/*
+ * PRCI integration data for each WRPLL instance
+ */
+
+static struct __prci_wrpll_data __prci_corepll_data = {
+ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .bypass = __prci_coreclksel_use_hfclk,
+ .no_bypass = __prci_coreclksel_use_corepll,
+};
+
+static struct __prci_wrpll_data __prci_ddrpll_data = {
+ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+};
+
+static struct __prci_wrpll_data __prci_gemgxlpll_data = {
+ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+};
+
+/*
+ * List of clock controls provided by the PRCI
+ */
+
+static struct __prci_clock __prci_init_clocks[] = {
+ [PRCI_CLK_COREPLL] = {
+ .name = "corepll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu540_prci_wrpll_clk_ops,
+ .pwd = &__prci_corepll_data,
+ },
+ [PRCI_CLK_DDRPLL] = {
+ .name = "ddrpll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu540_prci_wrpll_ro_clk_ops,
+ .pwd = &__prci_ddrpll_data,
+ },
+ [PRCI_CLK_GEMGXLPLL] = {
+ .name = "gemgxlpll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu540_prci_wrpll_clk_ops,
+ .pwd = &__prci_gemgxlpll_data,
+ },
+ [PRCI_CLK_TLCLK] = {
+ .name = "tlclk",
+ .parent_name = "corepll",
+ .ops = &sifive_fu540_prci_tlclksel_clk_ops,
+ },
+};
+
+static ulong sifive_fu540_prci_get_rate(struct clk *clk)
+{
+ struct __prci_clock *pc;
+
+ if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
+ return -ENXIO;
+
+ pc = &__prci_init_clocks[clk->id];
+ if (!pc->pd || !pc->ops->recalc_rate)
+ return -ENXIO;
+
+ return pc->ops->recalc_rate(pc, clk_get_rate(&pc->pd->parent));
+}
+
+static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
+{
+ int err;
+ struct __prci_clock *pc;
+
+ if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
+ return -ENXIO;
+
+ pc = &__prci_init_clocks[clk->id];
+ if (!pc->pd || !pc->ops->set_rate)
+ return -ENXIO;
+
+ err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent));
+ if (err)
+ return err;
+
+ return rate;
+}
+
+static int sifive_fu540_prci_probe(struct udevice *dev)
+{
+ int i, err;
+ struct __prci_clock *pc;
+ struct __prci_data *pd = dev_get_priv(dev);
+
+ pd->base = (void *)dev_read_addr(dev);
+ if (IS_ERR(pd->base))
+ return PTR_ERR(pd->base);
+
+ err = clk_get_by_index(dev, 0, &pd->parent);
+ if (err)
+ return err;
+
+ for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
+ pc = &__prci_init_clocks[i];
+ pc->pd = pd;
+ if (pc->pwd)
+ __prci_wrpll_read_cfg(pd, pc->pwd);
+ }
+
+ return 0;
+}
+
+static struct clk_ops sifive_fu540_prci_ops = {
+ .set_rate = sifive_fu540_prci_set_rate,
+ .get_rate = sifive_fu540_prci_get_rate,
+};
+
+static const struct udevice_id sifive_fu540_prci_ids[] = {
+ { .compatible = "sifive,fu540-c000-prci0" },
+ { .compatible = "sifive,aloeprci0" },
+ { }
+};
+
+U_BOOT_DRIVER(sifive_fu540_prci) = {
+ .name = "sifive-fu540-prci",
+ .id = UCLASS_CLK,
+ .of_match = sifive_fu540_prci_ids,
+ .probe = sifive_fu540_prci_probe,
+ .ops = &sifive_fu540_prci_ops,
+ .priv_auto_alloc_size = sizeof(struct __prci_data),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Copyright (C) 2018 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This library supports configuration parsing and reprogramming of
+ * the CLN28HPC variant of the Analog Bits Wide Range PLL. The
+ * intention is for this library to be reusable for any device that
+ * integrates this PLL; thus the register structure and programming
+ * details are expected to be provided by a separate IP block driver.
+ *
+ * The bulk of this code is primarily useful for clock configurations
+ * that must operate at arbitrary rates, as opposed to clock configurations
+ * that are restricted by software or manufacturer guidance to a small,
+ * pre-determined set of performance points.
+ *
+ * References:
+ * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
+ * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
+ */
+
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/log2.h>
+#include <linux/math64.h>
+
+#include "analogbits-wrpll-cln28hpc.h"
+
+/* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
+#define MIN_INPUT_FREQ 7000000
+
+/* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
+#define MAX_INPUT_FREQ 600000000
+
+/* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
+#define MIN_POST_DIVR_FREQ 7000000
+
+/* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
+#define MAX_POST_DIVR_FREQ 200000000
+
+/* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */
+#define MIN_VCO_FREQ 2400000000UL
+
+/* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */
+#define MAX_VCO_FREQ 4800000000ULL
+
+/* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */
+#define MAX_DIVQ_DIVISOR 64
+
+/* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */
+#define MAX_DIVR_DIVISOR 64
+
+/* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */
+#define MAX_LOCK_US 70
+
+/*
+ * ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding
+ * algorithm
+ */
+#define ROUND_SHIFT 20
+
+/*
+ * Private functions
+ */
+
+/**
+ * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
+ * @post_divr_freq: input clock rate after the R divider
+ *
+ * Select the value to be presented to the PLL RANGE input signals, based
+ * on the input clock frequency after the post-R-divider @post_divr_freq.
+ * This code follows the recommendations in the PLL datasheet for filter
+ * range selection.
+ *
+ * Return: The RANGE value to be presented to the PLL configuration inputs,
+ * or -1 upon error.
+ */
+static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
+{
+ u8 range;
+
+ if (post_divr_freq < MIN_POST_DIVR_FREQ ||
+ post_divr_freq > MAX_POST_DIVR_FREQ) {
+ WARN(1, "%s: post-divider reference freq out of range: %lu",
+ __func__, post_divr_freq);
+ return -1;
+ }
+
+ if (post_divr_freq < 11000000)
+ range = 1;
+ else if (post_divr_freq < 18000000)
+ range = 2;
+ else if (post_divr_freq < 30000000)
+ range = 3;
+ else if (post_divr_freq < 50000000)
+ range = 4;
+ else if (post_divr_freq < 80000000)
+ range = 5;
+ else if (post_divr_freq < 130000000)
+ range = 6;
+ else
+ range = 7;
+
+ return range;
+}
+
+/**
+ * __wrpll_calc_fbdiv() - return feedback fixed divide value
+ * @c: ptr to a struct analogbits_wrpll_cfg record to read from
+ *
+ * The internal feedback path includes a fixed by-two divider; the
+ * external feedback path does not. Return the appropriate divider
+ * value (2 or 1) depending on whether internal or external feedback
+ * is enabled. This code doesn't test for invalid configurations
+ * (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies
+ * on the caller to do so.
+ *
+ * Context: Any context. Caller must protect the memory pointed to by
+ * @c from simultaneous modification.
+ *
+ * Return: 2 if internal feedback is enabled or 1 if external feedback
+ * is enabled.
+ */
+static u8 __wrpll_calc_fbdiv(struct analogbits_wrpll_cfg *c)
+{
+ return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1;
+}
+
+/**
+ * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
+ * @target_rate: target PLL output clock rate
+ * @vco_rate: pointer to a u64 to store the computed VCO rate into
+ *
+ * Determine a reasonable value for the PLL Q post-divider, based on the
+ * target output rate @target_rate for the PLL. Along with returning the
+ * computed Q divider value as the return value, this function stores the
+ * desired target VCO rate into the variable pointed to by @vco_rate.
+ *
+ * Context: Any context. Caller must protect the memory pointed to by
+ * @vco_rate from simultaneous access or modification.
+ *
+ * Return: a positive integer DIVQ value to be programmed into the hardware
+ * upon success, or 0 upon error (since 0 is an invalid DIVQ value)
+ */
+static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
+{
+ u64 s;
+ u8 divq = 0;
+
+ if (!vco_rate) {
+ WARN_ON(1);
+ goto wcd_out;
+ }
+
+ s = div_u64(MAX_VCO_FREQ, target_rate);
+ if (s <= 1) {
+ divq = 1;
+ *vco_rate = MAX_VCO_FREQ;
+ } else if (s > MAX_DIVQ_DIVISOR) {
+ divq = ilog2(MAX_DIVQ_DIVISOR);
+ *vco_rate = MIN_VCO_FREQ;
+ } else {
+ divq = ilog2(s);
+ *vco_rate = target_rate << divq;
+ }
+
+wcd_out:
+ return divq;
+}
+
+/**
+ * __wrpll_update_parent_rate() - update PLL data when parent rate changes
+ * @c: ptr to a struct analogbits_wrpll_cfg record to write PLL data to
+ * @parent_rate: PLL input refclk rate (pre-R-divider)
+ *
+ * Pre-compute some data used by the PLL configuration algorithm when
+ * the PLL's reference clock rate changes. The intention is to avoid
+ * computation when the parent rate remains constant - expected to be
+ * the common case.
+ *
+ * Returns: 0 upon success or -1 if the reference clock rate is out of range.
+ */
+static int __wrpll_update_parent_rate(struct analogbits_wrpll_cfg *c,
+ unsigned long parent_rate)
+{
+ u8 max_r_for_parent;
+
+ if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
+ return -1;
+
+ c->_parent_rate = parent_rate;
+ max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
+ c->_max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent);
+
+ /* Round up */
+ c->_init_r = div_u64(parent_rate + MAX_POST_DIVR_FREQ - 1,
+ MAX_POST_DIVR_FREQ);
+
+ return 0;
+}
+
+/*
+ * Public functions
+ */
+
+/**
+ * analogbits_wrpll_configure() - compute PLL configuration for a target rate
+ * @c: ptr to a struct analogbits_wrpll_cfg record to write into
+ * @target_rate: target PLL output clock rate (post-Q-divider)
+ * @parent_rate: PLL input refclk rate (pre-R-divider)
+ *
+ * Given a pointer to a PLL context @c, a desired PLL target output
+ * rate @target_rate, and a reference clock input rate @parent_rate,
+ * compute the appropriate PLL signal configuration values. PLL
+ * reprogramming is not glitchless, so the caller should switch any
+ * downstream logic to a different clock source or clock-gate it
+ * before presenting these values to the PLL configuration signals.
+ *
+ * The caller must pass this function a pre-initialized struct
+ * analogbits_wrpll_cfg record: either initialized to zero (with the
+ * exception of the .name and .flags fields) or read from the PLL.
+ *
+ * Context: Any context. Caller must protect the memory pointed to by @c
+ * from simultaneous access or modification.
+ *
+ * Return: 0 upon success; anything else upon failure.
+ */
+int analogbits_wrpll_configure_for_rate(struct analogbits_wrpll_cfg *c,
+ u32 target_rate,
+ unsigned long parent_rate)
+{
+ unsigned long ratio;
+ u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre;
+ u32 best_f, f, post_divr_freq, fbcfg;
+ u8 fbdiv, divq, best_r, r;
+
+ if (!c)
+ return -1;
+
+ if (c->flags == 0) {
+ WARN(1, "%s called with uninitialized PLL config", __func__);
+ return -1;
+ }
+
+ fbcfg = WRPLL_FLAGS_INT_FEEDBACK_MASK | WRPLL_FLAGS_EXT_FEEDBACK_MASK;
+ if ((c->flags & fbcfg) == fbcfg) {
+ WARN(1, "%s called with invalid PLL config", __func__);
+ return -1;
+ }
+
+ if (c->flags == WRPLL_FLAGS_EXT_FEEDBACK_MASK) {
+ WARN(1, "%s: external feedback mode not currently supported",
+ __func__);
+ return -1;
+ }
+
+ /* Initialize rounding data if it hasn't been initialized already */
+ if (parent_rate != c->_parent_rate) {
+ if (__wrpll_update_parent_rate(c, parent_rate)) {
+ pr_err("%s: PLL input rate is out of range\n",
+ __func__);
+ return -1;
+ }
+ }
+
+ c->flags &= ~WRPLL_FLAGS_RESET_MASK;
+
+ /* Put the PLL into bypass if the user requests the parent clock rate */
+ if (target_rate == parent_rate) {
+ c->flags |= WRPLL_FLAGS_BYPASS_MASK;
+ return 0;
+ }
+ c->flags &= ~WRPLL_FLAGS_BYPASS_MASK;
+
+ /* Calculate the Q shift and target VCO rate */
+ divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
+ if (divq == 0)
+ return -1;
+ c->divq = divq;
+
+ /* Precalculate the pre-Q divider target ratio */
+ ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
+
+ fbdiv = __wrpll_calc_fbdiv(c);
+ best_r = 0;
+ best_f = 0;
+ best_delta = MAX_VCO_FREQ;
+
+ /*
+ * Consider all values for R which land within
+ * [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R
+ */
+ for (r = c->_init_r; r <= c->_max_r; ++r) {
+ /* What is the best F we can pick in this case? */
+ f_pre_div = ratio * r;
+ f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT;
+ f >>= (fbdiv - 1);
+
+ post_divr_freq = div_u64(parent_rate, r);
+ vco_pre = fbdiv * post_divr_freq;
+ vco = vco_pre * f;
+
+ /* Ensure rounding didn't take us out of range */
+ if (vco > target_vco_rate) {
+ --f;
+ vco = vco_pre * f;
+ } else if (vco < MIN_VCO_FREQ) {
+ ++f;
+ vco = vco_pre * f;
+ }
+
+ delta = abs(target_rate - vco);
+ if (delta < best_delta) {
+ best_delta = delta;
+ best_r = r;
+ best_f = f;
+ }
+ }
+
+ c->divr = best_r - 1;
+ c->divf = best_f - 1;
+
+ post_divr_freq = div_u64(parent_rate, best_r);
+
+ /* Pick the best PLL jitter filter */
+ c->range = __wrpll_calc_filter_range(post_divr_freq);
+
+ return 0;
+}
+
+/**
+ * analogbits_wrpll_calc_output_rate() - calculate the PLL's target output rate
+ * @c: ptr to a struct analogbits_wrpll_cfg record to read from
+ * @parent_rate: PLL refclk rate
+ *
+ * Given a pointer to the PLL's current input configuration @c and the
+ * PLL's input reference clock rate @parent_rate (before the R
+ * pre-divider), calculate the PLL's output clock rate (after the Q
+ * post-divider)
+ *
+ * Context: Any context. Caller must protect the memory pointed to by @c
+ * from simultaneous modification.
+ *
+ * Return: the PLL's output clock rate, in Hz.
+ */
+unsigned long analogbits_wrpll_calc_output_rate(struct analogbits_wrpll_cfg *c,
+ unsigned long parent_rate)
+{
+ u8 fbdiv;
+ u64 n;
+
+ WARN(c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK,
+ "external feedback mode not yet supported");
+
+ fbdiv = __wrpll_calc_fbdiv(c);
+ n = parent_rate * fbdiv * (c->divf + 1);
+ n = div_u64(n, (c->divr + 1));
+ n >>= c->divq;
+
+ return n;
+}
+
+/**
+ * analogbits_wrpll_calc_max_lock_us() - return the time for the PLL to lock
+ * @c: ptr to a struct analogbits_wrpll_cfg record to read from
+ *
+ * Return the minimum amount of time (in microseconds) that the caller
+ * must wait after reprogramming the PLL to ensure that it is locked
+ * to the input frequency and stable. This is likely to depend on the DIVR
+ * value; this is under discussion with the manufacturer.
+ *
+ * Return: the minimum amount of time the caller must wait for the PLL
+ * to lock (in microseconds)
+ */
+unsigned int analogbits_wrpll_calc_max_lock_us(struct analogbits_wrpll_cfg *c)
+{
+ return MAX_LOCK_US;
+}
{
struct syscon_uc_info *priv = dev_get_uclass_priv(dev);
+ /* Special case for PCI devices, which don't have a regmap */
+ if (device_get_uclass_id(dev->parent) == UCLASS_PCI)
+ return 0;
+
/*
* With OF_PLATDATA we really have no way of knowing the format of
* the device-specific platform data. So we assume that it starts with
#include <dm/device-internal.h>
#include <dm/lists.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
{
const char *isa;
/* save the hart id */
plat->cpu_id = dev_read_addr(dev);
-
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
/* if not found, then look at the parent /cpus node */
&plat->timebase_freq);
/*
- * Bind riscv-timer driver on hart 0
+ * Bind riscv-timer driver on boot hart.
*
* We only instantiate one timer device which is enough for U-Boot.
* Pass the "timebase-frequency" value as the driver data for the
* Return value is not checked since it's possible that the timer
* driver is not included.
*/
- if (!plat->cpu_id && plat->timebase_freq) {
+ if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
drv = lists_driver_lookup_name("riscv_timer");
if (!drv) {
debug("Cannot find the timer driver, not included?\n");
*/
/* Board-specific functions defined in each board's ddr.c */
-extern void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num);
+void __weak fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ return;
+}
struct dynamic_odt {
unsigned int odt_rd_cfg;
u32 resp_windex = 0;
u32 resp_count = 0;
u32 xfer_count = 0;
- u8 resp_err = 0;
+ int resp_err = 0;
u8 cmd_id = 1;
u32 args[3];
int ret;
rbf_size = 0;
}
- ret = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
+ resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
MBOX_CMD_INDIRECT, 3, args);
- if (ret) {
- resp_err = 1;
- } else {
+ if (!resp_err) {
xfer_count++;
cmd_id = add_transfer(xfer_pending,
MBOX_RESP_BUFFER_SIZE,
/* Check for response's status */
if (!resp_err) {
- ret = MBOX_RESP_ERR_GET(resp_hdr);
- debug("Response error code: %08x\n", ret);
- /* Error in response */
- if (ret)
- resp_err = 1;
+ resp_err = MBOX_RESP_ERR_GET(resp_hdr);
+ debug("Response error code: %08x\n", resp_err);
}
ret = get_and_clr_transfer(xfer_pending,
}
if (resp_err && !xfer_count)
- return ret;
+ return resp_err;
}
}
_ Optional clock stretching
_ Software reset
+config SYS_I2C_TEGRA
+ bool "NVIDIA Tegra internal I2C controller"
+ depends on TEGRA
+ help
+ Support for NVIDIA I2C controller available in Tegra SoCs.
+
config SYS_I2C_UNIPHIER
bool "UniPhier I2C driver"
depends on ARCH_UNIPHIER && DM_I2C
};
#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
-static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
u32 ena = enable ? IC_ENABLE_0B : 0;
writel(ena, &i2c_base->ic_enable);
+
+ return 0;
}
#else
-static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
+static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
u32 ena = enable ? IC_ENABLE_0B : 0;
int timeout = 100;
do {
writel(ena, &i2c_base->ic_enable);
if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
- return;
+ return 0;
/*
* Wait 10 times the signaling period of the highest I2C
*/
udelay(25);
} while (timeout--);
-
printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
+
+ return -ETIMEDOUT;
}
#endif
*
* Initialization function.
*/
-static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
+static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
{
+ int ret;
+
/* Disable i2c */
- dw_i2c_enable(i2c_base, false);
+ ret = dw_i2c_enable(i2c_base, false);
+ if (ret)
+ return ret;
writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
&i2c_base->ic_con);
#endif
/* Enable i2c */
- dw_i2c_enable(i2c_base, true);
+ ret = dw_i2c_enable(i2c_base, true);
+ if (ret)
+ return ret;
+
+ return 0;
}
#ifndef CONFIG_DM_I2C
if (&priv->reset_ctl)
reset_deassert(&priv->reset_ctl);
- __dw_i2c_init(priv->regs, 0, 0);
-
- return 0;
+ return __dw_i2c_init(priv->regs, 0, 0);
}
static int designware_i2c_bind(struct udevice *dev)
variable 'keymap' to "de" to select German. Keyboard repeat is
handled by the keyboard itself.
+config TEGRA_KEYBOARD
+ bool "NVIDIA Tegra internal matrix keyboard controller support"
+ help
+ A matrix keyboard connected directly to the internal keyboard
+ controller on Tegra SoCs.
+
config TWL4030_INPUT
bool "Enable TWL4030 Input controller"
help
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>
+#include <wait_bit.h>
#define PAGE_SIZE 4096
dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+ /* Clear IDMAC interrupt */
+ dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
+
data_start = (ulong)cur_idmac;
dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
/* only dma mode need it */
if (!host->fifo_mode) {
+ if (data->flags == MMC_DATA_READ)
+ mask = DWMCI_IDINTEN_RI;
+ else
+ mask = DWMCI_IDINTEN_TI;
+ ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
+ mask, true, 1000, false);
+ if (ret)
+ debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
+ __func__, mask);
+ /* clear interrupts */
+ dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
+
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl &= ~(DWMCI_DMA_EN);
dwmci_writel(host, DWMCI_CTRL, ctrl);
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
+ if (!host->fifo_mode)
+ dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
+
return 0;
}
return 0;
}
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+static int mmc_blk_remove(struct udevice *dev)
+{
+ struct udevice *mmc_dev = dev_get_parent(dev);
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc_dev);
+ struct mmc *mmc = upriv->mmc;
+
+ return mmc_deinit(mmc);
+}
+#endif
+
static const struct blk_ops mmc_blk_ops = {
.read = mmc_bread,
#if CONFIG_IS_ENABLED(MMC_WRITE)
.id = UCLASS_BLK,
.ops = &mmc_blk_ops,
.probe = mmc_blk_probe,
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ .remove = mmc_blk_remove,
+ .flags = DM_FLAG_OS_PREPARE,
+#endif
};
#endif /* CONFIG_BLK */
return err;
}
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+int mmc_deinit(struct mmc *mmc)
+{
+ u32 caps_filtered;
+
+ if (!mmc->has_init)
+ return 0;
+
+ if (IS_SD(mmc)) {
+ caps_filtered = mmc->card_caps &
+ ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
+ MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
+ MMC_CAP(UHS_SDR104));
+
+ return sd_select_mode_and_width(mmc, caps_filtered);
+ } else {
+ caps_filtered = mmc->card_caps &
+ ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
+
+ return mmc_select_mode_and_width(mmc, caps_filtered);
+ }
+}
+#endif
+
int mmc_set_dsr(struct mmc *mmc, u16 val)
{
mmc->dsr = val;
tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
}
+ tmio_sd_writel(priv, hs400 ? 0x704 : 0x300,
+ RENESAS_SDHI_SCC_DT2FF);
+
reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
* This register dropped backward compatibility at version 0x10.
* Write an appropriate value depending on the IP version.
*/
- if (priv->version >= 0x10)
- tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
- else
+ if (priv->version >= 0x10) {
+ if (priv->caps & TMIO_SD_CAP_64BIT)
+ tmio_sd_writel(priv, 0x100, TMIO_SD_HOST_MODE);
+ else
+ tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
+ } else {
tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
+ }
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
config ETH_DESIGNWARE
bool "Synopsys Designware Ethernet MAC"
select PHYLIB
+ imply ETH_DESIGNWARE_SOCFPGA if ARCH_SOCFPGA
help
This MAC is present in SoCs from various vendors. It supports
100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
provide the PHY (physical media interface).
config ETH_DESIGNWARE_SOCFPGA
+ select REGMAP
+ select SYSCON
bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
depends on DM_ETH && ETH_DESIGNWARE
help
#include <asm/arch/system_manager.h>
-enum dwmac_type {
- DWMAC_SOCFPGA_GEN5 = 0,
- DWMAC_SOCFPGA_ARRIA10,
- DWMAC_SOCFPGA_STRATIX10,
-};
-
struct dwmac_socfpga_platdata {
struct dw_eth_pdata dw_eth_pdata;
- enum dwmac_type type;
void *phy_intf;
+ u32 reg_shift;
};
static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
}
pdata->phy_intf = range + args.args[0];
-
- /*
- * Sadly, the Altera DT bindings don't have SoC-specific compatibles,
- * so we have to guesstimate which SoC we are running on from the
- * DWMAC version. Luckily, Altera at least updated the DWMAC with
- * each SoC.
- */
- if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.70a"))
- pdata->type = DWMAC_SOCFPGA_GEN5;
-
- if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.72a"))
- pdata->type = DWMAC_SOCFPGA_ARRIA10;
-
- if (ofnode_device_is_compatible(dev->node, "snps,dwmac-3.74a"))
- pdata->type = DWMAC_SOCFPGA_STRATIX10;
+ pdata->reg_shift = args.args[1];
return designware_eth_ofdata_to_platdata(dev);
}
struct eth_pdata *edata = &pdata->dw_eth_pdata.eth_pdata;
struct reset_ctl_bulk reset_bulk;
int ret;
- u8 modereg;
-
- if (pdata->type == DWMAC_SOCFPGA_ARRIA10) {
- switch (edata->phy_interface) {
- case PHY_INTERFACE_MODE_MII:
- case PHY_INTERFACE_MODE_GMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
- break;
- case PHY_INTERFACE_MODE_RMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
- break;
- case PHY_INTERFACE_MODE_RGMII:
- modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
- break;
- default:
- dev_err(dev, "Unsupported PHY mode\n");
- return -EINVAL;
- }
-
- ret = reset_get_bulk(dev, &reset_bulk);
- if (ret) {
- dev_err(dev, "Failed to get reset: %d\n", ret);
- return ret;
- }
-
- reset_assert_bulk(&reset_bulk);
-
- clrsetbits_le32(pdata->phy_intf,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
- modereg);
-
- reset_release_bulk(&reset_bulk);
+ u32 modereg;
+ u32 modemask;
+
+ switch (edata->phy_interface) {
+ case PHY_INTERFACE_MODE_MII:
+ case PHY_INTERFACE_MODE_GMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+ break;
+ default:
+ dev_err(dev, "Unsupported PHY mode\n");
+ return -EINVAL;
}
+ ret = reset_get_bulk(dev, &reset_bulk);
+ if (ret) {
+ dev_err(dev, "Failed to get reset: %d\n", ret);
+ return ret;
+ }
+
+ reset_assert_bulk(&reset_bulk);
+
+ modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
+ clrsetbits_le32(pdata->phy_intf, modemask,
+ modereg << pdata->reg_shift);
+
+ reset_release_bulk(&reset_bulk);
+
return designware_eth_probe(dev);
}
static int macb_is_gem(struct macb_device *macb)
{
- return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
+ return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
}
#ifndef cpu_is_sama5d2
return -EINVAL;
/*
- * Zynq clock driver didn't support for enable or disable
- * clock. Hence, clk_enable() didn't apply for Zynq
+ * If clock driver didn't support enable or disable then
+ * we get -ENOSYS from clk_enable(). To handle this, we
+ * don't fail for ret == -ENOSYS.
*/
-#ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);
- if (ret)
+ if (ret && ret != -ENOSYS)
return ret;
-#endif
clk_rate = clk_get_rate(&clk);
if (!clk_rate)
--- /dev/null
+config PCH
+ bool "Enable Platform-controller Hub (PCH) support"
+ depends on X86 || SANDBOX
+ help
+ Most x86 chips include a PCH which is responsible for handling
+ parts of the system not handled by that CPU. It supersedes the
+ northbridge / southbridge architecture that was previously used. The
+ PCH allows for higher performance since the memory functions are
+ handled in the CPU.
obj-y += pch-uclass.o
obj-y += pch7.o
obj-y += pch9.o
+obj-$(CONFIG_SANDBOX) += sandbox_pch.o
return ops->get_io_base(dev, iobasep);
}
+int pch_ioctl(struct udevice *dev, ulong req, void *data, int size)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ if (!ops->ioctl)
+ return -ENOSYS;
+
+ return ops->ioctl(dev, req, data, size);
+}
+
UCLASS_DRIVER(pch) = {
.id = UCLASS_PCH,
.name = "pch",
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+struct sandbox_pch_priv {
+ bool protect;
+};
+
+int sandbox_get_pch_spi_protect(struct udevice *dev)
+{
+ struct sandbox_pch_priv *priv = dev_get_priv(dev);
+
+ return priv->protect;
+}
+
+static int sandbox_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
+{
+ *sbasep = 0x10;
+
+ return 0;
+}
+
+static int sandbox_pch_set_spi_protect(struct udevice *dev, bool protect)
+{
+ struct sandbox_pch_priv *priv = dev_get_priv(dev);
+
+ priv->protect = protect;
+
+ return 0;
+}
+
+static int sandbox_pch_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+ *gbasep = 0x20;
+
+ return 0;
+}
+
+static int sandbox_pch_get_io_base(struct udevice *dev, u32 *iobasep)
+{
+ *iobasep = 0x30;
+
+ return 0;
+}
+
+int sandbox_pch_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
+ int size)
+{
+ switch (req) {
+ case PCH_REQ_TEST1:
+ return -ENOSYS;
+ case PCH_REQ_TEST2:
+ return *(char *)data;
+ case PCH_REQ_TEST3:
+ *(char *)data = 'x';
+ return 1;
+ default:
+ return -ENOSYS;
+ }
+}
+
+static const struct pch_ops sandbox_pch_ops = {
+ .get_spi_base = sandbox_pch_get_spi_base,
+ .set_spi_protect = sandbox_pch_set_spi_protect,
+ .get_gpio_base = sandbox_pch_get_gpio_base,
+ .get_io_base = sandbox_pch_get_io_base,
+ .ioctl = sandbox_pch_ioctl,
+};
+
+static const struct udevice_id sandbox_pch_ids[] = {
+ { .compatible = "sandbox,pch" },
+ { }
+};
+
+U_BOOT_DRIVER(sandbox_pch_drv) = {
+ .name = "sandbox-pch",
+ .id = UCLASS_PCH,
+ .of_match = sandbox_pch_ids,
+ .ops = &sandbox_pch_ops,
+ .priv_auto_alloc_size = sizeof(struct sandbox_pch_priv),
+};
return -1;
}
-int pci_hose_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- unsigned long io,
- pci_addr_t mem,
- unsigned long command)
+static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
+ ulong io, pci_addr_t mem, ulong command)
{
u32 bar_response;
unsigned int old_command;
memcpy(&bdesc->revision, &bd.revision, sizeof(bd.revision));
if (verbose) {
- printf(" Device %d: ", 0);
+ printf(" Device %d: ", bdesc->devnum);
dev_print(bdesc);
}
return 0;
scsi_max_devs = 0;
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) {
- ret = scsi_detect_dev(NULL, i, lun,
- &scsi_dev_desc[scsi_max_devs]);
+ struct blk_desc *bdesc = &scsi_dev_desc[scsi_max_devs];
+
+ ret = scsi_detect_dev(NULL, i, lun, bdesc);
if (ret)
continue;
- part_init(&scsi_dev_desc[scsi_max_devs]);
+ part_init(bdesc);
if (verbose) {
- printf(" Device %d: ", 0);
- dev_print(&scsi_dev_desc[scsi_max_devs]);
+ printf(" Device %d: ", bdesc->devnum);
+ dev_print(bdesc);
}
scsi_max_devs++;
} /* next LUN */
};
struct sifive_uart_platdata {
- unsigned int clock;
+ unsigned long clock;
int saved_input_char;
struct uart_sifive *regs;
};
+/**
+ * Find minimum divisor divides in_freq to max_target_hz;
+ * Based on uart driver n SiFive FSBL.
+ *
+ * f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
+ * The nearest integer solution requires rounding up as to not exceed
+ * max_target_hz.
+ * div = ceil(f_in / f_baud) - 1
+ * = floor((f_in - 1 + f_baud) / f_baud) - 1
+ * This should not overflow as long as (f_in - 1 + f_baud) does not exceed
+ * 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+ */
+static inline unsigned int uart_min_clk_divisor(unsigned long in_freq,
+ unsigned long max_target_hz)
+{
+ unsigned long quotient =
+ (in_freq + max_target_hz - 1) / (max_target_hz);
+ /* Avoid underflow */
+ if (quotient == 0)
+ return 0;
+ else
+ return quotient - 1;
+}
+
/* Set up the baud rate in gd struct */
static void _sifive_serial_setbrg(struct uart_sifive *regs,
unsigned long clock, unsigned long baud)
{
- writel((u32)((clock / baud) - 1), ®s->div);
+ writel((uart_min_clk_divisor(clock, baud)), ®s->div);
}
static void _sifive_serial_init(struct uart_sifive *regs)
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
{
- int err;
+ int ret;
struct clk clk;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ u32 clock = 0;
- err = clk_get_by_index(dev, 0, &clk);
- if (!err) {
- err = clk_get_rate(&clk);
- if (!IS_ERR_VALUE(err))
- platdata->clock = err;
- } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (IS_ERR_VALUE(ret)) {
debug("SiFive UART failed to get clock\n");
- return err;
- }
-
- if (!platdata->clock)
- platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0);
- if (!platdata->clock) {
- debug("SiFive UART clock not defined\n");
- return -EINVAL;
+ ret = dev_read_u32(dev, "clock-frequency", &clock);
+ if (IS_ERR_VALUE(ret)) {
+ debug("SiFive UART clock not defined\n");
+ return 0;
+ }
+ } else {
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ debug("SiFive UART clock get rate failed\n");
+ return 0;
+ }
}
-
+ platdata->clock = clock;
_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
return 0;
option provides an implementation for sound_init() and
sound_play().
+config SOUND_I8254
+ bool "Intel i8254 timer / beeper"
+ depends on SOUND
+ help
+ This enables support for a beeper that uses the i8254 timer chip.
+ This can emit beeps at a fixed frequency. It is possible to control
+ the length of the beeps, by turning a beep on, waiting for a period
+ of time, then turning it off.
+
+ This is quite an old feature, called PIT (Programmable Interval
+ Timer), but is nonetheless still available on modern x86 machines.
+
+config SOUND_INTEL_HDA
+ bool "Intel HDA audio codec"
+ depends on SOUND
+ help
+ Most Intel chips have an HDA (High-definition audio) codec which can
+ be used by U-Boot to play simple beeps. This is also sometimes called
+ Azalia which was the development code-name. It requires setup
+ information in the device tree (see intel-hda.txt).
+
+config SOUND_IVYBRIDGE
+ bool "Intel Ivybridge sound support"
+ depends on SOUND
+ select SOUND_INTEL_HDA
+ help
+ Enable sound output on supported Intel Ivybridge-based boards. This
+ driver uses Intel's High-definition Audio (HDA) architecture,
+ sometimes called Azalia. The audio codec is detected using a
+ semi-automatic mechanism.
+
config SOUND_MAX98088
bool "Support Maxim max98088 audio codec"
depends on I2S
audio data and I2C for codec control. At present it only works
with the Samsung I2S driver.
+config SOUND_RT5677
+ bool "Support Realtek RT5677 audio codec"
+ depends on SOUND
+ help
+ Enable the Realtek RT5677 audio codec. This is an I2S device used on
+ some Chromebooks from around 2015 ('auron'). It is configured using
+ an I2C interface and supports multiple sound inputs and outputs,
+ including digital microphones.
+
config SOUND_SANDBOX
bool "Support sandbox emulated audio codec"
depends on SANDBOX && SOUND
obj-$(CONFIG_SOUND_MAX98088) += max98088.o maxim_codec.o
obj-$(CONFIG_SOUND_MAX98090) += max98090.o maxim_codec.o
obj-$(CONFIG_SOUND_MAX98095) += max98095.o maxim_codec.o
+obj-$(CONFIG_SOUND_INTEL_HDA) += hda_codec.o
+obj-$(CONFIG_SOUND_I8254) += i8254_beep.o
+obj-$(CONFIG_SOUND_RT5677) += rt5677.o
+obj-$(CONFIG_INTEL_BROADWELL) += broadwell_i2s.o broadwell_sound.o
+obj-$(CONFIG_SOUND_IVYBRIDGE) += ivybridge_sound.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Intel Broadwell I2S driver
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Modified from dc i2s/broadwell/broadwell.c
+ */
+
+#define LOG_CATEGORY UCLASS_I2S
+
+#include <common.h>
+#include <dm.h>
+#include <i2s.h>
+#include <asm/io.h>
+#include "broadwell_i2s.h"
+
+enum {
+ BDW_SHIM_START_ADDRESS = 0xfb000,
+ BDW_SSP0_START_ADDRESS = 0xfc000,
+ BDW_SSP1_START_ADDRESS = 0xfd000,
+};
+
+struct broadwell_i2s_priv {
+ enum frame_sync_rel_timing_t rel_timing;
+ enum frame_sync_pol_t sfrm_polarity;
+ enum end_transfer_state_t end_transfer_state;
+ enum clock_mode_t sclk_mode;
+ uint sclk_dummy_stop; /* 0-31 */
+ uint sclk_frame_width; /* 1-38 */
+ struct i2s_shim_regs *shim;
+ struct broadwell_i2s_regs *regs;
+};
+
+static void init_shim_csr(struct broadwell_i2s_priv *priv)
+{
+ /*
+ * Select SSP clock
+ * Turn off low power clock
+ * Set PIO mode
+ * Stall DSP core
+ */
+ clrsetbits_le32(&priv->shim->csr,
+ SHIM_CS_S0IOCS | SHIM_CS_LPCS | SHIM_CS_DCS_MASK,
+ SHIM_CS_S1IOCS | SHIM_CS_SBCS_SSP1_24MHZ |
+ SHIM_CS_SBCS_SSP0_24MHZ | SHIM_CS_SDPM_PIO_SSP1 |
+ SHIM_CS_SDPM_PIO_SSP0 | SHIM_CS_STALL |
+ SHIM_CS_DCS_DSP32_AF32);
+}
+
+static void init_shim_clkctl(struct i2s_uc_priv *uc_priv,
+ struct broadwell_i2s_priv *priv)
+{
+ u32 clkctl = readl(&priv->shim->clkctl);
+
+ /* Set 24Mhz mclk, prevent local clock gating, enable SSP0 clock */
+ clkctl &= SHIM_CLKCTL_RESERVED;
+ clkctl |= SHIM_CLKCTL_MCLK_24MHZ | SHIM_CLKCTL_DCPLCG;
+
+ /* Enable requested SSP interface */
+ if (uc_priv->id)
+ clkctl |= SHIM_CLKCTL_SCOE_SSP1 | SHIM_CLKCTL_SFLCGB_SSP1_CGD;
+ else
+ clkctl |= SHIM_CLKCTL_SCOE_SSP0 | SHIM_CLKCTL_SFLCGB_SSP0_CGD;
+
+ writel(clkctl, &priv->shim->clkctl);
+}
+
+static void init_sscr0(struct i2s_uc_priv *uc_priv,
+ struct broadwell_i2s_priv *priv)
+{
+ u32 sscr0;
+ uint scale;
+
+ /* Set data size based on BPS */
+ if (uc_priv->bitspersample > 16)
+ sscr0 = (uc_priv->bitspersample - 16 - 1) << SSP_SSC0_DSS_SHIFT
+ | SSP_SSC0_EDSS;
+ else
+ sscr0 = (uc_priv->bitspersample - 1) << SSP_SSC0_DSS_SHIFT;
+
+ /* Set network mode, Stereo PSP frame format */
+ sscr0 |= SSP_SSC0_MODE_NETWORK |
+ SSP_SSC0_FRDC_STEREO |
+ SSP_SSC0_FRF_PSP |
+ SSP_SSC0_TIM |
+ SSP_SSC0_RIM |
+ SSP_SSC0_ECS_PCH |
+ SSP_SSC0_NCS_PCH |
+ SSP_SSC0_ACS_PCH;
+
+ /* Scale 24MHz MCLK */
+ scale = uc_priv->audio_pll_clk / uc_priv->samplingrate / uc_priv->bfs;
+ sscr0 |= scale << SSP_SSC0_SCR_SHIFT;
+
+ writel(sscr0, &priv->regs->sscr0);
+}
+
+static void init_sscr1(struct broadwell_i2s_priv *priv)
+{
+ u32 sscr1 = readl(&priv->regs->sscr1);
+
+ sscr1 &= SSP_SSC1_RESERVED;
+
+ /* Set as I2S master */
+ sscr1 |= SSP_SSC1_SCLKDIR_MASTER | SSP_SSC1_SCLKDIR_MASTER;
+
+ /* Enable TXD tristate behavior for PCH */
+ sscr1 |= SSP_SSC1_TTELP | SSP_SSC1_TTE;
+
+ /* Disable DMA Tx/Rx service request */
+ sscr1 |= SSP_SSC1_TSRE | SSP_SSC1_RSRE;
+
+ /* Clock on during transfer */
+ sscr1 |= SSP_SSC1_SCFR;
+
+ /* Set FIFO thresholds */
+ sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_RFT_SHIFT;
+ sscr1 |= SSP_FIFO_SIZE << SSP_SSC1_TFT_SHIFT;
+
+ /* Disable interrupts */
+ sscr1 &= ~(SSP_SSC1_EBCEI | SSP_SSC1_TINTE | SSP_SSC1_PINTE);
+ sscr1 &= ~(SSP_SSC1_LBM | SSP_SSC1_RWOT);
+
+ writel(sscr1, &priv->regs->sscr1);
+}
+
+static void init_sspsp(struct broadwell_i2s_priv *priv)
+{
+ u32 sspsp = readl(&priv->regs->sspsp);
+
+ sspsp &= SSP_PSP_RESERVED;
+ sspsp |= priv->sclk_mode << SSP_PSP_SCMODE_SHIFT;
+ sspsp |= (priv->sclk_dummy_stop << SSP_PSP_DMYSTOP_SHIFT) &
+ SSP_PSP_DMYSTOP_MASK;
+ sspsp |= (priv->sclk_dummy_stop >> 2 << SSP_PSP_EDYMSTOP_SHIFT) &
+ SSP_PSP_EDMYSTOP_MASK;
+ sspsp |= priv->sclk_frame_width << SSP_PSP_SFRMWDTH_SHIFT;
+
+ /* Frame Sync Relative Timing */
+ if (priv->rel_timing == NEXT_FRMS_AFTER_END_OF_T4)
+ sspsp |= SSP_PSP_FSRT;
+ else
+ sspsp &= ~SSP_PSP_FSRT;
+
+ /* Serial Frame Polarity */
+ if (priv->sfrm_polarity == SSP_FRMS_ACTIVE_HIGH)
+ sspsp |= SSP_PSP_SFRMP;
+ else
+ sspsp &= ~SSP_PSP_SFRMP;
+
+ /* End Data Transfer State */
+ if (priv->end_transfer_state == SSP_END_TRANSFER_STATE_LOW)
+ sspsp &= ~SSP_PSP_ETDS;
+ else
+ sspsp |= SSP_PSP_ETDS;
+
+ writel(sspsp, &priv->regs->sspsp);
+}
+
+static void init_ssp_time_slot(struct broadwell_i2s_priv *priv)
+{
+ writel(3, &priv->regs->sstsa);
+ writel(3, &priv->regs->ssrsa);
+}
+
+static int bdw_i2s_init(struct udevice *dev)
+{
+ struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct broadwell_i2s_priv *priv = dev_get_priv(dev);
+
+ init_shim_csr(priv);
+ init_shim_clkctl(uc_priv, priv);
+ init_sscr0(uc_priv, priv);
+ init_sscr1(priv);
+ init_sspsp(priv);
+ init_ssp_time_slot(priv);
+
+ return 0;
+}
+
+static void bdw_i2s_enable(struct broadwell_i2s_priv *priv)
+{
+ setbits_le32(&priv->regs->sscr0, SSP_SSC0_SSE);
+ setbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
+}
+
+static void bdw_i2s_disable(struct broadwell_i2s_priv *priv)
+{
+ clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
+ clrbits_le32(&priv->regs->sstsa, SSP_SSTSA_EN);
+}
+
+static int broadwell_i2s_tx_data(struct udevice *dev, void *data,
+ uint data_size)
+{
+ struct broadwell_i2s_priv *priv = dev_get_priv(dev);
+ u32 *ptr = data;
+
+ log_debug("data=%p, data_size=%x\n", data, data_size);
+ if (data_size < SSP_FIFO_SIZE) {
+ log_err("Invalid I2S data size\n");
+ return -ENODATA;
+ }
+
+ /* Enable I2S interface */
+ bdw_i2s_enable(priv);
+
+ /* Transfer data */
+ while (data_size > 0) {
+ ulong start = timer_get_us() + 100000;
+
+ /* Write data if transmit FIFO has room */
+ if (readl(&priv->regs->sssr) & SSP_SSS_TNF) {
+ writel(*ptr++, &priv->regs->ssdr);
+ data_size -= sizeof(*ptr);
+ } else {
+ if ((long)(timer_get_us() - start) > 0) {
+ /* Disable I2S interface */
+ bdw_i2s_disable(priv);
+ log_debug("I2S Transfer Timeout\n");
+ return -ETIMEDOUT;
+ }
+ }
+ }
+
+ /* Disable I2S interface */
+ bdw_i2s_disable(priv);
+ log_debug("done\n");
+
+ return 0;
+}
+
+static int broadwell_i2s_probe(struct udevice *dev)
+{
+ struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct broadwell_i2s_priv *priv = dev_get_priv(dev);
+ struct udevice *adsp = dev_get_parent(dev);
+ u32 bar0, offset;
+ int ret;
+
+ bar0 = dm_pci_read_bar32(adsp, 0);
+ if (!bar0) {
+ log_debug("Cannot read adsp bar0\n");
+ return -EINVAL;
+ }
+ offset = dev_read_addr_index(dev, 0);
+ if (offset == FDT_ADDR_T_NONE) {
+ log_debug("Cannot read address index 0\n");
+ return -EINVAL;
+ }
+ uc_priv->base_address = bar0 + offset;
+
+ /*
+ * Hard-code these values. If other settings are required we can add
+ * this to the device tree.
+ */
+ uc_priv->rfs = 64;
+ uc_priv->bfs = 32;
+ uc_priv->audio_pll_clk = 24 * 1000 * 1000;
+ uc_priv->samplingrate = 48000;
+ uc_priv->bitspersample = 16;
+ uc_priv->channels = 2;
+ uc_priv->id = 0;
+
+ priv->shim = (struct i2s_shim_regs *)uc_priv->base_address;
+ priv->sfrm_polarity = SSP_FRMS_ACTIVE_LOW;
+ priv->end_transfer_state = SSP_END_TRANSFER_STATE_LOW;
+ priv->sclk_mode = SCLK_MODE_DDF_DSR_ISL;
+ priv->rel_timing = NEXT_FRMS_WITH_LSB_PREVIOUS_FRM;
+ priv->sclk_dummy_stop = 0;
+ priv->sclk_frame_width = 31;
+
+ offset = dev_read_addr_index(dev, 1 + uc_priv->id);
+ if (offset == FDT_ADDR_T_NONE) {
+ log_debug("Cannot read address index %d\n", 1 + uc_priv->id);
+ return -EINVAL;
+ }
+ log_debug("bar0=%x, uc_priv->base_address=%x, offset=%x\n", bar0,
+ uc_priv->base_address, offset);
+ priv->regs = (struct broadwell_i2s_regs *)(bar0 + offset);
+
+ ret = bdw_i2s_init(dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static const struct i2s_ops broadwell_i2s_ops = {
+ .tx_data = broadwell_i2s_tx_data,
+};
+
+static const struct udevice_id broadwell_i2s_ids[] = {
+ { .compatible = "intel,broadwell-i2s" },
+ { }
+};
+
+U_BOOT_DRIVER(broadwell_i2s) = {
+ .name = "broadwell_i2s",
+ .id = UCLASS_I2S,
+ .of_match = broadwell_i2s_ids,
+ .probe = broadwell_i2s_probe,
+ .ops = &broadwell_i2s_ops,
+ .priv_auto_alloc_size = sizeof(struct broadwell_i2s_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Intel Broadwell I2S driver
+ *
+ * Copyright 2019 Google LLC
+ *
+ * Modified from dc i2s/broadwell/broadwell.h
+ */
+
+#ifndef __BROADWELL_I2S_H__
+#define __BROADWELL_I2S_H__
+
+enum {
+ SSP_FIFO_SIZE = 7,
+};
+
+enum frame_sync_rel_timing_t {
+ NEXT_FRMS_AFTER_END_OF_T4 = 0,
+ NEXT_FRMS_WITH_LSB_PREVIOUS_FRM,
+};
+
+enum frame_sync_pol_t {
+ SSP_FRMS_ACTIVE_LOW = 0,
+ SSP_FRMS_ACTIVE_HIGH,
+};
+
+enum end_transfer_state_t {
+ SSP_END_TRANSFER_STATE_LOW = 0,
+ SSP_END_TRANSFER_STATE_PEVIOUS_BIT,
+};
+
+enum clock_mode_t {
+ /* Data driven (falling), data sampled (rising), idle state (low) */
+ SCLK_MODE_DDF_DSR_ISL,
+ /* Data driven (rising), data sampled (falling), idle state (low) */
+ SCLK_MODE_DDR_DSF_ISL,
+ /* Data driven (rising), data sampled (falling), idle state (high) */
+ SCLK_MODE_DDR_DSF_ISH,
+ /* Data driven (falling), data sampled (rising), idle state (high) */
+ SCLK_MODE_DDF_DSR_ISH,
+};
+
+struct i2s_shim_regs {
+ u32 csr; /* 0x00 */
+ u32 reserved0[29]; /* 0x14 - 0x77 */
+ u32 clkctl; /* 0x78 */
+ u32 reserved1; /* 0x7c */
+ u32 cs2; /* 0x80 */
+};
+
+struct broadwell_i2s_regs {
+ u32 sscr0; /* 0x00 */
+ u32 sscr1; /* 0x04 */
+ u32 sssr; /* 0x08 */
+ u32 ssitr; /* 0x0c */
+ u32 ssdr; /* 0x10 */
+ u32 reserved0[5]; /* 0x14 - 0x27 */
+ u32 ssto; /* 0x28 */
+ u32 sspsp; /* 0x2c */
+ u32 sstsa; /* 0x30 */
+ u32 ssrsa; /* 0x34 */
+ u32 sstss; /* 0x38 */
+ u32 sscr2; /* 0x40 */
+ u32 sspsp2; /* 0x44 */
+};
+
+/* SHIM Configuration & Status */
+enum {
+ /* Low Power Clock Select */
+ SHIM_CS_LPCS = 1 << 31,
+ /* SSP Force Clock Running */
+ SHIM_CS_SFCR_SSP1 = 1 << 28,
+ SHIM_CS_SFCR_SSP0 = 1 << 27,
+ /* SSP1 IO Clock Select */
+ SHIM_CS_S1IOCS = 1 << 23,
+ /* SSP0 IO Clock Select */
+ SHIM_CS_S0IOCS = 1 << 21,
+ /* Parity Check Enable */
+ SHIM_CS_PCE = 1 << 15,
+ /* SSP DMA or PIO Mode */
+ SHIM_CS_SDPM_PIO_SSP1 = 1 << 12,
+ SHIM_CS_SDPM_DMA_SSP1 = 0 << 12,
+ SHIM_CS_SDPM_PIO_SSP0 = 1 << 11,
+ SHIM_CS_SDPM_DMA_SSP0 = 0 << 11,
+ /* Run / Stall */
+ SHIM_CS_STALL = 1 << 10,
+ /* DSP Clock Select */
+ SHIM_CS_DCS_DSP320_AF80 = 0 << 4,
+ SHIM_CS_DCS_DSP160_AF80 = 1 << 4,
+ SHIM_CS_DCS_DSP80_AF80 = 2 << 4,
+ SHIM_CS_DCS_DSP320_AF160 = 4 << 4,
+ SHIM_CS_DCS_DSP160_AF160 = 5 << 4,
+ SHIM_CS_DCS_DSP32_AF32 = 6 << 4,
+ SHIM_CS_DCS_MASK = 7 << 4,
+ /* SSP Base Clock Select */
+ SHIM_CS_SBCS_SSP0_24MHZ = 1 << 3,
+ SHIM_CS_SBCS_SSP0_32MHZ = 0 << 3,
+ SHIM_CS_SBCS_SSP1_24MHZ = 1 << 2,
+ SHIM_CS_SBCS_SSP1_32MHZ = 0 << 2,
+ /* DSP Core Reset */
+ SHIM_CS_RST = 1 << 1,
+};
+
+/* SHIM Clock Control */
+enum {
+ /* Clock Frequency Change In Progress */
+ SHIM_CLKCTL_CFCIP = 1 << 31,
+ /* SSP MCLK Output Select */
+ SHIM_CLKCTL_MCLK_MASK = 0x3,
+ SHIM_CLKCTL_MCLK_SHIFT = 24,
+ SHIM_CLKCTL_MCLK_DISABLED = 0 << 24,
+ SHIM_CLKCTL_MCLK_6MHZ = 1 << 24,
+ SHIM_CLKCTL_MCLK_12MHZ = 2 << 24,
+ SHIM_CLKCTL_MCLK_24MHZ = 3 << 24,
+ /* DSP Core Prevent Local Clock Gating */
+ SHIM_CLKCTL_DCPLCG = 1 << 18,
+ /* SSP Clock Output Enable */
+ SHIM_CLKCTL_SCOE_SSP1 = 1 << 17,
+ SHIM_CLKCTL_SCOE_SSP0 = 1 << 16,
+ /* DMA Engine Force Local Clock Gating */
+ SHIM_CLKCTL_DEFLCGB_DMA1_CGE = 0 << 6,
+ SHIM_CLKCTL_DEFLCGB_DMA1_CGD = 1 << 6,
+ SHIM_CLKCTL_DEFLCGB_DMA0_CGE = 0 << 5,
+ SHIM_CLKCTL_DEFLCGB_DMA0_CGD = 1 << 5,
+ /* SSP Force Local Clock Gating */
+ SHIM_CLKCTL_SFLCGB_SSP1_CGE = 0 << 1,
+ SHIM_CLKCTL_SFLCGB_SSP1_CGD = 1 << 1,
+ SHIM_CLKCTL_SFLCGB_SSP0_CGE = 0 << 0,
+ SHIM_CLKCTL_SFLCGB_SSP0_CGD = 1 << 0,
+
+ /* Reserved bits: 30:26, 23:19, 15:7, 4:2 */
+ SHIM_CLKCTL_RESERVED = 0x1f << 26 | 0x1f << 19 | 0x1ff << 7 | 0x7 << 2,
+};
+
+/* SSP Status */
+enum {
+ /* Bit Count Error */
+ SSP_SSS_BCE = 1 << 23,
+ /* Clock Sync Statu s*/
+ SSP_SSS_CSS = 1 << 22,
+ /* Transmit FIFO Underrun */
+ SSP_SSS_TUR = 1 << 21,
+ /* End Of Chain */
+ SSP_SSS_EOC = 1 << 20,
+ /* Receiver Time-out Interrupt */
+ SSP_SSS_TINT = 1 << 19,
+ /* Peripheral Trailing Byte Interrupt */
+ SSP_SSS_PINT = 1 << 18,
+ /* Received FIFO Level */
+ SSP_RFL_MASK = 0xf,
+ SSP_RFL_SHIFT = 12,
+ /* Transmit FIFO Level */
+ SSP_TFL_MASK = 0xf,
+ SSP_TFL_SHIFT = 8,
+ /* Receive FIFO Overrun */
+ SSP_SSS_ROR = 1 << 7,
+ /* Receive FIFO Service Request */
+ SSP_SSS_RFS = 1 << 6,
+ /* Transmit FIFO Service Request */
+ SSP_SSS_TFS = 1 << 5,
+ /* SSP Busy */
+ SSP_SSS_BSY = 1 << 4,
+ /* Receive FIFO Not Empty */
+ SSP_SSS_RNE = 1 << 3,
+ /* Transmit FIFO Not Full */
+ SSP_SSS_TNF = 1 << 2,
+};
+
+/* SSP Control 0 */
+enum {
+ /* Mode */
+ SSP_SSC0_MODE_NORMAL = 0 << 31,
+ SSP_SSC0_MODE_NETWORK = 1 << 31,
+ /* Audio Clock Select */
+ SSP_SSC0_ACS_PCH = 0 << 30,
+ /* Frame Rate Divider Control (0-7) */
+ SSP_SSC0_FRDC_MASK = 0x7,
+ SSP_SSC0_FRDC_SHIFT = 24,
+ SSP_SSC0_FRDC_STEREO = 1 << 24,
+ /* Transmit FIFO Underrun Interrupt Mask */
+ SSP_SSC0_TIM = 1 << 23,
+ /* Receive FIFO Underrun Interrupt Mask */
+ SSP_SSC0_RIM = 1 << 22,
+ /* Network Clock Select */
+ SSP_SSC0_NCS_PCH = 0 << 21,
+ /* Extended Data Size Select */
+ SSP_SSC0_EDSS = 1 << 20,
+ /* Serial Clock Rate (0-4095) */
+ SSP_SSC0_SCR_SHIFT = 8,
+ SSP_SSC0_SCR_MASK = 0xfff << SSP_SSC0_SCR_SHIFT,
+ /* Synchronous Serial Port Enable */
+ SSP_SSC0_SSE = 1 << 7,
+ /* External Clock Select */
+ SSP_SSC0_ECS_PCH = 0 << 6,
+ /* Frame Format */
+ SSP_SSC0_FRF_MOTOROLA_SPI = 0 << 4,
+ SSP_SSC0_FRF_TI_SSP = 1 << 4,
+ SSP_SSC0_FRF_NS_MICROWIRE = 2 << 4,
+ SSP_SSC0_FRF_PSP = 3 << 4,
+ /* Data Size Select */
+ SSP_SSC0_DSS_SHIFT = 0,
+ SSP_SSC0_DSS_MASK = 0xf << SSP_SSC0_DSS_SHIFT,
+};
+
+/* SSP Control 1 */
+enum {
+ /* TXD Tristate Enable on Last Phase */
+ SSP_SSC1_TTELP = 1 << 31,
+ /* TXD Tristate Enable */
+ SSP_SSC1_TTE = 1 << 30,
+ /* Enable Bit Count Error Interrupt */
+ SSP_SSC1_EBCEI = 1 << 29,
+ /* Slave Clock Running */
+ SSP_SSC1_SCFR = 1 << 28,
+ /* Enable Clock Request A */
+ SSP_SSC1_ECRA = 1 << 27,
+ /* Enable Clock Request B */
+ SSP_SSC1_ECRB = 1 << 26,
+ /* SSPCLK Direction */
+ SSP_SSC1_SCLKDIR_SLAVE = 1 << 25,
+ SSP_SSC1_SCLKDIR_MASTER = 0 << 25,
+ /* SSPFRM Direction */
+ SSP_SSC1_SFRMDIR_SLAVE = 1 << 24,
+ SSP_SSC1_SFRMDIR_MASTER = 0 << 24,
+ /* Receive without Transmit */
+ SSP_SSC1_RWOT = 1 << 23,
+ /* Trailing Byte */
+ SSP_SSC1_TRAIL = 1 << 22,
+ /* DMA Tx Service Request Enable */
+ SSP_SSC1_TSRE = 1 << 21,
+ /* DMA Rx Service Request Enable */
+ SSP_SSC1_RSRE = 1 << 20,
+ /* Receiver Timeout Interrupt Enable */
+ SSP_SSC1_TINTE = 1 << 19,
+ /* Periph. Trailing Byte Int. Enable */
+ SSP_SSC1_PINTE = 1 << 18,
+ /* Invert Frame Signal */
+ SSP_SSC1_IFS = 1 << 16,
+ /* Select FIFO for EFWR: test mode */
+ SSP_SSC1_STRF = 1 << 15,
+ /* Enable FIFO Write/Read: test mode */
+ SSP_SSC1_EFWR = 1 << 14,
+ /* Receive FIFO Trigger Threshold */
+ SSP_SSC1_RFT_SHIFT = 10,
+ SSP_SSC1_RFT_MASK = 0xf << SSP_SSC1_RFT_SHIFT,
+ /* Transmit FIFO Trigger Threshold */
+ SSP_SSC1_TFT_SHIFT = 6,
+ SSP_SSC1_TFT_MASK = 0xf << SSP_SSC1_TFT_SHIFT,
+ /* Microwire Transmit Data Size */
+ SSP_SSC1_MWDS = 1 << 5,
+ /* Motorola SPI SSPSCLK Phase Setting*/
+ SSP_SSC1_SPH = 1 << 4,
+ /* Motorola SPI SSPSCLK Polarity */
+ SSP_SSC1_SPO = 1 << 3,
+ /* Loopback mode: test mode */
+ SSP_SSC1_LBM = 1 << 2,
+ /* Transmit FIFO Interrupt Enable */
+ SSP_SSC1_TIE = 1 << 1,
+ /* Receive FIFO Interrupt Enable */
+ SSP_SSC1_RIE = 1 << 0,
+
+ SSP_SSC1_RESERVED = 17 << 1,
+};
+
+/* SSP Programmable Serial Protocol */
+enum {
+ /* Extended Dummy Stop (0-31) */
+ SSP_PSP_EDYMSTOP_SHIFT = 26,
+ SSP_PSP_EDMYSTOP_MASK = 0x7 << SSP_PSP_EDYMSTOP_SHIFT,
+ /* Frame Sync Relative Timing */
+ SSP_PSP_FSRT = 1 << 25,
+ /* Dummy Stop low bits */
+ SSP_PSP_DMYSTOP_SHIFT = 23,
+ SSP_PSP_DMYSTOP_MASK = 0x3 << SSP_PSP_DMYSTOP_SHIFT,
+ /* Serial Frame Width */
+ SSP_PSP_SFRMWDTH_SHIFT = 16,
+ SSP_PSP_SFRMWDTH_MASK = 0x3f << SSP_PSP_SFRMWDTH_SHIFT,
+ /* Serial Frame Delay */
+ SSP_PSP_SFRMDLY_MASK = 0x7f,
+ SSP_PSP_SFRMDLY_SHIFT = 9,
+ /* Start Delay */
+ SSP_PSP_STRTDLY_MASK = 0x7,
+ SSP_PSP_STRTDLY_SHIFT = 4,
+ /* End of Transfer Data State */
+ SSP_PSP_ETDS = 1 << 3,
+ /* Serial Frame Polarity */
+ SSP_PSP_SFRMP = 1 << 2,
+ /* Serial Clock Mode */
+ SSP_PSP_SCMODE_SHIFT = 0,
+ SSP_PSP_SCMODE_MASK = 0x3 << SSP_PSP_SCMODE_SHIFT,
+
+ SSP_PSP_RESERVED = 1 << 22,
+};
+
+/* SSP TX Time Slot Active */
+enum {
+ SSP_SSTSA_EN = 1 << 8,
+ SSP_SSTSA_MASK = 0xff,
+};
+
+#endif /* __BROADWELL_I2S_H__ */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sound for broadwell
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#define LOG_CATEGORY UCLASS_SOUND
+
+#include <common.h>
+#include <audio_codec.h>
+#include <dm.h>
+#include <i2s.h>
+#include <sound.h>
+
+static int broadwell_sound_probe(struct udevice *dev)
+{
+ return sound_find_codec_i2s(dev);
+}
+
+static int broadwell_sound_setup(struct udevice *dev)
+{
+ struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s);
+ int ret;
+
+ if (uc_priv->setup_done)
+ return -EALREADY;
+ ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id,
+ i2c_priv->samplingrate,
+ i2c_priv->samplingrate * i2c_priv->rfs,
+ i2c_priv->bitspersample,
+ i2c_priv->channels);
+ if (ret)
+ return ret;
+ uc_priv->setup_done = true;
+
+ return 0;
+}
+
+static int broadwell_sound_play(struct udevice *dev, void *data, uint data_size)
+{
+ struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ return i2s_tx_data(uc_priv->i2s, data, data_size);
+}
+
+static const struct sound_ops broadwell_sound_ops = {
+ .setup = broadwell_sound_setup,
+ .play = broadwell_sound_play,
+};
+
+static const struct udevice_id broadwell_sound_ids[] = {
+ { .compatible = "google,samus-sound" },
+ { }
+};
+
+U_BOOT_DRIVER(broadwell_sound_drv) = {
+ .name = "broadwell_sound",
+ .id = UCLASS_SOUND,
+ .of_match = broadwell_sound_ids,
+ .probe = broadwell_sound_probe,
+ .ops = &broadwell_sound_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Implementation of per-board codec beeping
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright 2018 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_SOUND
+
+#include <common.h>
+#include <dm.h>
+#include <hda_codec.h>
+#include <pci.h>
+#include <sound.h>
+#include <asm/io.h>
+#include <dt-bindings/sound/azalia.h>
+
+/**
+ * struct hda_regs - HDA registers
+ *
+ * https://wiki.osdev.org/Intel_High_Definition_Audio
+ * https://www.intel.com/content/www/us/en/standards/high-definition-audio-specification.html
+ */
+struct hda_regs {
+ u16 gcap;
+ u8 vmin;
+ u8 vmaj;
+ u16 outpay;
+ u16 inpay;
+ u32 gctl;
+ u16 wakeen;
+ u16 statests;
+ u8 reserved[0x50];
+ u32 cmd; /* 0x60 */
+ u32 resp;
+ u32 icii;
+};
+
+enum {
+ HDA_ICII_BUSY = BIT(0),
+ HDA_ICII_VALID = BIT(1),
+
+ /* Common node IDs */
+ HDA_ROOT_NODE = 0x00,
+
+ /* HDA verbs fields */
+ HDA_VERB_NID_S = 20,
+ HDA_VERB_VERB_S = 8,
+ HDA_VERB_PARAM_S = 0,
+
+ HDA_VERB_GET_PARAMS = 0xf00,
+ HDA_VERB_SET_BEEP = 0x70a,
+
+ /* GET_PARAMS parameter IDs */
+ GET_PARAMS_NODE_COUNT = 0x04,
+ GET_PARAMS_AUDIO_GROUP_CAPS = 0x08,
+ GET_PARAMS_AUDIO_WIDGET_CAPS = 0x09,
+
+ /* Sub-node fields */
+ NUM_SUB_NODES_S = 0,
+ NUM_SUB_NODES_M = 0xff << NUM_SUB_NODES_S,
+ FIRST_SUB_NODE_S = 16,
+ FIRST_SUB_NODE_M = 0xff << FIRST_SUB_NODE_S,
+
+ /* Get Audio Function Group Capabilities fields */
+ AUDIO_GROUP_CAPS_BEEP_GEN = 0x10000,
+
+ /* Get Audio Widget Capabilities fields */
+ AUDIO_WIDGET_TYPE_BEEP = 0x7,
+ AUDIO_WIDGET_TYPE_S = 20,
+ AUDIO_WIDGET_TYPE_M = 0xf << AUDIO_WIDGET_TYPE_S,
+
+ BEEP_FREQ_BASE = 12000,
+};
+
+static inline uint hda_verb(uint nid, uint verb, uint param)
+{
+ return nid << HDA_VERB_NID_S | verb << HDA_VERB_VERB_S |
+ param << HDA_VERB_PARAM_S;
+}
+
+int hda_wait_for_ready(struct hda_regs *regs)
+{
+ int timeout = 1000; /* Use a 1msec timeout */
+
+ while (timeout--) {
+ u32 reg32 = readl(®s->icii);
+
+ if (!(reg32 & HDA_ICII_BUSY))
+ return 0;
+ udelay(1);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int wait_for_response(struct hda_regs *regs, uint *response)
+{
+ int timeout = 1000;
+ u32 reg32;
+
+ /* Send the verb to the codec */
+ setbits_le32(®s->icii, HDA_ICII_BUSY | HDA_ICII_VALID);
+
+ /* Use a 1msec timeout */
+ while (timeout--) {
+ reg32 = readl(®s->icii);
+ if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+ HDA_ICII_VALID) {
+ if (response)
+ *response = readl(®s->resp);
+ return 0;
+ }
+ udelay(1);
+ }
+
+ return -ETIMEDOUT;
+}
+
+int hda_wait_for_valid(struct hda_regs *regs)
+{
+ return wait_for_response(regs, NULL);
+}
+
+static int set_bits(void *port, u32 mask, u32 val)
+{
+ u32 reg32;
+ int count;
+
+ /* Write (val & mask) to port */
+ clrsetbits_le32(port, mask, val);
+
+ /* Wait for readback of register to match what was just written to it */
+ count = 50;
+ do {
+ /* Wait 1ms based on BKDG wait time */
+ mdelay(1);
+ reg32 = readl(port) & mask;
+ } while (reg32 != val && --count);
+
+ /* Timeout occurred */
+ if (!count)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+int hda_codec_detect(struct hda_regs *regs)
+{
+ uint reg8;
+
+ /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+ if (set_bits(®s->gctl, 1, 1))
+ goto no_codec;
+
+ /* Write back the value once reset bit is set */
+ writew(readw(®s->gcap), ®s->gcap);
+
+ /* Read in Codec location */
+ reg8 = readb(®s->statests) & 0xf;
+ if (!reg8)
+ goto no_codec;
+
+ return reg8;
+
+no_codec:
+ /* Codec Not found - put HDA back in reset */
+ set_bits(®s->gctl, 1, 0);
+ log_debug("No codec\n");
+
+ return 0;
+}
+
+static int find_verb_data(struct udevice *dev, uint id, ofnode *nodep)
+{
+ ofnode parent = dev_read_subnode(dev, "codecs");
+ ofnode node;
+ u32 vendor_id, device_id;
+
+ ofnode_for_each_subnode(node, parent) {
+ if (ofnode_read_u32(node, "vendor-id", &vendor_id) ||
+ ofnode_read_u32(node, "device-id", &device_id)) {
+ log_debug("Cannot get IDs for '%s'\n",
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+ if (id != (vendor_id << 16 | device_id)) {
+ log_debug("Skip codec node '%s' for %08x\n",
+ ofnode_get_name(node), id);
+ continue;
+ }
+
+ log_debug("Found codec node '%s' for %08x\n",
+ ofnode_get_name(node), id);
+ *nodep = node;
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static int send_verbs(ofnode node, const char *prop_name, struct hda_regs *regs)
+{
+ int ret, verb_size, i;
+ const u32 *verb;
+
+ verb = ofnode_get_property(node, prop_name, &verb_size);
+ if (verb_size < 0) {
+ log_debug("No verb data\n");
+ return -EINVAL;
+ }
+ log_debug("verb_size: %d\n", verb_size);
+
+ for (i = 0; i < verb_size / sizeof(*verb); i++) {
+ ret = hda_wait_for_ready(regs);
+ if (ret) {
+ log_debug(" codec ready timeout\n");
+ return ret;
+ }
+
+ writel(fdt32_to_cpu(verb[i]), ®s->cmd);
+
+ ret = hda_wait_for_valid(regs);
+ if (ret) {
+ log_debug(" codec valid timeout\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int codec_init(struct udevice *dev, struct hda_regs *regs, uint addr)
+{
+ ofnode node;
+ uint id;
+ int ret;
+
+ log_debug("Initializing codec #%d\n", addr);
+ ret = hda_wait_for_ready(regs);
+ if (ret) {
+ log_debug(" codec not ready\n");
+ return ret;
+ }
+
+ /* Read the codec's vendor ID */
+ writel(addr << AZALIA_CODEC_SHIFT |
+ AZALIA_OPCODE_READ_PARAM << AZALIA_VERB_SHIFT |
+ AZALIA_PARAM_VENDOR_ID, ®s->cmd);
+ ret = hda_wait_for_valid(regs);
+ if (ret) {
+ log_debug(" codec not valid\n");
+ return ret;
+ }
+
+ id = readl(®s->resp);
+ log_debug("codec vid/did: %08x\n", id);
+ ret = find_verb_data(dev, id, &node);
+ if (ret) {
+ log_debug("No verb (err=%d)\n", ret);
+ return ret;
+ }
+ ret = send_verbs(node, "verbs", regs);
+ if (ret) {
+ log_debug("failed to send verbs (err=%d)\n", ret);
+ return ret;
+ }
+ log_debug("verb loaded\n");
+
+ return 0;
+}
+
+int hda_codecs_init(struct udevice *dev, struct hda_regs *regs, u32 codec_mask)
+{
+ int ret;
+ int i;
+
+ for (i = 3; i >= 0; i--) {
+ if (codec_mask & (1 << i)) {
+ ret = codec_init(dev, regs, i);
+ if (ret)
+ return ret;
+ }
+ }
+
+ ret = send_verbs(dev_ofnode(dev), "beep-verbs", regs);
+ if (ret) {
+ log_debug("failed to send beep verbs (err=%d)\n", ret);
+ return ret;
+ }
+ log_debug("beep verbs loaded\n");
+
+ return 0;
+}
+
+/**
+ * exec_verb() - Write a verb to the codec
+ *
+ * @regs: HDA registers
+ * @val: Command to write
+ * @response: Set to response from codec
+ * @return 0 if OK, -ve on error
+ */
+static int exec_verb(struct hda_regs *regs, uint val, uint *response)
+{
+ int ret;
+
+ ret = hda_wait_for_ready(regs);
+ if (ret)
+ return ret;
+
+ writel(val, ®s->cmd);
+
+ return wait_for_response(regs, response);
+}
+
+/**
+ * get_subnode_info() - Get subnode information
+ *
+ * @regs: HDA registers
+ * @nid: Parent node ID to check
+ * @num_sub_nodesp: Returns number of subnodes
+ * @start_sub_node_nidp: Returns start subnode number
+ * @return 0 if OK, -ve on error
+ */
+static int get_subnode_info(struct hda_regs *regs, uint nid,
+ uint *num_sub_nodesp, uint *start_sub_node_nidp)
+{
+ uint response;
+ int ret;
+
+ ret = exec_verb(regs, hda_verb(nid, HDA_VERB_GET_PARAMS,
+ GET_PARAMS_NODE_COUNT),
+ &response);
+ if (ret < 0) {
+ printf("Audio: Error reading sub-node info %d\n", nid);
+ return ret;
+ }
+
+ *num_sub_nodesp = (response & NUM_SUB_NODES_M) >> NUM_SUB_NODES_S;
+ *start_sub_node_nidp = (response & FIRST_SUB_NODE_M) >>
+ FIRST_SUB_NODE_S;
+
+ return 0;
+}
+
+/**
+ * find_beep_node_in_group() - Finds the beeping node
+ *
+ * Searches the audio group for a node that supports beeping
+ *
+ * @regs: HDA registers
+ * @group_nid: Group node ID to check
+ * @return 0 if OK, -ve on error
+ */
+static uint find_beep_node_in_group(struct hda_regs *regs, uint group_nid)
+{
+ uint node_count = 0;
+ uint current_nid = 0;
+ uint response;
+ uint end_nid;
+ int ret;
+
+ ret = get_subnode_info(regs, group_nid, &node_count, ¤t_nid);
+ if (ret < 0)
+ return 0;
+
+ end_nid = current_nid + node_count;
+ while (current_nid < end_nid) {
+ ret = exec_verb(regs,
+ hda_verb(current_nid, HDA_VERB_GET_PARAMS,
+ GET_PARAMS_AUDIO_WIDGET_CAPS),
+ &response);
+ if (ret < 0) {
+ printf("Audio: Error reading widget caps\n");
+ return 0;
+ }
+
+ if ((response & AUDIO_WIDGET_TYPE_M) >> AUDIO_WIDGET_TYPE_S ==
+ AUDIO_WIDGET_TYPE_BEEP)
+ return current_nid;
+
+ current_nid++;
+ }
+
+ return 0; /* no beep node found */
+}
+
+/**
+ * audio_group_has_beep_node() - Check if group has a beep node
+ *
+ * Checks if the given audio group contains a beep generator
+ * @regs: HDA registers
+ * @nid: Node ID to check
+ * @return 0 if OK, -ve on error
+ */
+static int audio_group_has_beep_node(struct hda_regs *regs, uint nid)
+{
+ uint response;
+ int ret;
+
+ ret = exec_verb(regs, hda_verb(nid, HDA_VERB_GET_PARAMS,
+ GET_PARAMS_AUDIO_GROUP_CAPS),
+ &response);
+ if (ret < 0) {
+ printf("Audio: Error reading audio group caps %d\n", nid);
+ return 0;
+ }
+
+ return !!(response & AUDIO_GROUP_CAPS_BEEP_GEN);
+}
+
+/**
+ * get_hda_beep_nid() - Finds the node ID of the beep node
+ *
+ * Finds the nid of the beep node if it exists. Starts at the root node, for
+ * each sub-node checks if the group contains a beep node. If the group
+ * contains a beep node, polls each node in the group until it is found.
+ *
+ * If the device has a intel,beep-nid property, the value of that is used
+ * instead.
+ *
+ * @dev: Sound device
+ * @return Node ID >0 if found, -ve error code otherwise
+ */
+static int get_hda_beep_nid(struct udevice *dev)
+{
+ struct hda_codec_priv *priv = dev_get_priv(dev);
+ uint current_nid = 0;
+ uint node_count = 0;
+ uint end_nid;
+ int ret;
+
+ /* If the field exists, use the beep nid set in the fdt */
+ ret = dev_read_u32(dev, "intel,beep-nid", ¤t_nid);
+ if (!ret)
+ return current_nid;
+
+ ret = get_subnode_info(priv->regs, HDA_ROOT_NODE, &node_count,
+ ¤t_nid);
+ if (ret < 0)
+ return ret;
+
+ end_nid = current_nid + node_count;
+ while (current_nid < end_nid) {
+ if (audio_group_has_beep_node(priv->regs, current_nid))
+ return find_beep_node_in_group(priv->regs,
+ current_nid);
+ current_nid++;
+ }
+ /* no beep node found */
+
+ return -ENOENT;
+}
+
+/**
+ * set_beep_divisor() - Sets the beep divisor to set the pitch
+ *
+ * @priv: Device's private data
+ * @divider: Divider value (0 to disable the beep)
+ * @return 0 if OK, -ve on error
+ */
+static int set_beep_divisor(struct hda_codec_priv *priv, uint divider)
+{
+ return exec_verb(priv->regs,
+ hda_verb(priv->beep_nid, HDA_VERB_SET_BEEP, divider),
+ NULL);
+}
+
+int hda_codec_init(struct udevice *dev)
+{
+ struct hda_codec_priv *priv = dev_get_priv(dev);
+ ulong base_addr;
+
+ base_addr = dm_pci_read_bar32(dev, 0);
+ log_debug("base = %08lx\n", base_addr);
+ if (!base_addr)
+ return -EINVAL;
+
+ priv->regs = (struct hda_regs *)base_addr;
+
+ return 0;
+}
+
+int hda_codec_finish_init(struct udevice *dev)
+{
+ struct hda_codec_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = get_hda_beep_nid(dev);
+ if (ret <= 0) {
+ log_warning("Could not find beep NID (err=%d)\n", ret);
+ return ret ? ret : -ENOENT;
+ }
+ priv->beep_nid = ret;
+
+ return 0;
+}
+
+int hda_codec_start_beep(struct udevice *dev, int frequency_hz)
+{
+ struct hda_codec_priv *priv = dev_get_priv(dev);
+ uint divider_val;
+
+ if (!priv->beep_nid) {
+ log_err("Failed to find a beep-capable node\n");
+ return -ENOENT;
+ }
+
+ if (!frequency_hz)
+ divider_val = 0; /* off */
+ else if (frequency_hz > BEEP_FREQ_BASE)
+ divider_val = 1;
+ else if (frequency_hz < BEEP_FREQ_BASE / 0xff)
+ divider_val = 0xff;
+ else
+ divider_val = 0xff & (BEEP_FREQ_BASE / frequency_hz);
+
+ return set_beep_divisor(priv, divider_val);
+}
+
+int hda_codec_stop_beep(struct udevice *dev)
+{
+ struct hda_codec_priv *priv = dev_get_priv(dev);
+
+ return set_beep_divisor(priv, 0);
+}
+
+static const struct sound_ops hda_codec_ops = {
+ .setup = hda_codec_finish_init,
+ .start_beep = hda_codec_start_beep,
+ .stop_beep = hda_codec_stop_beep,
+};
+
+U_BOOT_DRIVER(hda_codec) = {
+ .name = "hda_codec",
+ .id = UCLASS_SOUND,
+ .ops = &hda_codec_ops,
+ .priv_auto_alloc_size = sizeof(struct hda_codec_priv),
+ .probe = hda_codec_init,
+};
+
+static struct pci_device_id hda_supported[] = {
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA},
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_WILDCATPOINT_HDA) },
+
+ /*
+ * Note this driver is not necessarily generic, but it attempts to
+ * support any codec in the hd-audio class
+ */
+ { PCI_DEVICE_CLASS(PCI_CLASS_MULTIMEDIA_HD_AUDIO, 0xffffff) },
+};
+
+U_BOOT_PCI_DEVICE(hda_codec, hda_supported);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sound.h>
+#include <asm/i8254.h>
+
+int i8254_start_beep(struct udevice *dev, int frequency_hz)
+{
+ return i8254_enable_beep(frequency_hz);
+}
+
+int i8254_stop_beep(struct udevice *dev)
+{
+ i8254_disable_beep();
+
+ return 0;
+}
+
+static const struct sound_ops i8254_ops = {
+ .start_beep = i8254_start_beep,
+ .stop_beep = i8254_stop_beep,
+};
+
+static const struct udevice_id i8254_ids[] = {
+ { .compatible = "i8254,beeper" },
+ { }
+};
+
+U_BOOT_DRIVER(i8254_drv) = {
+ .name = "i8254_drv",
+ .id = UCLASS_SOUND,
+ .of_match = i8254_ids,
+ .ops = &i8254_ops,
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel HDA audio (Azalia) for ivybridge
+ *
+ * Originally from coreboot file bd82x6x/azalia.c
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.
+ * Copyright 2018 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_SOUND
+
+#include <common.h>
+#include <dm.h>
+#include <hda_codec.h>
+#include <pch.h>
+#include <sound.h>
+
+static int bd82x6x_azalia_probe(struct udevice *dev)
+{
+ struct pci_child_platdata *plat;
+ struct hda_codec_priv *priv;
+ struct udevice *pch;
+ u32 codec_mask;
+ int conf;
+ int ret;
+
+ /* Only init after relocation */
+ if (!(gd->flags & GD_FLG_RELOC))
+ return 0;
+
+ ret = hda_codec_init(dev);
+ if (ret) {
+ log_debug("Cannot set up HDA codec (err=%d)\n", ret);
+ return ret;
+ }
+ priv = dev_get_priv(dev);
+
+ ret = uclass_first_device_err(UCLASS_PCH, &pch);
+ log_debug("PCH %p %s\n", pch, pch->name);
+ if (ret)
+ return ret;
+
+ conf = pch_ioctl(pch, PCH_REQ_HDA_CONFIG, NULL, 0);
+ log_debug("conf = %x\n", conf);
+ if (conf >= 0) {
+ dm_pci_clrset_config32(dev, 0x120, 7 << 24 | 0xfe,
+ 1 << 24 | /* 2 << 24 for server */
+ conf);
+
+ dm_pci_clrset_config16(dev, 0x78, 0, 1 << 1);
+ } else {
+ log_debug("V1CTL disabled\n");
+ }
+ dm_pci_clrset_config32(dev, 0x114, 0xfe, 0);
+
+ /* Set VCi enable bit */
+ dm_pci_clrset_config32(dev, 0x120, 0, 1U << 31);
+
+ /* Enable HDMI codec */
+ dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 1);
+ dm_pci_clrset_config8(dev, 0x43, 0, 1 << 6);
+
+ /* Additional programming steps */
+ dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 13);
+ dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 10);
+ dm_pci_clrset_config32(dev, 0xd0, 1U << 31, 0);
+
+ /* Additional step on Panther Point */
+ plat = dev_get_parent_platdata(dev);
+ if (plat->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA)
+ dm_pci_clrset_config32(dev, 0xc4, 0, 1 << 17);
+
+ dm_pci_write_config8(dev, 0x3c, 0xa); /* unused? */
+
+ /* Audio Control: Select Azalia mode */
+ dm_pci_clrset_config8(dev, 0x40, 0, 1);
+ dm_pci_clrset_config8(dev, 0x4d, 1 << 7, 0); /* Docking not supported */
+ codec_mask = hda_codec_detect(priv->regs);
+ log_debug("codec_mask = %02x\n", codec_mask);
+
+ if (codec_mask) {
+ ret = hda_codecs_init(dev, priv->regs, codec_mask);
+ if (ret) {
+ log_err("Codec init failed (err=%d)\n", ret);
+ return ret;
+ }
+ }
+
+ /* Enable dynamic clock gating */
+ dm_pci_clrset_config8(dev, 0x43, 7, BIT(2) | BIT(0));
+
+ ret = hda_codec_finish_init(dev);
+ if (ret) {
+ log_debug("Cannot set up HDA codec (err=%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int bd82x6x_azalia_setup(struct udevice *dev)
+{
+ return 0;
+}
+
+int bd82x6x_azalia_start_beep(struct udevice *dev, int frequency_hz)
+{
+ return hda_codec_start_beep(dev, frequency_hz);
+}
+
+int bd82x6x_azalia_stop_beep(struct udevice *dev)
+{
+ return hda_codec_stop_beep(dev);
+}
+
+static const struct sound_ops bd82x6x_azalia_ops = {
+ .setup = bd82x6x_azalia_setup,
+ .start_beep = bd82x6x_azalia_start_beep,
+ .stop_beep = bd82x6x_azalia_stop_beep,
+};
+
+static const struct udevice_id bd82x6x_azalia_ids[] = {
+ { .compatible = "intel,hd-audio" },
+ { }
+};
+
+U_BOOT_DRIVER(bd82x6x_azalia_drv) = {
+ .name = "bd82x6x-hda",
+ .id = UCLASS_SOUND,
+ .of_match = bd82x6x_azalia_ids,
+ .probe = bd82x6x_azalia_probe,
+ .ops = &bd82x6x_azalia_ops,
+ .priv_auto_alloc_size = sizeof(struct hda_codec_priv),
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_SOUND
+
+#include <common.h>
+#include <audio_codec.h>
+#include <dm.h>
+#include <i2c.h>
+#include "rt5677.h"
+
+struct rt5677_priv {
+ struct udevice *dev;
+};
+
+/* RT5677 has 256 8-bit register addresses, and 16-bit register data */
+struct rt5677_init_reg {
+ u8 reg;
+ u16 val;
+};
+
+static struct rt5677_init_reg init_list[] = {
+ {RT5677_LOUT1, 0x0800},
+ {RT5677_SIDETONE_CTRL, 0x0000},
+ {RT5677_STO1_ADC_DIG_VOL, 0x3F3F},
+ {RT5677_DAC1_DIG_VOL, 0x9090},
+ {RT5677_STO2_ADC_MIXER, 0xA441},
+ {RT5677_STO1_ADC_MIXER, 0x5480},
+ {RT5677_STO1_DAC_MIXER, 0x8A8A},
+ {RT5677_PWR_DIG1, 0x9800}, /* Power up I2S1 */
+ {RT5677_PWR_ANLG1, 0xE9D5},
+ {RT5677_PWR_ANLG2, 0x2CC0},
+ {RT5677_PWR_DSP2, 0x0C00},
+ {RT5677_I2S2_SDP, 0x0000},
+ {RT5677_CLK_TREE_CTRL1, 0x1111},
+ {RT5677_PLL1_CTRL1, 0x0000},
+ {RT5677_PLL1_CTRL2, 0x0000},
+ {RT5677_DIG_MISC, 0x0029},
+ {RT5677_GEN_CTRL1, 0x00FF},
+ {RT5677_GPIO_CTRL2, 0x0020},
+ {RT5677_PWR_DIG2, 0x9024}, /* Power on ADC Stereo Filters */
+ {RT5677_PDM_OUT_CTRL, 0x0088}, /* Unmute PDM, set stereo1 DAC */
+ {RT5677_PDM_DATA_CTRL1, 0x0001}, /* Sysclk to PDM filter divider 2 */
+};
+
+/**
+ * rt5677_i2c_read() - Read a 16-bit register
+ *
+ * @priv: Private driver data
+ * @reg: Register number to read
+ * @returns data read or -ve on error
+ */
+static int rt5677_i2c_read(struct rt5677_priv *priv, uint reg)
+{
+ u8 buf[2];
+ int ret;
+
+ ret = dm_i2c_read(priv->dev, reg, buf, sizeof(u16));
+ if (ret)
+ return ret;
+ return buf[0] << 8 | buf[1];
+}
+
+/**
+ * rt5677_i2c_write() - Write a 16-bit register
+ *
+ * @priv: Private driver data
+ * @reg: Register number to read
+ * @data: Data to write
+ * @returns 0 if OK, -ve on error
+ */
+static int rt5677_i2c_write(struct rt5677_priv *priv, uint reg, uint data)
+{
+ u8 buf[2];
+
+ buf[0] = (data >> 8) & 0xff;
+ buf[1] = data & 0xff;
+
+ return dm_i2c_write(priv->dev, reg, buf, sizeof(u16));
+}
+
+/**
+ * rt5677_bic_or() - Set and clear bits of a codec register
+ *
+ * @priv: Private driver data
+ * @reg: Register number to update
+ * @bic: Mask of bits to clear
+ * @set: Mask of bits to set
+ * @returns 0 if OK, -ve on error
+ *
+ */
+static int rt5677_bic_or(struct rt5677_priv *priv, uint reg, uint bic,
+ uint set)
+{
+ uint old, new_value;
+ int ret;
+
+ old = rt5677_i2c_read(priv, reg);
+ if (old < 0)
+ return old;
+
+ new_value = (old & ~bic) | (set & bic);
+
+ if (old != new_value) {
+ ret = rt5677_i2c_write(priv, reg, new_value);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * rt5677_reg_init() - Initialise codec regs w/static/base values
+ *
+ * @priv: Private driver data
+ * @returns 0 if OK, -ve on error
+ */
+static int rt5677_reg_init(struct rt5677_priv *priv)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(init_list); i++) {
+ ret = rt5677_i2c_write(priv, init_list[i].reg, init_list[i].val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef DEBUG
+static void debug_dump_5677_regs(struct rt5677_priv *priv, int swap)
+{
+ uint i, reg_word;
+
+ /* Show all 16-bit codec regs */
+ for (i = 0; i < RT5677_REG_CNT; i++) {
+ if (i % 8 == 0)
+ log_debug("\nMX%02x: ", i);
+
+ rt5677_i2c_read(priv, (u8)i, ®_word);
+ if (swap)
+ log_debug("%04x ", swap_bytes16(reg_word));
+ else
+ log_debug("%04x ", reg_word);
+ }
+ log_debug("\n");
+
+ /* Show all 16-bit 'private' codec regs */
+ for (i = 0; i < RT5677_PR_REG_CNT; i++) {
+ if (i % 8 == 0)
+ log_debug("\nPR%02x: ", i);
+
+ rt5677_i2c_write(priv, RT5677_PRIV_INDEX, i);
+ rt5677_i2c_read(priv, RT5677_PRIV_DATA, ®_word);
+ if (swap)
+ log_debug("%04x ", swap_bytes16(reg_word));
+ else
+ log_debug("%04x ", reg_word);
+ }
+ log_debug("\n");
+}
+#endif /* DEBUG */
+
+static int rt5677_hw_params(struct rt5677_priv *priv, uint bits_per_sample)
+{
+ int ret;
+
+ switch (bits_per_sample) {
+ case 16:
+ ret = rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_DL_MASK,
+ 0);
+ if (ret) {
+ log_debug("Error updating I2S1 Interface Ctrl reg\n");
+ return 1;
+ }
+ break;
+ default:
+ log_err("Illegal bits per sample %d\n", bits_per_sample);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/**
+ * rt5677_set_fmt() - set rt5677 I2S format
+ *
+ * @priv: Private driver data
+ * @returns 0 if OK, -ve on error
+ */
+static int rt5677_set_fmt(struct rt5677_priv *priv)
+{
+ int ret = 0;
+
+ /*
+ * Set format here: Assumes I2S, NB_NF, CBS_CFS
+ *
+ * CBS_CFS (Codec Bit Slave/Codec Frame Slave)
+ */
+ ret = rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_MS_MASK,
+ RT5677_I2S_MS_S);
+
+ /* NB_NF (Normal Bit/Normal Frame) */
+ ret |= rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_BP_MASK,
+ RT5677_I2S_BP_NOR);
+
+ /* I2S mode */
+ ret |= rt5677_bic_or(priv, RT5677_I2S1_SDP, RT5677_I2S_DF_MASK,
+ RT5677_I2S_DF_I2S);
+
+ /* A44: I2S2 (going to speaker amp) is master */
+ ret |= rt5677_bic_or(priv, RT5677_I2S2_SDP, RT5677_I2S_MS_MASK,
+ RT5677_I2S_MS_M);
+
+ if (ret) {
+ log_err("Error updating I2S1 Interface Ctrl reg\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * rt5677_reset() - reset the audio codec
+ *
+ * @priv: Private driver data
+ * @returns 0 if OK, -ve on error
+ */
+static int rt5677_reset(struct rt5677_priv *priv)
+{
+ int ret;
+
+ /* Reset the codec registers to their defaults */
+ ret = rt5677_i2c_write(priv, RT5677_RESET, RT5677_SW_RESET);
+ if (ret) {
+ log_err("Error resetting codec\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * Initialise rt5677 codec device
+ *
+ * @priv: Private driver data
+ * @returns 0 if OK, -ve on error
+ */
+int rt5677_device_init(struct rt5677_priv *priv)
+{
+ int ret;
+
+ /* Read status reg */
+ ret = rt5677_i2c_read(priv, RT5677_RESET);
+ if (ret < 0)
+ return ret;
+ log_debug("reg 00h, Software Reset & Status = 0x%04x\n", ret);
+
+ /* Reset the codec/regs */
+ ret = rt5677_reset(priv);
+ if (ret)
+ return ret;
+
+ ret = rt5677_i2c_read(priv, RT5677_VENDOR_ID1);
+ if (ret < 0) {
+ log_err("Error reading vendor ID\n");
+ return 1;
+ }
+ log_debug("Hardware ID: %0xX\n", ret);
+
+ ret = rt5677_i2c_read(priv, RT5677_VENDOR_ID2);
+ if (ret < 0) {
+ log_err("Error reading vendor rev\n");
+ return 1;
+ }
+ log_debug("Hardware revision: %04x\n", ret);
+
+ return 0;
+}
+
+static int rt5677_set_params(struct udevice *dev, int interface, int rate,
+ int mclk_freq, int bits_per_sample,
+ uint channels)
+{
+ struct rt5677_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ /* Initialise codec regs w/static/base values, same as Linux driver */
+ ret = rt5677_reg_init(priv);
+ if (ret)
+ return ret;
+
+ ret = rt5677_hw_params(priv, bits_per_sample);
+ if (ret)
+ return ret;
+
+ ret = rt5677_set_fmt(priv);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int rt5677_probe(struct udevice *dev)
+{
+ struct rt5677_priv *priv = dev_get_priv(dev);
+
+ priv->dev = dev;
+
+ return rt5677_device_init(priv);
+}
+
+static const struct audio_codec_ops rt5677_ops = {
+ .set_params = rt5677_set_params,
+};
+
+static const struct udevice_id rt5677_ids[] = {
+ { .compatible = "realtek,rt5677" },
+ { }
+};
+
+U_BOOT_DRIVER(rt5677_drv) = {
+ .name = "rt5677",
+ .id = UCLASS_AUDIO_CODEC,
+ .of_match = rt5677_ids,
+ .ops = &rt5677_ops,
+ .probe = rt5677_probe,
+ .priv_auto_alloc_size = sizeof(struct rt5677_priv),
+};
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * rt5677.h -- RealTek ALC5677 ALSA SoC Audio driver
+ *
+ * Copyright 2013 Realtek Semiconductor Corp.
+ * Author: Oder Chiou <oder_chiou@realtek.com>
+ *
+ * Based on the file by the same name in Chromium OS dc
+ */
+
+#ifndef __DRIVERS_SOUND_RT5677_H__
+#define __DRIVERS_SOUND_RT5677_H__
+
+/*
+ * RT5677 Registers Definition
+ */
+
+/* Info */
+#define RT5677_RESET 0x00
+#define RT5677_VENDOR_ID 0xfd
+#define RT5677_VENDOR_ID1 0xfe
+#define RT5677_VENDOR_ID2 0xff
+
+#define RT5677_REG_CNT (RT5677_VENDOR_ID2 + 1)
+#define RT5677_PR_REG_CNT 255
+
+/* I/O - Output */
+#define RT5677_LOUT1 0x01
+/* I/O - Input */
+#define RT5677_IN1 0x03
+#define RT5677_MICBIAS 0x04
+/* I/O - SLIMBus */
+#define RT5677_SLIMBUS_PARAM 0x07
+#define RT5677_SLIMBUS_RX 0x08
+#define RT5677_SLIMBUS_CTRL 0x09
+/* I/O */
+#define RT5677_SIDETONE_CTRL 0x13
+/* I/O - ADC/DAC */
+#define RT5677_ANA_DAC1_2_3_SRC 0x15
+#define RT5677_IF_DSP_DAC3_4_MIXER 0x16
+#define RT5677_DAC4_DIG_VOL 0x17
+#define RT5677_DAC3_DIG_VOL 0x18
+#define RT5677_DAC1_DIG_VOL 0x19
+#define RT5677_DAC2_DIG_VOL 0x1a
+#define RT5677_IF_DSP_DAC2_MIXER 0x1b
+#define RT5677_STO1_ADC_DIG_VOL 0x1c
+#define RT5677_MONO_ADC_DIG_VOL 0x1d
+#define RT5677_STO1_2_ADC_BST 0x1e
+#define RT5677_STO2_ADC_DIG_VOL 0x1f
+/* Mixer - D-D */
+#define RT5677_ADC_BST_CTRL2 0x20
+#define RT5677_STO3_4_ADC_BST 0x21
+#define RT5677_STO3_ADC_DIG_VOL 0x22
+#define RT5677_STO4_ADC_DIG_VOL 0x23
+#define RT5677_STO4_ADC_MIXER 0x24
+#define RT5677_STO3_ADC_MIXER 0x25
+#define RT5677_STO2_ADC_MIXER 0x26
+#define RT5677_STO1_ADC_MIXER 0x27
+#define RT5677_MONO_ADC_MIXER 0x28
+#define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29
+#define RT5677_STO1_DAC_MIXER 0x2a
+#define RT5677_MONO_DAC_MIXER 0x2b
+#define RT5677_DD1_MIXER 0x2c
+#define RT5677_DD2_MIXER 0x2d
+#define RT5677_IF3_DATA 0x2f
+#define RT5677_IF4_DATA 0x30
+/* Mixer - PDM */
+#define RT5677_PDM_OUT_CTRL 0x31
+#define RT5677_PDM_DATA_CTRL1 0x32
+#define RT5677_PDM_DATA_CTRL2 0x33
+#define RT5677_PDM1_DATA_CTRL2 0x34
+#define RT5677_PDM1_DATA_CTRL3 0x35
+#define RT5677_PDM1_DATA_CTRL4 0x36
+#define RT5677_PDM2_DATA_CTRL2 0x37
+#define RT5677_PDM2_DATA_CTRL3 0x38
+#define RT5677_PDM2_DATA_CTRL4 0x39
+/* TDM */
+#define RT5677_TDM1_CTRL1 0x3b
+#define RT5677_TDM1_CTRL2 0x3c
+#define RT5677_TDM1_CTRL3 0x3d
+#define RT5677_TDM1_CTRL4 0x3e
+#define RT5677_TDM1_CTRL5 0x3f
+#define RT5677_TDM2_CTRL1 0x40
+#define RT5677_TDM2_CTRL2 0x41
+#define RT5677_TDM2_CTRL3 0x42
+#define RT5677_TDM2_CTRL4 0x43
+#define RT5677_TDM2_CTRL5 0x44
+/* I2C_MASTER_CTRL */
+#define RT5677_I2C_MASTER_CTRL1 0x47
+#define RT5677_I2C_MASTER_CTRL2 0x48
+#define RT5677_I2C_MASTER_CTRL3 0x49
+#define RT5677_I2C_MASTER_CTRL4 0x4a
+#define RT5677_I2C_MASTER_CTRL5 0x4b
+#define RT5677_I2C_MASTER_CTRL6 0x4c
+#define RT5677_I2C_MASTER_CTRL7 0x4d
+#define RT5677_I2C_MASTER_CTRL8 0x4e
+/* DMIC */
+#define RT5677_DMIC_CTRL1 0x50
+#define RT5677_DMIC_CTRL2 0x51
+/* Haptic Generator */
+#define RT5677_HAP_GENE_CTRL1 0x56
+#define RT5677_HAP_GENE_CTRL2 0x57
+#define RT5677_HAP_GENE_CTRL3 0x58
+#define RT5677_HAP_GENE_CTRL4 0x59
+#define RT5677_HAP_GENE_CTRL5 0x5a
+#define RT5677_HAP_GENE_CTRL6 0x5b
+#define RT5677_HAP_GENE_CTRL7 0x5c
+#define RT5677_HAP_GENE_CTRL8 0x5d
+#define RT5677_HAP_GENE_CTRL9 0x5e
+#define RT5677_HAP_GENE_CTRL10 0x5f
+/* Power */
+#define RT5677_PWR_DIG1 0x61
+#define RT5677_PWR_DIG2 0x62
+#define RT5677_PWR_ANLG1 0x63
+#define RT5677_PWR_ANLG2 0x64
+#define RT5677_PWR_DSP1 0x65
+#define RT5677_PWR_DSP_ST 0x66
+#define RT5677_PWR_DSP2 0x67
+#define RT5677_ADC_DAC_HPF_CTRL1 0x68
+/* Private Register Control */
+#define RT5677_PRIV_INDEX 0x6a
+#define RT5677_PRIV_DATA 0x6c
+/* Format - ADC/DAC */
+#define RT5677_I2S4_SDP 0x6f
+#define RT5677_I2S1_SDP 0x70
+#define RT5677_I2S2_SDP 0x71
+#define RT5677_I2S3_SDP 0x72
+#define RT5677_CLK_TREE_CTRL1 0x73
+#define RT5677_CLK_TREE_CTRL2 0x74
+#define RT5677_CLK_TREE_CTRL3 0x75
+/* Function - Analog */
+#define RT5677_PLL1_CTRL1 0x7a
+#define RT5677_PLL1_CTRL2 0x7b
+#define RT5677_PLL2_CTRL1 0x7c
+#define RT5677_PLL2_CTRL2 0x7d
+#define RT5677_GLB_CLK1 0x80
+#define RT5677_GLB_CLK2 0x81
+#define RT5677_ASRC_1 0x83
+#define RT5677_ASRC_2 0x84
+#define RT5677_ASRC_3 0x85
+#define RT5677_ASRC_4 0x86
+#define RT5677_ASRC_5 0x87
+#define RT5677_ASRC_6 0x88
+#define RT5677_ASRC_7 0x89
+#define RT5677_ASRC_8 0x8a
+#define RT5677_ASRC_9 0x8b
+#define RT5677_ASRC_10 0x8c
+#define RT5677_ASRC_11 0x8d
+#define RT5677_ASRC_12 0x8e
+#define RT5677_ASRC_13 0x8f
+#define RT5677_ASRC_14 0x90
+#define RT5677_ASRC_15 0x91
+#define RT5677_ASRC_16 0x92
+#define RT5677_ASRC_17 0x93
+#define RT5677_ASRC_18 0x94
+#define RT5677_ASRC_19 0x95
+#define RT5677_ASRC_20 0x97
+#define RT5677_ASRC_21 0x98
+#define RT5677_ASRC_22 0x99
+#define RT5677_ASRC_23 0x9a
+#define RT5677_VAD_CTRL1 0x9c
+#define RT5677_VAD_CTRL2 0x9d
+#define RT5677_VAD_CTRL3 0x9e
+#define RT5677_VAD_CTRL4 0x9f
+#define RT5677_VAD_CTRL5 0xa0
+/* Function - Digital */
+#define RT5677_DSP_INB_CTRL1 0xa3
+#define RT5677_DSP_INB_CTRL2 0xa4
+#define RT5677_DSP_IN_OUTB_CTRL 0xa5
+#define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6
+#define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7
+#define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8
+#define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9
+#define RT5677_ADC_EQ_CTRL1 0xae
+#define RT5677_ADC_EQ_CTRL2 0xaf
+#define RT5677_EQ_CTRL1 0xb0
+#define RT5677_EQ_CTRL2 0xb1
+#define RT5677_EQ_CTRL3 0xb2
+#define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3
+#define RT5677_JD_CTRL1 0xb5
+#define RT5677_JD_CTRL2 0xb6
+#define RT5677_JD_CTRL3 0xb8
+#define RT5677_IRQ_CTRL1 0xbd
+#define RT5677_IRQ_CTRL2 0xbe
+#define RT5677_GPIO_ST 0xbf
+#define RT5677_GPIO_CTRL1 0xc0
+#define RT5677_GPIO_CTRL2 0xc1
+#define RT5677_GPIO_CTRL3 0xc2
+#define RT5677_STO1_ADC_HI_FILTER1 0xc5
+#define RT5677_STO1_ADC_HI_FILTER2 0xc6
+#define RT5677_MONO_ADC_HI_FILTER1 0xc7
+#define RT5677_MONO_ADC_HI_FILTER2 0xc8
+#define RT5677_STO2_ADC_HI_FILTER1 0xc9
+#define RT5677_STO2_ADC_HI_FILTER2 0xca
+#define RT5677_STO3_ADC_HI_FILTER1 0xcb
+#define RT5677_STO3_ADC_HI_FILTER2 0xcc
+#define RT5677_STO4_ADC_HI_FILTER1 0xcd
+#define RT5677_STO4_ADC_HI_FILTER2 0xce
+#define RT5677_MB_DRC_CTRL1 0xd0
+#define RT5677_DRC1_CTRL1 0xd2
+#define RT5677_DRC1_CTRL2 0xd3
+#define RT5677_DRC1_CTRL3 0xd4
+#define RT5677_DRC1_CTRL4 0xd5
+#define RT5677_DRC1_CTRL5 0xd6
+#define RT5677_DRC1_CTRL6 0xd7
+#define RT5677_DRC2_CTRL1 0xd8
+#define RT5677_DRC2_CTRL2 0xd9
+#define RT5677_DRC2_CTRL3 0xda
+#define RT5677_DRC2_CTRL4 0xdb
+#define RT5677_DRC2_CTRL5 0xdc
+#define RT5677_DRC2_CTRL6 0xdd
+#define RT5677_DRC1_HL_CTRL1 0xde
+#define RT5677_DRC1_HL_CTRL2 0xdf
+#define RT5677_DRC2_HL_CTRL1 0xe0
+#define RT5677_DRC2_HL_CTRL2 0xe1
+#define RT5677_DSP_INB1_SRC_CTRL1 0xe3
+#define RT5677_DSP_INB1_SRC_CTRL2 0xe4
+#define RT5677_DSP_INB1_SRC_CTRL3 0xe5
+#define RT5677_DSP_INB1_SRC_CTRL4 0xe6
+#define RT5677_DSP_INB2_SRC_CTRL1 0xe7
+#define RT5677_DSP_INB2_SRC_CTRL2 0xe8
+#define RT5677_DSP_INB2_SRC_CTRL3 0xe9
+#define RT5677_DSP_INB2_SRC_CTRL4 0xea
+#define RT5677_DSP_INB3_SRC_CTRL1 0xeb
+#define RT5677_DSP_INB3_SRC_CTRL2 0xec
+#define RT5677_DSP_INB3_SRC_CTRL3 0xed
+#define RT5677_DSP_INB3_SRC_CTRL4 0xee
+#define RT5677_DSP_OUTB1_SRC_CTRL1 0xef
+#define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0
+#define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1
+#define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2
+#define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3
+#define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4
+#define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5
+#define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6
+
+/* Virtual DSP Mixer Control */
+#define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7
+#define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8
+#define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9
+
+/* General Control */
+#define RT5677_DIG_MISC 0xfa
+#define RT5677_GEN_CTRL1 0xfb
+#define RT5677_GEN_CTRL2 0xfc
+
+/* DSP Mode I2C Control*/
+#define RT5677_DSP_I2C_OP_CODE 0x00
+#define RT5677_DSP_I2C_ADDR_LSB 0x01
+#define RT5677_DSP_I2C_ADDR_MSB 0x02
+#define RT5677_DSP_I2C_DATA_LSB 0x03
+#define RT5677_DSP_I2C_DATA_MSB 0x04
+
+/* Index of Codec Private Register definition */
+#define RT5677_PR_DRC1_CTRL_1 0x01
+#define RT5677_PR_DRC1_CTRL_2 0x02
+#define RT5677_PR_DRC1_CTRL_3 0x03
+#define RT5677_PR_DRC1_CTRL_4 0x04
+#define RT5677_PR_DRC1_CTRL_5 0x05
+#define RT5677_PR_DRC1_CTRL_6 0x06
+#define RT5677_PR_DRC1_CTRL_7 0x07
+#define RT5677_PR_DRC2_CTRL_1 0x08
+#define RT5677_PR_DRC2_CTRL_2 0x09
+#define RT5677_PR_DRC2_CTRL_3 0x0a
+#define RT5677_PR_DRC2_CTRL_4 0x0b
+#define RT5677_PR_DRC2_CTRL_5 0x0c
+#define RT5677_PR_DRC2_CTRL_6 0x0d
+#define RT5677_PR_DRC2_CTRL_7 0x0e
+#define RT5677_BIAS_CUR1 0x10
+#define RT5677_BIAS_CUR2 0x12
+#define RT5677_BIAS_CUR3 0x13
+#define RT5677_BIAS_CUR4 0x14
+#define RT5677_BIAS_CUR5 0x15
+#define RT5677_VREF_LOUT_CTRL 0x17
+#define RT5677_DIG_VOL_CTRL1 0x1a
+#define RT5677_DIG_VOL_CTRL2 0x1b
+#define RT5677_ANA_ADC_GAIN_CTRL 0x1e
+#define RT5677_VAD_SRAM_TEST1 0x20
+#define RT5677_VAD_SRAM_TEST2 0x21
+#define RT5677_VAD_SRAM_TEST3 0x22
+#define RT5677_VAD_SRAM_TEST4 0x23
+#define RT5677_PAD_DRV_CTRL 0x26
+#define RT5677_DIG_IN_PIN_ST_CTRL1 0x29
+#define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a
+#define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b
+#define RT5677_PLL1_INT 0x38
+#define RT5677_PLL2_INT 0x39
+#define RT5677_TEST_CTRL1 0x3a
+#define RT5677_TEST_CTRL2 0x3b
+#define RT5677_TEST_CTRL3 0x3c
+#define RT5677_CHOP_DAC_ADC 0x3d
+#define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e
+#define RT5677_CROSS_OVER_FILTER1 0x90
+#define RT5677_CROSS_OVER_FILTER2 0x91
+#define RT5677_CROSS_OVER_FILTER3 0x92
+#define RT5677_CROSS_OVER_FILTER4 0x93
+#define RT5677_CROSS_OVER_FILTER5 0x94
+#define RT5677_CROSS_OVER_FILTER6 0x95
+#define RT5677_CROSS_OVER_FILTER7 0x96
+#define RT5677_CROSS_OVER_FILTER8 0x97
+#define RT5677_CROSS_OVER_FILTER9 0x98
+#define RT5677_CROSS_OVER_FILTER10 0x99
+
+/* global definition */
+#define RT5677_L_MUTE (0x1 << 15)
+#define RT5677_L_MUTE_SFT 15
+#define RT5677_VOL_L_MUTE (0x1 << 14)
+#define RT5677_VOL_L_SFT 14
+#define RT5677_R_MUTE (0x1 << 7)
+#define RT5677_R_MUTE_SFT 7
+#define RT5677_VOL_R_MUTE (0x1 << 6)
+#define RT5677_VOL_R_SFT 6
+#define RT5677_L_VOL_MASK (0x3f << 8)
+#define RT5677_L_VOL_SFT 8
+#define RT5677_R_VOL_MASK (0x3f)
+#define RT5677_R_VOL_SFT 0
+
+/* LOUT1 Control (0x01) */
+#define RT5677_LOUT1_L_MUTE (0x1 << 15)
+#define RT5677_LOUT1_L_MUTE_SFT (15)
+#define RT5677_LOUT1_L_DF (0x1 << 14)
+#define RT5677_LOUT1_L_DF_SFT (14)
+#define RT5677_LOUT2_L_MUTE (0x1 << 13)
+#define RT5677_LOUT2_L_MUTE_SFT (13)
+#define RT5677_LOUT2_L_DF (0x1 << 12)
+#define RT5677_LOUT2_L_DF_SFT (12)
+#define RT5677_LOUT3_L_MUTE (0x1 << 11)
+#define RT5677_LOUT3_L_MUTE_SFT (11)
+#define RT5677_LOUT3_L_DF (0x1 << 10)
+#define RT5677_LOUT3_L_DF_SFT (10)
+#define RT5677_LOUT1_ENH_DRV (0x1 << 9)
+#define RT5677_LOUT1_ENH_DRV_SFT (9)
+#define RT5677_LOUT2_ENH_DRV (0x1 << 8)
+#define RT5677_LOUT2_ENH_DRV_SFT (8)
+#define RT5677_LOUT3_ENH_DRV (0x1 << 7)
+#define RT5677_LOUT3_ENH_DRV_SFT (7)
+
+/* IN1 Control (0x03) */
+#define RT5677_BST_MASK1 (0xf << 12)
+#define RT5677_BST_SFT1 12
+#define RT5677_BST_MASK2 (0xf << 8)
+#define RT5677_BST_SFT2 8
+#define RT5677_IN_DF1 (0x1 << 7)
+#define RT5677_IN_DF1_SFT 7
+#define RT5677_IN_DF2 (0x1 << 6)
+#define RT5677_IN_DF2_SFT 6
+
+/* Micbias Control (0x04) */
+#define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
+#define RT5677_MICBIAS1_OUTVOLT_SFT (15)
+#define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)
+#define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
+#define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
+#define RT5677_MICBIAS1_CTRL_VDD_SFT (14)
+#define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)
+#define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
+#define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
+#define RT5677_MICBIAS1_OVCD_SHIFT (11)
+#define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)
+#define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
+#define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
+#define RT5677_MICBIAS1_OVTH_SFT 9
+#define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)
+#define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
+#define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)
+
+/* SLIMbus Parameter (0x07) */
+
+/* SLIMbus Rx (0x08) */
+#define RT5677_SLB_ADC4_MASK (0x3 << 6)
+#define RT5677_SLB_ADC4_SFT 6
+#define RT5677_SLB_ADC3_MASK (0x3 << 4)
+#define RT5677_SLB_ADC3_SFT 4
+#define RT5677_SLB_ADC2_MASK (0x3 << 2)
+#define RT5677_SLB_ADC2_SFT 2
+#define RT5677_SLB_ADC1_MASK (0x3 << 0)
+#define RT5677_SLB_ADC1_SFT 0
+
+/* SLIMBus control (0x09) */
+
+/* Sidetone Control (0x13) */
+#define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
+#define RT5677_ST_HPF_SEL_SFT 13
+#define RT5677_ST_HPF_PATH (0x1 << 12)
+#define RT5677_ST_HPF_PATH_SFT 12
+#define RT5677_ST_SEL_MASK (0x7 << 9)
+#define RT5677_ST_SEL_SFT 9
+#define RT5677_ST_EN (0x1 << 6)
+#define RT5677_ST_EN_SFT 6
+
+/* Analog DAC1/2/3 Source Control (0x15) */
+#define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
+#define RT5677_ANA_DAC3_SRC_SEL_SFT 4
+#define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
+#define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0
+
+/* IF/DSP to DAC3/4 Mixer Control (0x16) */
+#define RT5677_M_DAC4_L_VOL (0x1 << 15)
+#define RT5677_M_DAC4_L_VOL_SFT 15
+#define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
+#define RT5677_SEL_DAC4_L_SRC_SFT 12
+#define RT5677_M_DAC4_R_VOL (0x1 << 11)
+#define RT5677_M_DAC4_R_VOL_SFT 11
+#define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
+#define RT5677_SEL_DAC4_R_SRC_SFT 8
+#define RT5677_M_DAC3_L_VOL (0x1 << 7)
+#define RT5677_M_DAC3_L_VOL_SFT 7
+#define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
+#define RT5677_SEL_DAC3_L_SRC_SFT 4
+#define RT5677_M_DAC3_R_VOL (0x1 << 3)
+#define RT5677_M_DAC3_R_VOL_SFT 3
+#define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
+#define RT5677_SEL_DAC3_R_SRC_SFT 0
+
+/* DAC4 Digital Volume (0x17) */
+#define RT5677_DAC4_L_VOL_MASK (0xff << 8)
+#define RT5677_DAC4_L_VOL_SFT 8
+#define RT5677_DAC4_R_VOL_MASK (0xff)
+#define RT5677_DAC4_R_VOL_SFT 0
+
+/* DAC3 Digital Volume (0x18) */
+#define RT5677_DAC3_L_VOL_MASK (0xff << 8)
+#define RT5677_DAC3_L_VOL_SFT 8
+#define RT5677_DAC3_R_VOL_MASK (0xff)
+#define RT5677_DAC3_R_VOL_SFT 0
+
+/* DAC3 Digital Volume (0x19) */
+#define RT5677_DAC1_L_VOL_MASK (0xff << 8)
+#define RT5677_DAC1_L_VOL_SFT 8
+#define RT5677_DAC1_R_VOL_MASK (0xff)
+#define RT5677_DAC1_R_VOL_SFT 0
+
+/* DAC2 Digital Volume (0x1a) */
+#define RT5677_DAC2_L_VOL_MASK (0xff << 8)
+#define RT5677_DAC2_L_VOL_SFT 8
+#define RT5677_DAC2_R_VOL_MASK (0xff)
+#define RT5677_DAC2_R_VOL_SFT 0
+
+/* IF/DSP to DAC2 Mixer Control (0x1b) */
+#define RT5677_M_DAC2_L_VOL (0x1 << 7)
+#define RT5677_M_DAC2_L_VOL_SFT 7
+#define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
+#define RT5677_SEL_DAC2_L_SRC_SFT 4
+#define RT5677_M_DAC2_R_VOL (0x1 << 3)
+#define RT5677_M_DAC2_R_VOL_SFT 3
+#define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
+#define RT5677_SEL_DAC2_R_SRC_SFT 0
+
+/* Stereo1 ADC Digital Volume Control (0x1c) */
+#define RT5677_STO1_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5677_STO1_ADC_L_VOL_SFT 8
+#define RT5677_STO1_ADC_R_VOL_MASK (0x7f)
+#define RT5677_STO1_ADC_R_VOL_SFT 0
+
+/* Mono ADC Digital Volume Control (0x1d) */
+#define RT5677_MONO_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5677_MONO_ADC_L_VOL_SFT 8
+#define RT5677_MONO_ADC_R_VOL_MASK (0x7f)
+#define RT5677_MONO_ADC_R_VOL_SFT 0
+
+/* Stereo 1/2 ADC Boost Gain Control (0x1e) */
+#define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
+#define RT5677_STO1_ADC_L_BST_SFT 14
+#define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
+#define RT5677_STO1_ADC_R_BST_SFT 12
+#define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
+#define RT5677_STO1_ADC_COMP_SFT 10
+#define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
+#define RT5677_STO2_ADC_L_BST_SFT 8
+#define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
+#define RT5677_STO2_ADC_R_BST_SFT 6
+#define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
+#define RT5677_STO2_ADC_COMP_SFT 4
+
+/* Stereo2 ADC Digital Volume Control (0x1f) */
+#define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5677_STO2_ADC_L_VOL_SFT 8
+#define RT5677_STO2_ADC_R_VOL_MASK (0x7f)
+#define RT5677_STO2_ADC_R_VOL_SFT 0
+
+/* ADC Boost Gain Control 2 (0x20) */
+#define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
+#define RT5677_MONO_ADC_L_BST_SFT 14
+#define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
+#define RT5677_MONO_ADC_R_BST_SFT 12
+#define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
+#define RT5677_MONO_ADC_COMP_SFT 10
+
+/* Stereo 3/4 ADC Boost Gain Control (0x21) */
+#define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
+#define RT5677_STO3_ADC_L_BST_SFT 14
+#define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
+#define RT5677_STO3_ADC_R_BST_SFT 12
+#define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
+#define RT5677_STO3_ADC_COMP_SFT 10
+#define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
+#define RT5677_STO4_ADC_L_BST_SFT 8
+#define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
+#define RT5677_STO4_ADC_R_BST_SFT 6
+#define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
+#define RT5677_STO4_ADC_COMP_SFT 4
+
+/* Stereo3 ADC Digital Volume Control (0x22) */
+#define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5677_STO3_ADC_L_VOL_SFT 8
+#define RT5677_STO3_ADC_R_VOL_MASK (0x7f)
+#define RT5677_STO3_ADC_R_VOL_SFT 0
+
+/* Stereo4 ADC Digital Volume Control (0x23) */
+#define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
+#define RT5677_STO4_ADC_L_VOL_SFT 8
+#define RT5677_STO4_ADC_R_VOL_MASK (0x7f)
+#define RT5677_STO4_ADC_R_VOL_SFT 0
+
+/* Stereo4 ADC Mixer control (0x24) */
+#define RT5677_M_STO4_ADC_L2 (0x1 << 15)
+#define RT5677_M_STO4_ADC_L2_SFT 15
+#define RT5677_M_STO4_ADC_L1 (0x1 << 14)
+#define RT5677_M_STO4_ADC_L1_SFT 14
+#define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
+#define RT5677_SEL_STO4_ADC1_SFT 12
+#define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
+#define RT5677_SEL_STO4_ADC2_SFT 10
+#define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
+#define RT5677_SEL_STO4_DMIC_SFT 8
+#define RT5677_M_STO4_ADC_R1 (0x1 << 7)
+#define RT5677_M_STO4_ADC_R1_SFT 7
+#define RT5677_M_STO4_ADC_R2 (0x1 << 6)
+#define RT5677_M_STO4_ADC_R2_SFT 6
+
+/* Stereo3 ADC Mixer control (0x25) */
+#define RT5677_M_STO3_ADC_L2 (0x1 << 15)
+#define RT5677_M_STO3_ADC_L2_SFT 15
+#define RT5677_M_STO3_ADC_L1 (0x1 << 14)
+#define RT5677_M_STO3_ADC_L1_SFT 14
+#define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
+#define RT5677_SEL_STO3_ADC1_SFT 12
+#define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
+#define RT5677_SEL_STO3_ADC2_SFT 10
+#define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
+#define RT5677_SEL_STO3_DMIC_SFT 8
+#define RT5677_M_STO3_ADC_R1 (0x1 << 7)
+#define RT5677_M_STO3_ADC_R1_SFT 7
+#define RT5677_M_STO3_ADC_R2 (0x1 << 6)
+#define RT5677_M_STO3_ADC_R2_SFT 6
+
+/* Stereo2 ADC Mixer Control (0x26) */
+#define RT5677_M_STO2_ADC_L2 (0x1 << 15)
+#define RT5677_M_STO2_ADC_L2_SFT 15
+#define RT5677_M_STO2_ADC_L1 (0x1 << 14)
+#define RT5677_M_STO2_ADC_L1_SFT 14
+#define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
+#define RT5677_SEL_STO2_ADC1_SFT 12
+#define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
+#define RT5677_SEL_STO2_ADC2_SFT 10
+#define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
+#define RT5677_SEL_STO2_DMIC_SFT 8
+#define RT5677_M_STO2_ADC_R1 (0x1 << 7)
+#define RT5677_M_STO2_ADC_R1_SFT 7
+#define RT5677_M_STO2_ADC_R2 (0x1 << 6)
+#define RT5677_M_STO2_ADC_R2_SFT 6
+#define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
+#define RT5677_SEL_STO2_LR_MIX_SFT 0
+#define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)
+#define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
+
+/* Stereo1 ADC Mixer control (0x27) */
+#define RT5677_M_STO1_ADC_L2 (0x1 << 15)
+#define RT5677_M_STO1_ADC_L2_SFT 15
+#define RT5677_M_STO1_ADC_L1 (0x1 << 14)
+#define RT5677_M_STO1_ADC_L1_SFT 14
+#define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
+#define RT5677_SEL_STO1_ADC1_SFT 12
+#define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
+#define RT5677_SEL_STO1_ADC2_SFT 10
+#define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
+#define RT5677_SEL_STO1_DMIC_SFT 8
+#define RT5677_M_STO1_ADC_R1 (0x1 << 7)
+#define RT5677_M_STO1_ADC_R1_SFT 7
+#define RT5677_M_STO1_ADC_R2 (0x1 << 6)
+#define RT5677_M_STO1_ADC_R2_SFT 6
+
+/* Mono ADC Mixer control (0x28) */
+#define RT5677_M_MONO_ADC_L2 (0x1 << 15)
+#define RT5677_M_MONO_ADC_L2_SFT 15
+#define RT5677_M_MONO_ADC_L1 (0x1 << 14)
+#define RT5677_M_MONO_ADC_L1_SFT 14
+#define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
+#define RT5677_SEL_MONO_ADC_L1_SFT 12
+#define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
+#define RT5677_SEL_MONO_ADC_L2_SFT 10
+#define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
+#define RT5677_SEL_MONO_DMIC_L_SFT 8
+#define RT5677_M_MONO_ADC_R1 (0x1 << 7)
+#define RT5677_M_MONO_ADC_R1_SFT 7
+#define RT5677_M_MONO_ADC_R2 (0x1 << 6)
+#define RT5677_M_MONO_ADC_R2_SFT 6
+#define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
+#define RT5677_SEL_MONO_ADC_R1_SFT 4
+#define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
+#define RT5677_SEL_MONO_ADC_R2_SFT 2
+#define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
+#define RT5677_SEL_MONO_DMIC_R_SFT 0
+
+/* ADC/IF/DSP to DAC1 Mixer control (0x29) */
+#define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
+#define RT5677_M_ADDA_MIXER1_L_SFT 15
+#define RT5677_M_DAC1_L (0x1 << 14)
+#define RT5677_M_DAC1_L_SFT 14
+#define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
+#define RT5677_DAC1_L_SEL_SFT 8
+#define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
+#define RT5677_M_ADDA_MIXER1_R_SFT 7
+#define RT5677_M_DAC1_R (0x1 << 6)
+#define RT5677_M_DAC1_R_SFT 6
+#define RT5677_ADDA1_SEL_MASK (0x3 << 0)
+#define RT5677_ADDA1_SEL_SFT 0
+
+/* Stereo1 DAC Mixer L/R Control (0x2a) */
+#define RT5677_M_ST_DAC1_L (0x1 << 15)
+#define RT5677_M_ST_DAC1_L_SFT 15
+#define RT5677_M_DAC1_L_STO_L (0x1 << 13)
+#define RT5677_M_DAC1_L_STO_L_SFT 13
+#define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
+#define RT5677_DAC1_L_STO_L_VOL_SFT 12
+#define RT5677_M_DAC2_L_STO_L (0x1 << 11)
+#define RT5677_M_DAC2_L_STO_L_SFT 11
+#define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
+#define RT5677_DAC2_L_STO_L_VOL_SFT 10
+#define RT5677_M_DAC1_R_STO_L (0x1 << 9)
+#define RT5677_M_DAC1_R_STO_L_SFT 9
+#define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
+#define RT5677_DAC1_R_STO_L_VOL_SFT 8
+#define RT5677_M_ST_DAC1_R (0x1 << 7)
+#define RT5677_M_ST_DAC1_R_SFT 7
+#define RT5677_M_DAC1_R_STO_R (0x1 << 5)
+#define RT5677_M_DAC1_R_STO_R_SFT 5
+#define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
+#define RT5677_DAC1_R_STO_R_VOL_SFT 4
+#define RT5677_M_DAC2_R_STO_R (0x1 << 3)
+#define RT5677_M_DAC2_R_STO_R_SFT 3
+#define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
+#define RT5677_DAC2_R_STO_R_VOL_SFT 2
+#define RT5677_M_DAC1_L_STO_R (0x1 << 1)
+#define RT5677_M_DAC1_L_STO_R_SFT 1
+#define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
+#define RT5677_DAC1_L_STO_R_VOL_SFT 0
+
+/* Mono DAC Mixer L/R Control (0x2b) */
+#define RT5677_M_ST_DAC2_L (0x1 << 15)
+#define RT5677_M_ST_DAC2_L_SFT 15
+#define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
+#define RT5677_M_DAC2_L_MONO_L_SFT 13
+#define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
+#define RT5677_DAC2_L_MONO_L_VOL_SFT 12
+#define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
+#define RT5677_M_DAC2_R_MONO_L_SFT 11
+#define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
+#define RT5677_DAC2_R_MONO_L_VOL_SFT 10
+#define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
+#define RT5677_M_DAC1_L_MONO_L_SFT 9
+#define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
+#define RT5677_DAC1_L_MONO_L_VOL_SFT 8
+#define RT5677_M_ST_DAC2_R (0x1 << 7)
+#define RT5677_M_ST_DAC2_R_SFT 7
+#define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
+#define RT5677_M_DAC2_R_MONO_R_SFT 5
+#define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
+#define RT5677_DAC2_R_MONO_R_VOL_SFT 4
+#define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
+#define RT5677_M_DAC1_R_MONO_R_SFT 3
+#define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
+#define RT5677_DAC1_R_MONO_R_VOL_SFT 2
+#define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
+#define RT5677_M_DAC2_L_MONO_R_SFT 1
+#define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
+#define RT5677_DAC2_L_MONO_R_VOL_SFT 0
+
+/* DD Mixer 1 Control (0x2c) */
+#define RT5677_M_STO_L_DD1_L (0x1 << 15)
+#define RT5677_M_STO_L_DD1_L_SFT 15
+#define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
+#define RT5677_STO_L_DD1_L_VOL_SFT 14
+#define RT5677_M_MONO_L_DD1_L (0x1 << 13)
+#define RT5677_M_MONO_L_DD1_L_SFT 13
+#define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
+#define RT5677_MONO_L_DD1_L_VOL_SFT 12
+#define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
+#define RT5677_M_DAC3_L_DD1_L_SFT 11
+#define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
+#define RT5677_DAC3_L_DD1_L_VOL_SFT 10
+#define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
+#define RT5677_M_DAC3_R_DD1_L_SFT 9
+#define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
+#define RT5677_DAC3_R_DD1_L_VOL_SFT 8
+#define RT5677_M_STO_R_DD1_R (0x1 << 7)
+#define RT5677_M_STO_R_DD1_R_SFT 7
+#define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
+#define RT5677_STO_R_DD1_R_VOL_SFT 6
+#define RT5677_M_MONO_R_DD1_R (0x1 << 5)
+#define RT5677_M_MONO_R_DD1_R_SFT 5
+#define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
+#define RT5677_MONO_R_DD1_R_VOL_SFT 4
+#define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
+#define RT5677_M_DAC3_R_DD1_R_SFT 3
+#define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
+#define RT5677_DAC3_R_DD1_R_VOL_SFT 2
+#define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
+#define RT5677_M_DAC3_L_DD1_R_SFT 1
+#define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
+#define RT5677_DAC3_L_DD1_R_VOL_SFT 0
+
+/* DD Mixer 2 Control (0x2d) */
+#define RT5677_M_STO_L_DD2_L (0x1 << 15)
+#define RT5677_M_STO_L_DD2_L_SFT 15
+#define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
+#define RT5677_STO_L_DD2_L_VOL_SFT 14
+#define RT5677_M_MONO_L_DD2_L (0x1 << 13)
+#define RT5677_M_MONO_L_DD2_L_SFT 13
+#define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
+#define RT5677_MONO_L_DD2_L_VOL_SFT 12
+#define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
+#define RT5677_M_DAC4_L_DD2_L_SFT 11
+#define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
+#define RT5677_DAC4_L_DD2_L_VOL_SFT 10
+#define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
+#define RT5677_M_DAC4_R_DD2_L_SFT 9
+#define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
+#define RT5677_DAC4_R_DD2_L_VOL_SFT 8
+#define RT5677_M_STO_R_DD2_R (0x1 << 7)
+#define RT5677_M_STO_R_DD2_R_SFT 7
+#define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
+#define RT5677_STO_R_DD2_R_VOL_SFT 6
+#define RT5677_M_MONO_R_DD2_R (0x1 << 5)
+#define RT5677_M_MONO_R_DD2_R_SFT 5
+#define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
+#define RT5677_MONO_R_DD2_R_VOL_SFT 4
+#define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
+#define RT5677_M_DAC4_R_DD2_R_SFT 3
+#define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
+#define RT5677_DAC4_R_DD2_R_VOL_SFT 2
+#define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
+#define RT5677_M_DAC4_L_DD2_R_SFT 1
+#define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
+#define RT5677_DAC4_L_DD2_R_VOL_SFT 0
+
+/* IF3 data control (0x2f) */
+#define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
+#define RT5677_IF3_DAC_SEL_SFT 6
+#define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
+#define RT5677_IF3_ADC_SEL_SFT 4
+#define RT5677_IF3_ADC_IN_MASK (0xf << 0)
+#define RT5677_IF3_ADC_IN_SFT 0
+
+/* IF4 data control (0x30) */
+#define RT5677_IF4_ADC_IN_MASK (0xf << 4)
+#define RT5677_IF4_ADC_IN_SFT 4
+#define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
+#define RT5677_IF4_DAC_SEL_SFT 2
+#define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
+#define RT5677_IF4_ADC_SEL_SFT 0
+
+/* PDM Output Control (0x31) */
+#define RT5677_M_PDM1_L (0x1 << 15)
+#define RT5677_M_PDM1_L_SFT 15
+#define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
+#define RT5677_SEL_PDM1_L_SFT 12
+#define RT5677_M_PDM1_R (0x1 << 11)
+#define RT5677_M_PDM1_R_SFT 11
+#define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
+#define RT5677_SEL_PDM1_R_SFT 8
+#define RT5677_M_PDM2_L (0x1 << 7)
+#define RT5677_M_PDM2_L_SFT 7
+#define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
+#define RT5677_SEL_PDM2_L_SFT 4
+#define RT5677_M_PDM2_R (0x1 << 3)
+#define RT5677_M_PDM2_R_SFT 3
+#define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
+#define RT5677_SEL_PDM2_R_SFT 0
+
+/* PDM I2C / Data Control 1 (0x32) */
+#define RT5677_PDM2_PW_DOWN (0x1 << 7)
+#define RT5677_PDM1_PW_DOWN (0x1 << 6)
+#define RT5677_PDM2_BUSY (0x1 << 5)
+#define RT5677_PDM1_BUSY (0x1 << 4)
+#define RT5677_PDM_PATTERN (0x1 << 3)
+#define RT5677_PDM_GAIN (0x1 << 2)
+#define RT5677_PDM_DIV_MASK (0x3 << 0)
+
+/* PDM I2C / Data Control 2 (0x33) */
+#define RT5677_PDM1_I2C_ID (0xf << 12)
+#define RT5677_PDM1_EXE (0x1 << 11)
+#define RT5677_PDM1_I2C_CMD (0x1 << 10)
+#define RT5677_PDM1_I2C_EXE (0x1 << 9)
+#define RT5677_PDM1_I2C_BUSY (0x1 << 8)
+#define RT5677_PDM2_I2C_ID (0xf << 4)
+#define RT5677_PDM2_EXE (0x1 << 3)
+#define RT5677_PDM2_I2C_CMD (0x1 << 2)
+#define RT5677_PDM2_I2C_EXE (0x1 << 1)
+#define RT5677_PDM2_I2C_BUSY (0x1 << 0)
+
+/* MX3C TDM1 control 1 (0x3c) */
+#define RT5677_IF1_ADC4_MASK (0x3 << 10)
+#define RT5677_IF1_ADC4_SFT 10
+#define RT5677_IF1_ADC3_MASK (0x3 << 8)
+#define RT5677_IF1_ADC3_SFT 8
+#define RT5677_IF1_ADC2_MASK (0x3 << 6)
+#define RT5677_IF1_ADC2_SFT 6
+#define RT5677_IF1_ADC1_MASK (0x3 << 4)
+#define RT5677_IF1_ADC1_SFT 4
+
+/* MX41 TDM2 control 1 (0x41) */
+#define RT5677_IF2_ADC4_MASK (0x3 << 10)
+#define RT5677_IF2_ADC4_SFT 10
+#define RT5677_IF2_ADC3_MASK (0x3 << 8)
+#define RT5677_IF2_ADC3_SFT 8
+#define RT5677_IF2_ADC2_MASK (0x3 << 6)
+#define RT5677_IF2_ADC2_SFT 6
+#define RT5677_IF2_ADC1_MASK (0x3 << 4)
+#define RT5677_IF2_ADC1_SFT 4
+
+/* Digital Microphone Control 1 (0x50) */
+#define RT5677_DMIC_1_EN_MASK (0x1 << 15)
+#define RT5677_DMIC_1_EN_SFT 15
+#define RT5677_DMIC_1_DIS (0x0 << 15)
+#define RT5677_DMIC_1_EN (0x1 << 15)
+#define RT5677_DMIC_2_EN_MASK (0x1 << 14)
+#define RT5677_DMIC_2_EN_SFT 14
+#define RT5677_DMIC_2_DIS (0x0 << 14)
+#define RT5677_DMIC_2_EN (0x1 << 14)
+#define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
+#define RT5677_DMIC_L_STO1_LH_SFT 13
+#define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)
+#define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
+#define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
+#define RT5677_DMIC_R_STO1_LH_SFT 12
+#define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
+#define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
+#define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
+#define RT5677_DMIC_L_STO3_LH_SFT 11
+#define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)
+#define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
+#define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
+#define RT5677_DMIC_R_STO3_LH_SFT 10
+#define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)
+#define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
+#define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
+#define RT5677_DMIC_L_STO2_LH_SFT 9
+#define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)
+#define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
+#define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
+#define RT5677_DMIC_R_STO2_LH_SFT 8
+#define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
+#define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
+#define RT5677_DMIC_CLK_MASK (0x7 << 5)
+#define RT5677_DMIC_CLK_SFT 5
+#define RT5677_DMIC_3_EN_MASK (0x1 << 4)
+#define RT5677_DMIC_3_EN_SFT 4
+#define RT5677_DMIC_3_DIS (0x0 << 4)
+#define RT5677_DMIC_3_EN (0x1 << 4)
+#define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
+#define RT5677_DMIC_R_MONO_LH_SFT 2
+#define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)
+#define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
+#define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
+#define RT5677_DMIC_L_STO4_LH_SFT 1
+#define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)
+#define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
+#define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
+#define RT5677_DMIC_R_STO4_LH_SFT 0
+#define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)
+#define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
+
+/* Digital Microphone Control 2 (0x51) */
+#define RT5677_DMIC_4_EN_MASK (0x1 << 15)
+#define RT5677_DMIC_4_EN_SFT 15
+#define RT5677_DMIC_4_DIS (0x0 << 15)
+#define RT5677_DMIC_4_EN (0x1 << 15)
+#define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
+#define RT5677_DMIC_4L_LH_SFT 7
+#define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
+#define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
+#define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
+#define RT5677_DMIC_4R_LH_SFT 6
+#define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)
+#define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
+#define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
+#define RT5677_DMIC_3L_LH_SFT 5
+#define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)
+#define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
+#define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
+#define RT5677_DMIC_3R_LH_SFT 4
+#define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)
+#define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
+#define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
+#define RT5677_DMIC_2L_LH_SFT 3
+#define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
+#define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
+#define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
+#define RT5677_DMIC_2R_LH_SFT 2
+#define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)
+#define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
+#define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
+#define RT5677_DMIC_1L_LH_SFT 1
+#define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)
+#define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
+#define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
+#define RT5677_DMIC_1R_LH_SFT 0
+#define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)
+#define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
+
+/* Power Management for Digital 1 (0x61) */
+#define RT5677_PWR_I2S1 (0x1 << 15)
+#define RT5677_PWR_I2S1_BIT 15
+#define RT5677_PWR_I2S2 (0x1 << 14)
+#define RT5677_PWR_I2S2_BIT 14
+#define RT5677_PWR_I2S3 (0x1 << 13)
+#define RT5677_PWR_I2S3_BIT 13
+#define RT5677_PWR_DAC1 (0x1 << 12)
+#define RT5677_PWR_DAC1_BIT 12
+#define RT5677_PWR_DAC2 (0x1 << 11)
+#define RT5677_PWR_DAC2_BIT 11
+#define RT5677_PWR_I2S4 (0x1 << 10)
+#define RT5677_PWR_I2S4_BIT 10
+#define RT5677_PWR_SLB (0x1 << 9)
+#define RT5677_PWR_SLB_BIT 9
+#define RT5677_PWR_DAC3 (0x1 << 7)
+#define RT5677_PWR_DAC3_BIT 7
+#define RT5677_PWR_ADCFED2 (0x1 << 4)
+#define RT5677_PWR_ADCFED2_BIT 4
+#define RT5677_PWR_ADCFED1 (0x1 << 3)
+#define RT5677_PWR_ADCFED1_BIT 3
+#define RT5677_PWR_ADC_L (0x1 << 2)
+#define RT5677_PWR_ADC_L_BIT 2
+#define RT5677_PWR_ADC_R (0x1 << 1)
+#define RT5677_PWR_ADC_R_BIT 1
+#define RT5677_PWR_I2C_MASTER (0x1 << 0)
+#define RT5677_PWR_I2C_MASTER_BIT 0
+
+/* Power Management for Digital 2 (0x62) */
+#define RT5677_PWR_ADC_S1F (0x1 << 15)
+#define RT5677_PWR_ADC_S1F_BIT 15
+#define RT5677_PWR_ADC_MF_L (0x1 << 14)
+#define RT5677_PWR_ADC_MF_L_BIT 14
+#define RT5677_PWR_ADC_MF_R (0x1 << 13)
+#define RT5677_PWR_ADC_MF_R_BIT 13
+#define RT5677_PWR_DAC_S1F (0x1 << 12)
+#define RT5677_PWR_DAC_S1F_BIT 12
+#define RT5677_PWR_DAC_M2F_L (0x1 << 11)
+#define RT5677_PWR_DAC_M2F_L_BIT 11
+#define RT5677_PWR_DAC_M2F_R (0x1 << 10)
+#define RT5677_PWR_DAC_M2F_R_BIT 10
+#define RT5677_PWR_DAC_M3F_L (0x1 << 9)
+#define RT5677_PWR_DAC_M3F_L_BIT 9
+#define RT5677_PWR_DAC_M3F_R (0x1 << 8)
+#define RT5677_PWR_DAC_M3F_R_BIT 8
+#define RT5677_PWR_DAC_M4F_L (0x1 << 7)
+#define RT5677_PWR_DAC_M4F_L_BIT 7
+#define RT5677_PWR_DAC_M4F_R (0x1 << 6)
+#define RT5677_PWR_DAC_M4F_R_BIT 6
+#define RT5677_PWR_ADC_S2F (0x1 << 5)
+#define RT5677_PWR_ADC_S2F_BIT 5
+#define RT5677_PWR_ADC_S3F (0x1 << 4)
+#define RT5677_PWR_ADC_S3F_BIT 4
+#define RT5677_PWR_ADC_S4F (0x1 << 3)
+#define RT5677_PWR_ADC_S4F_BIT 3
+#define RT5677_PWR_PDM1 (0x1 << 2)
+#define RT5677_PWR_PDM1_BIT 2
+#define RT5677_PWR_PDM2 (0x1 << 1)
+#define RT5677_PWR_PDM2_BIT 1
+
+/* Power Management for Analog 1 (0x63) */
+#define RT5677_PWR_VREF1 (0x1 << 15)
+#define RT5677_PWR_VREF1_BIT 15
+#define RT5677_PWR_FV1 (0x1 << 14)
+#define RT5677_PWR_FV1_BIT 14
+#define RT5677_PWR_MB (0x1 << 13)
+#define RT5677_PWR_MB_BIT 13
+#define RT5677_PWR_LO1 (0x1 << 12)
+#define RT5677_PWR_LO1_BIT 12
+#define RT5677_PWR_BG (0x1 << 11)
+#define RT5677_PWR_BG_BIT 11
+#define RT5677_PWR_LO2 (0x1 << 10)
+#define RT5677_PWR_LO2_BIT 10
+#define RT5677_PWR_LO3 (0x1 << 9)
+#define RT5677_PWR_LO3_BIT 9
+#define RT5677_PWR_VREF2 (0x1 << 8)
+#define RT5677_PWR_VREF2_BIT 8
+#define RT5677_PWR_FV2 (0x1 << 7)
+#define RT5677_PWR_FV2_BIT 7
+#define RT5677_LDO2_SEL_MASK (0x7 << 4)
+#define RT5677_LDO2_SEL_SFT 4
+#define RT5677_LDO1_SEL_MASK (0x7 << 0)
+#define RT5677_LDO1_SEL_SFT 0
+
+/* Power Management for Analog 2 (0x64) */
+#define RT5677_PWR_BST1 (0x1 << 15)
+#define RT5677_PWR_BST1_BIT 15
+#define RT5677_PWR_BST2 (0x1 << 14)
+#define RT5677_PWR_BST2_BIT 14
+#define RT5677_PWR_CLK_MB1 (0x1 << 13)
+#define RT5677_PWR_CLK_MB1_BIT 13
+#define RT5677_PWR_SLIM (0x1 << 12)
+#define RT5677_PWR_SLIM_BIT 12
+#define RT5677_PWR_MB1 (0x1 << 11)
+#define RT5677_PWR_MB1_BIT 11
+#define RT5677_PWR_PP_MB1 (0x1 << 10)
+#define RT5677_PWR_PP_MB1_BIT 10
+#define RT5677_PWR_PLL1 (0x1 << 9)
+#define RT5677_PWR_PLL1_BIT 9
+#define RT5677_PWR_PLL2 (0x1 << 8)
+#define RT5677_PWR_PLL2_BIT 8
+#define RT5677_PWR_CORE (0x1 << 7)
+#define RT5677_PWR_CORE_BIT 7
+#define RT5677_PWR_CLK_MB (0x1 << 6)
+#define RT5677_PWR_CLK_MB_BIT 6
+#define RT5677_PWR_BST1_P (0x1 << 5)
+#define RT5677_PWR_BST1_P_BIT 5
+#define RT5677_PWR_BST2_P (0x1 << 4)
+#define RT5677_PWR_BST2_P_BIT 4
+#define RT5677_PWR_IPTV (0x1 << 3)
+#define RT5677_PWR_IPTV_BIT 3
+#define RT5677_PWR_25M_CLK (0x1 << 1)
+#define RT5677_PWR_25M_CLK_BIT 1
+#define RT5677_PWR_LDO1 (0x1 << 0)
+#define RT5677_PWR_LDO1_BIT 0
+
+/* Power Management for DSP (0x65) */
+#define RT5677_PWR_SR7 (0x1 << 10)
+#define RT5677_PWR_SR7_BIT 10
+#define RT5677_PWR_SR6 (0x1 << 9)
+#define RT5677_PWR_SR6_BIT 9
+#define RT5677_PWR_SR5 (0x1 << 8)
+#define RT5677_PWR_SR5_BIT 8
+#define RT5677_PWR_SR4 (0x1 << 7)
+#define RT5677_PWR_SR4_BIT 7
+#define RT5677_PWR_SR3 (0x1 << 6)
+#define RT5677_PWR_SR3_BIT 6
+#define RT5677_PWR_SR2 (0x1 << 5)
+#define RT5677_PWR_SR2_BIT 5
+#define RT5677_PWR_SR1 (0x1 << 4)
+#define RT5677_PWR_SR1_BIT 4
+#define RT5677_PWR_SR0 (0x1 << 3)
+#define RT5677_PWR_SR0_BIT 3
+#define RT5677_PWR_MLT (0x1 << 2)
+#define RT5677_PWR_MLT_BIT 2
+#define RT5677_PWR_DSP (0x1 << 1)
+#define RT5677_PWR_DSP_BIT 1
+#define RT5677_PWR_DSP_CPU (0x1 << 0)
+#define RT5677_PWR_DSP_CPU_BIT 0
+
+/* Power Status for DSP (0x66) */
+#define RT5677_PWR_SR7_RDY (0x1 << 9)
+#define RT5677_PWR_SR7_RDY_BIT 9
+#define RT5677_PWR_SR6_RDY (0x1 << 8)
+#define RT5677_PWR_SR6_RDY_BIT 8
+#define RT5677_PWR_SR5_RDY (0x1 << 7)
+#define RT5677_PWR_SR5_RDY_BIT 7
+#define RT5677_PWR_SR4_RDY (0x1 << 6)
+#define RT5677_PWR_SR4_RDY_BIT 6
+#define RT5677_PWR_SR3_RDY (0x1 << 5)
+#define RT5677_PWR_SR3_RDY_BIT 5
+#define RT5677_PWR_SR2_RDY (0x1 << 4)
+#define RT5677_PWR_SR2_RDY_BIT 4
+#define RT5677_PWR_SR1_RDY (0x1 << 3)
+#define RT5677_PWR_SR1_RDY_BIT 3
+#define RT5677_PWR_SR0_RDY (0x1 << 2)
+#define RT5677_PWR_SR0_RDY_BIT 2
+#define RT5677_PWR_MLT_RDY (0x1 << 1)
+#define RT5677_PWR_MLT_RDY_BIT 1
+#define RT5677_PWR_DSP_RDY (0x1 << 0)
+#define RT5677_PWR_DSP_RDY_BIT 0
+
+/* Power Management for DSP (0x67) */
+#define RT5677_PWR_SLIM_ISO (0x1 << 11)
+#define RT5677_PWR_SLIM_ISO_BIT 11
+#define RT5677_PWR_CORE_ISO (0x1 << 10)
+#define RT5677_PWR_CORE_ISO_BIT 10
+#define RT5677_PWR_DSP_ISO (0x1 << 9)
+#define RT5677_PWR_DSP_ISO_BIT 9
+#define RT5677_PWR_SR7_ISO (0x1 << 8)
+#define RT5677_PWR_SR7_ISO_BIT 8
+#define RT5677_PWR_SR6_ISO (0x1 << 7)
+#define RT5677_PWR_SR6_ISO_BIT 7
+#define RT5677_PWR_SR5_ISO (0x1 << 6)
+#define RT5677_PWR_SR5_ISO_BIT 6
+#define RT5677_PWR_SR4_ISO (0x1 << 5)
+#define RT5677_PWR_SR4_ISO_BIT 5
+#define RT5677_PWR_SR3_ISO (0x1 << 4)
+#define RT5677_PWR_SR3_ISO_BIT 4
+#define RT5677_PWR_SR2_ISO (0x1 << 3)
+#define RT5677_PWR_SR2_ISO_BIT 3
+#define RT5677_PWR_SR1_ISO (0x1 << 2)
+#define RT5677_PWR_SR1_ISO_BIT 2
+#define RT5677_PWR_SR0_ISO (0x1 << 1)
+#define RT5677_PWR_SR0_ISO_BIT 1
+#define RT5677_PWR_MLT_ISO (0x1 << 0)
+#define RT5677_PWR_MLT_ISO_BIT 0
+
+/* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
+#define RT5677_I2S_MS_MASK (0x1 << 15)
+#define RT5677_I2S_MS_SFT 15
+#define RT5677_I2S_MS_M (0x0 << 15)
+#define RT5677_I2S_MS_S (0x1 << 15)
+#define RT5677_I2S_O_CP_MASK (0x3 << 10)
+#define RT5677_I2S_O_CP_SFT 10
+#define RT5677_I2S_O_CP_OFF (0x0 << 10)
+#define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
+#define RT5677_I2S_O_CP_A_LAW (0x2 << 10)
+#define RT5677_I2S_I_CP_MASK (0x3 << 8)
+#define RT5677_I2S_I_CP_SFT 8
+#define RT5677_I2S_I_CP_OFF (0x0 << 8)
+#define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
+#define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
+#define RT5677_I2S_BP_MASK (0x1 << 7)
+#define RT5677_I2S_BP_SFT 7
+#define RT5677_I2S_BP_NOR (0x0 << 7)
+#define RT5677_I2S_BP_INV (0x1 << 7)
+#define RT5677_I2S_DL_MASK (0x3 << 2)
+#define RT5677_I2S_DL_SFT 2
+#define RT5677_I2S_DL_16 (0x0 << 2)
+#define RT5677_I2S_DL_20 (0x1 << 2)
+#define RT5677_I2S_DL_24 (0x2 << 2)
+#define RT5677_I2S_DL_8 (0x3 << 2)
+#define RT5677_I2S_DF_MASK (0x3 << 0)
+#define RT5677_I2S_DF_SFT 0
+#define RT5677_I2S_DF_I2S (0x0 << 0)
+#define RT5677_I2S_DF_LEFT (0x1 << 0)
+#define RT5677_I2S_DF_PCM_A (0x2 << 0)
+#define RT5677_I2S_DF_PCM_B (0x3 << 0)
+
+/* Clock Tree Control 1 (0x73) */
+#define RT5677_I2S_PD1_MASK (0x7 << 12)
+#define RT5677_I2S_PD1_SFT 12
+#define RT5677_I2S_PD1_1 (0x0 << 12)
+#define RT5677_I2S_PD1_2 (0x1 << 12)
+#define RT5677_I2S_PD1_3 (0x2 << 12)
+#define RT5677_I2S_PD1_4 (0x3 << 12)
+#define RT5677_I2S_PD1_6 (0x4 << 12)
+#define RT5677_I2S_PD1_8 (0x5 << 12)
+#define RT5677_I2S_PD1_12 (0x6 << 12)
+#define RT5677_I2S_PD1_16 (0x7 << 12)
+#define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
+#define RT5677_I2S_BCLK_MS2_SFT 11
+#define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)
+#define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
+#define RT5677_I2S_PD2_MASK (0x7 << 8)
+#define RT5677_I2S_PD2_SFT 8
+#define RT5677_I2S_PD2_1 (0x0 << 8)
+#define RT5677_I2S_PD2_2 (0x1 << 8)
+#define RT5677_I2S_PD2_3 (0x2 << 8)
+#define RT5677_I2S_PD2_4 (0x3 << 8)
+#define RT5677_I2S_PD2_6 (0x4 << 8)
+#define RT5677_I2S_PD2_8 (0x5 << 8)
+#define RT5677_I2S_PD2_12 (0x6 << 8)
+#define RT5677_I2S_PD2_16 (0x7 << 8)
+#define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
+#define RT5677_I2S_BCLK_MS3_SFT 7
+#define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
+#define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
+#define RT5677_I2S_PD3_MASK (0x7 << 4)
+#define RT5677_I2S_PD3_SFT 4
+#define RT5677_I2S_PD3_1 (0x0 << 4)
+#define RT5677_I2S_PD3_2 (0x1 << 4)
+#define RT5677_I2S_PD3_3 (0x2 << 4)
+#define RT5677_I2S_PD3_4 (0x3 << 4)
+#define RT5677_I2S_PD3_6 (0x4 << 4)
+#define RT5677_I2S_PD3_8 (0x5 << 4)
+#define RT5677_I2S_PD3_12 (0x6 << 4)
+#define RT5677_I2S_PD3_16 (0x7 << 4)
+#define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
+#define RT5677_I2S_BCLK_MS4_SFT 3
+#define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
+#define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
+#define RT5677_I2S_PD4_MASK (0x7 << 0)
+#define RT5677_I2S_PD4_SFT 0
+#define RT5677_I2S_PD4_1 (0x0 << 0)
+#define RT5677_I2S_PD4_2 (0x1 << 0)
+#define RT5677_I2S_PD4_3 (0x2 << 0)
+#define RT5677_I2S_PD4_4 (0x3 << 0)
+#define RT5677_I2S_PD4_6 (0x4 << 0)
+#define RT5677_I2S_PD4_8 (0x5 << 0)
+#define RT5677_I2S_PD4_12 (0x6 << 0)
+#define RT5677_I2S_PD4_16 (0x7 << 0)
+
+/* Clock Tree Control 2 (0x74) */
+#define RT5677_I2S_PD5_MASK (0x7 << 12)
+#define RT5677_I2S_PD5_SFT 12
+#define RT5677_I2S_PD5_1 (0x0 << 12)
+#define RT5677_I2S_PD5_2 (0x1 << 12)
+#define RT5677_I2S_PD5_3 (0x2 << 12)
+#define RT5677_I2S_PD5_4 (0x3 << 12)
+#define RT5677_I2S_PD5_6 (0x4 << 12)
+#define RT5677_I2S_PD5_8 (0x5 << 12)
+#define RT5677_I2S_PD5_12 (0x6 << 12)
+#define RT5677_I2S_PD5_16 (0x7 << 12)
+#define RT5677_I2S_PD6_MASK (0x7 << 8)
+#define RT5677_I2S_PD6_SFT 8
+#define RT5677_I2S_PD6_1 (0x0 << 8)
+#define RT5677_I2S_PD6_2 (0x1 << 8)
+#define RT5677_I2S_PD6_3 (0x2 << 8)
+#define RT5677_I2S_PD6_4 (0x3 << 8)
+#define RT5677_I2S_PD6_6 (0x4 << 8)
+#define RT5677_I2S_PD6_8 (0x5 << 8)
+#define RT5677_I2S_PD6_12 (0x6 << 8)
+#define RT5677_I2S_PD6_16 (0x7 << 8)
+#define RT5677_I2S_PD7_MASK (0x7 << 4)
+#define RT5677_I2S_PD7_SFT 4
+#define RT5677_I2S_PD7_1 (0x0 << 4)
+#define RT5677_I2S_PD7_2 (0x1 << 4)
+#define RT5677_I2S_PD7_3 (0x2 << 4)
+#define RT5677_I2S_PD7_4 (0x3 << 4)
+#define RT5677_I2S_PD7_6 (0x4 << 4)
+#define RT5677_I2S_PD7_8 (0x5 << 4)
+#define RT5677_I2S_PD7_12 (0x6 << 4)
+#define RT5677_I2S_PD7_16 (0x7 << 4)
+#define RT5677_I2S_PD8_MASK (0x7 << 0)
+#define RT5677_I2S_PD8_SFT 0
+#define RT5677_I2S_PD8_1 (0x0 << 0)
+#define RT5677_I2S_PD8_2 (0x1 << 0)
+#define RT5677_I2S_PD8_3 (0x2 << 0)
+#define RT5677_I2S_PD8_4 (0x3 << 0)
+#define RT5677_I2S_PD8_6 (0x4 << 0)
+#define RT5677_I2S_PD8_8 (0x5 << 0)
+#define RT5677_I2S_PD8_12 (0x6 << 0)
+#define RT5677_I2S_PD8_16 (0x7 << 0)
+
+/* Clock Tree Control 3 (0x75) */
+#define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
+#define RT5677_DSP_ASRC_O_SFT 6
+#define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)
+#define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
+#define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)
+#define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
+#define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
+#define RT5677_DSP_ASRC_I_SFT 4
+#define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)
+#define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
+#define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)
+#define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
+#define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
+#define RT5677_DSP_BUS_PD_SFT 0
+#define RT5677_DSP_BUS_PD_1 (0x0 << 0)
+#define RT5677_DSP_BUS_PD_2 (0x1 << 0)
+#define RT5677_DSP_BUS_PD_3 (0x2 << 0)
+#define RT5677_DSP_BUS_PD_4 (0x3 << 0)
+#define RT5677_DSP_BUS_PD_6 (0x4 << 0)
+#define RT5677_DSP_BUS_PD_8 (0x5 << 0)
+#define RT5677_DSP_BUS_PD_12 (0x6 << 0)
+#define RT5677_DSP_BUS_PD_16 (0x7 << 0)
+
+#define RT5677_PLL_INP_MAX 40000000
+#define RT5677_PLL_INP_MIN 2048000
+/* PLL M/N/K Code Control 1 (0x7a 0x7c) */
+#define RT5677_PLL_N_MAX 0x1ff
+#define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
+#define RT5677_PLL_N_SFT 7
+#define RT5677_PLL_K_BP (0x1 << 5)
+#define RT5677_PLL_K_BP_SFT 5
+#define RT5677_PLL_K_MAX 0x1f
+#define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)
+#define RT5677_PLL_K_SFT 0
+
+/* PLL M/N/K Code Control 2 (0x7b 0x7d) */
+#define RT5677_PLL_M_MAX 0xf
+#define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
+#define RT5677_PLL_M_SFT 12
+#define RT5677_PLL_M_BP (0x1 << 11)
+#define RT5677_PLL_M_BP_SFT 11
+
+/* Global Clock Control 1 (0x80) */
+#define RT5677_SCLK_SRC_MASK (0x3 << 14)
+#define RT5677_SCLK_SRC_SFT 14
+#define RT5677_SCLK_SRC_MCLK (0x0 << 14)
+#define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
+#define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */
+#define RT5677_SCLK_SRC_SLIM (0x3 << 14)
+#define RT5677_PLL1_SRC_MASK (0x7 << 11)
+#define RT5677_PLL1_SRC_SFT 11
+#define RT5677_PLL1_SRC_MCLK (0x0 << 11)
+#define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
+#define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)
+#define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
+#define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)
+#define RT5677_PLL1_SRC_RCCLK (0x5 << 11)
+#define RT5677_PLL1_SRC_SLIM (0x6 << 11)
+#define RT5677_MCLK_SRC_MASK (0x1 << 10)
+#define RT5677_MCLK_SRC_SFT 10
+#define RT5677_MCLK1_SRC (0x0 << 10)
+#define RT5677_MCLK2_SRC (0x1 << 10)
+#define RT5677_PLL1_PD_MASK (0x1 << 8)
+#define RT5677_PLL1_PD_SFT 8
+#define RT5677_PLL1_PD_1 (0x0 << 8)
+#define RT5677_PLL1_PD_2 (0x1 << 8)
+#define RT5671_DAC_OSR_MASK (0x3 << 6)
+#define RT5671_DAC_OSR_SFT 6
+#define RT5671_DAC_OSR_128 (0x0 << 6)
+#define RT5671_DAC_OSR_64 (0x1 << 6)
+#define RT5671_DAC_OSR_32 (0x2 << 6)
+#define RT5671_ADC_OSR_MASK (0x3 << 4)
+#define RT5671_ADC_OSR_SFT 4
+#define RT5671_ADC_OSR_128 (0x0 << 4)
+#define RT5671_ADC_OSR_64 (0x1 << 4)
+#define RT5671_ADC_OSR_32 (0x2 << 4)
+
+/* Global Clock Control 2 (0x81) */
+#define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
+#define RT5677_PLL2_PR_SRC_SFT 15
+#define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)
+#define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
+#define RT5677_PLL2_SRC_MASK (0x7 << 12)
+#define RT5677_PLL2_SRC_SFT 12
+#define RT5677_PLL2_SRC_MCLK (0x0 << 12)
+#define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
+#define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
+#define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
+#define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
+#define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
+#define RT5677_PLL2_SRC_SLIM (0x6 << 12)
+#define RT5671_DSP_ASRC_O_SRC (0x3 << 10)
+#define RT5671_DSP_ASRC_O_SRC_SFT 10
+#define RT5671_DSP_ASRC_O_MCLK (0x0 << 10)
+#define RT5671_DSP_ASRC_O_PLL1 (0x1 << 10)
+#define RT5671_DSP_ASRC_O_SLIM (0x2 << 10)
+#define RT5671_DSP_ASRC_O_RCCLK (0x3 << 10)
+#define RT5671_DSP_ASRC_I_SRC (0x3 << 8)
+#define RT5671_DSP_ASRC_I_SRC_SFT 8
+#define RT5671_DSP_ASRC_I_MCLK (0x0 << 8)
+#define RT5671_DSP_ASRC_I_PLL1 (0x1 << 8)
+#define RT5671_DSP_ASRC_I_SLIM (0x2 << 8)
+#define RT5671_DSP_ASRC_I_RCCLK (0x3 << 8)
+#define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
+#define RT5677_DSP_CLK_SRC_SFT 7
+#define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
+#define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
+
+/* VAD Function Control 4 (0x9f) */
+#define RT5677_VAD_SRC_MASK (0x7 << 8)
+#define RT5677_VAD_SRC_SFT 8
+
+/* DSP InBound Control (0xa3) */
+#define RT5677_IB01_SRC_MASK (0x7 << 12)
+#define RT5677_IB01_SRC_SFT 12
+#define RT5677_IB23_SRC_MASK (0x7 << 8)
+#define RT5677_IB23_SRC_SFT 8
+#define RT5677_IB45_SRC_MASK (0x7 << 4)
+#define RT5677_IB45_SRC_SFT 4
+#define RT5677_IB6_SRC_MASK (0x7 << 0)
+#define RT5677_IB6_SRC_SFT 0
+
+/* DSP InBound Control (0xa4) */
+#define RT5677_IB7_SRC_MASK (0x7 << 12)
+#define RT5677_IB7_SRC_SFT 12
+#define RT5677_IB8_SRC_MASK (0x7 << 8)
+#define RT5677_IB8_SRC_SFT 8
+#define RT5677_IB9_SRC_MASK (0x7 << 4)
+#define RT5677_IB9_SRC_SFT 4
+
+/* DSP In/OutBound Control (0xa5) */
+#define RT5677_SEL_SRC_OB23 (0x1 << 4)
+#define RT5677_SEL_SRC_OB23_SFT 4
+#define RT5677_SEL_SRC_OB01 (0x1 << 3)
+#define RT5677_SEL_SRC_OB01_SFT 3
+#define RT5677_SEL_SRC_IB45 (0x1 << 2)
+#define RT5677_SEL_SRC_IB45_SFT 2
+#define RT5677_SEL_SRC_IB23 (0x1 << 1)
+#define RT5677_SEL_SRC_IB23_SFT 1
+#define RT5677_SEL_SRC_IB01 (0x1 << 0)
+#define RT5677_SEL_SRC_IB01_SFT 0
+
+/* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
+#define RT5677_DSP_IB_01_H (0x1 << 15)
+#define RT5677_DSP_IB_01_H_SFT 15
+#define RT5677_DSP_IB_23_H (0x1 << 14)
+#define RT5677_DSP_IB_23_H_SFT 14
+#define RT5677_DSP_IB_45_H (0x1 << 13)
+#define RT5677_DSP_IB_45_H_SFT 13
+#define RT5677_DSP_IB_6_H (0x1 << 12)
+#define RT5677_DSP_IB_6_H_SFT 12
+#define RT5677_DSP_IB_7_H (0x1 << 11)
+#define RT5677_DSP_IB_7_H_SFT 11
+#define RT5677_DSP_IB_8_H (0x1 << 10)
+#define RT5677_DSP_IB_8_H_SFT 10
+#define RT5677_DSP_IB_9_H (0x1 << 9)
+#define RT5677_DSP_IB_9_H_SFT 9
+#define RT5677_DSP_IB_01_L (0x1 << 7)
+#define RT5677_DSP_IB_01_L_SFT 7
+#define RT5677_DSP_IB_23_L (0x1 << 6)
+#define RT5677_DSP_IB_23_L_SFT 6
+#define RT5677_DSP_IB_45_L (0x1 << 5)
+#define RT5677_DSP_IB_45_L_SFT 5
+#define RT5677_DSP_IB_6_L (0x1 << 4)
+#define RT5677_DSP_IB_6_L_SFT 4
+#define RT5677_DSP_IB_7_L (0x1 << 3)
+#define RT5677_DSP_IB_7_L_SFT 3
+#define RT5677_DSP_IB_8_L (0x1 << 2)
+#define RT5677_DSP_IB_8_L_SFT 2
+#define RT5677_DSP_IB_9_L (0x1 << 1)
+#define RT5677_DSP_IB_9_L_SFT 1
+
+#define RT5677_SW_RESET 0x10EC
+
+/* System Clock Source */
+enum {
+ RT5677_SCLK_S_MCLK,
+ RT5677_SCLK_S_PLL1,
+ RT5677_SCLK_S_RCCLK,
+};
+
+/* PLL1 Source */
+enum {
+ RT5677_PLL1_S_MCLK,
+ RT5677_PLL1_S_BCLK1,
+ RT5677_PLL1_S_BCLK2,
+ RT5677_PLL1_S_BCLK3,
+ RT5677_PLL1_S_BCLK4,
+};
+
+enum {
+ RT5677_AIF1,
+ RT5677_AIF2,
+ RT5677_AIF3,
+ RT5677_AIF4,
+ RT5677_AIF5,
+ RT5677_AIFS,
+};
+
+#endif /* __DRIVERS_SOUND_RT5677_H__ */
* Copyright (c) 2013 Google, Inc
*/
+#define LOG_CATEGORY UCLASS_SOUND
+
#include <common.h>
#include <audio_codec.h>
#include <dm.h>
struct sandbox_i2s_priv {
int sum; /* Use to sum the provided audio data */
+ bool silent; /* Sound is silent, don't use SDL */
};
struct sandbox_sound_priv {
int setup_called;
- int sum; /* Use to sum the provided audio data */
+ int sum; /* Use to sum the provided audio data */
+ bool allow_beep; /* true to allow the start_beep() interface */
+ int frequency_hz; /* Beep frequency if active, else 0 */
};
void sandbox_get_codec_params(struct udevice *dev, int *interfacep, int *ratep,
return priv->sum;
}
+void sandbox_set_allow_beep(struct udevice *dev, bool allow)
+{
+ struct sandbox_sound_priv *priv = dev_get_priv(dev);
+
+ priv->allow_beep = allow;
+}
+
+int sandbox_get_beep_frequency(struct udevice *dev)
+{
+ struct sandbox_sound_priv *priv = dev_get_priv(dev);
+
+ return priv->frequency_hz;
+}
+
static int sandbox_codec_set_params(struct udevice *dev, int interface,
int rate, int mclk_freq,
int bits_per_sample, uint channels)
for (i = 0; i < data_size; i++)
priv->sum += ((uint8_t *)data)[i];
- return sandbox_sdl_sound_play(data, data_size);
+ if (!priv->silent) {
+ int ret;
+
+ ret = sandbox_sdl_sound_play(data, data_size);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
static int sandbox_i2s_probe(struct udevice *dev)
{
struct i2s_uc_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct sandbox_i2s_priv *priv = dev_get_priv(dev);
/* Use hard-coded values here */
uc_priv->rfs = 256;
uc_priv->channels = 2;
uc_priv->id = 1;
- /* Ignore any error here - we'll just have no sound */
- sandbox_sdl_sound_init(uc_priv->samplingrate, uc_priv->channels);
+ priv->silent = dev_read_bool(dev, "sandbox,silent");
+
+ if (priv->silent) {
+ log_warning("Sound is silenced\n");
+ } else if (sandbox_sdl_sound_init(uc_priv->samplingrate,
+ uc_priv->channels)) {
+ /* Ignore any error here - we'll just have no sound */
+ priv->silent = true;
+ }
return 0;
}
return i2s_tx_data(uc_priv->i2s, data, data_size);
}
+int sandbox_sound_start_beep(struct udevice *dev, int frequency_hz)
+{
+ struct sandbox_sound_priv *priv = dev_get_priv(dev);
+
+ if (!priv->allow_beep)
+ return -ENOSYS;
+ priv->frequency_hz = frequency_hz;
+
+ return 0;
+}
+
+int sandbox_sound_stop_beep(struct udevice *dev)
+{
+ struct sandbox_sound_priv *priv = dev_get_priv(dev);
+
+ if (!priv->allow_beep)
+ return -ENOSYS;
+ priv->frequency_hz = 0;
+
+ return 0;
+}
+
static int sandbox_sound_probe(struct udevice *dev)
{
return sound_find_codec_i2s(dev);
};
static const struct sound_ops sandbox_sound_ops = {
- .setup = sandbox_sound_setup,
- .play = sandbox_sound_play,
+ .setup = sandbox_sound_setup,
+ .play = sandbox_sound_play,
+ .start_beep = sandbox_sound_start_beep,
+ .stop_beep = sandbox_sound_stop_beep,
};
static const struct udevice_id sandbox_sound_ids[] = {
struct sound_ops *ops = sound_get_ops(dev);
if (!ops->setup)
- return -ENOSYS;
+ return 0;
return ops->setup(dev);
}
return ops->play(dev, data, data_size);
}
+int sound_start_beep(struct udevice *dev, int frequency_hz)
+{
+ struct sound_ops *ops = sound_get_ops(dev);
+
+ if (!ops->start_beep)
+ return -ENOSYS;
+
+ return ops->start_beep(dev, frequency_hz);
+}
+
+int sound_stop_beep(struct udevice *dev)
+{
+ struct sound_ops *ops = sound_get_ops(dev);
+
+ if (!ops->stop_beep)
+ return -ENOSYS;
+
+ return ops->stop_beep(dev);
+}
+
int sound_beep(struct udevice *dev, int msecs, int frequency_hz)
{
struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
- struct i2s_uc_priv *i2s_uc_priv = dev_get_uclass_priv(uc_priv->i2s);
+ struct i2s_uc_priv *i2s_uc_priv;
unsigned short *data;
uint data_size;
int ret;
if (ret && ret != -EALREADY)
return ret;
+ /* Try using the beep interface if available */
+ ret = sound_start_beep(dev, frequency_hz);
+ if (ret != -ENOSYS) {
+ if (ret)
+ return ret;
+ mdelay(msecs);
+ ret = sound_stop_beep(dev);
+
+ return ret;
+ }
+
/* Buffer length computation */
+ i2s_uc_priv = dev_get_uclass_priv(uc_priv->i2s);
data_size = i2s_uc_priv->samplingrate * i2s_uc_priv->channels;
data_size *= (i2s_uc_priv->bitspersample / SOUND_BITS_IN_BYTE);
data = malloc(data_size);
unsigned int confr;
/* McSPI individual channel configuration */
- confr = readl(&priv->regs->channel[priv->wordlen].chconf);
+ confr = readl(&priv->regs->channel[priv->cs].chconf);
/* wordlength */
confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
help
Enables support for the PCI-based EHCI controller.
+config USB_EHCI_TEGRA
+ bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
+ depends on TEGRA
+ ---help---
+ Enable support for Tegra on-chip EHCI USB controller
+
config USB_EHCI_ZYNQ
bool "Support for Xilinx Zynq on-chip EHCI USB controller"
depends on ARCH_ZYNQ
writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
+ /* Enable PLLs for eventual DDC */
+ writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
+ &hdmi->pad_ctrl1);
+ writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
+ &hdmi->pll_ctrl);
+ writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
+
while (timer_get_us() < tmo) {
if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
return 1;
return r;
}
-static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
+static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode,
+ bool verbose_mode)
{
struct edid1_info edid1;
struct edid_cea861_info cea681[4];
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int i, r, ext_blocks = 0;
- /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
- writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
- &hdmi->pad_ctrl1);
- writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
- &hdmi->pll_ctrl);
- writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
-
/* Reset i2c controller */
setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
if (r == 0) {
r = edid_check_info(&edid1);
if (r) {
- printf("EDID: invalid EDID data\n");
+ if (verbose_mode)
+ printf("EDID: invalid EDID data\n");
r = -EINVAL;
}
}
struct ctfb_res_modes custom;
const char *options;
#ifdef CONFIG_VIDEO_HDMI
- int ret, hpd, hpd_delay, edid;
+ int hpd, hpd_delay, edid;
+ bool hdmi_present;
#endif
int i, overscan_offset, overscan_x, overscan_y;
unsigned int fb_dma_addr;
if (sunxi_display.monitor == sunxi_monitor_dvi ||
sunxi_display.monitor == sunxi_monitor_hdmi) {
/* Always call hdp_detect, as it also enables clocks, etc. */
- ret = sunxi_hdmi_hpd_detect(hpd_delay);
- if (ret) {
+ hdmi_present = (sunxi_hdmi_hpd_detect(hpd_delay) == 1);
+ if (hdmi_present && edid) {
printf("HDMI connected: ");
- if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
+ if (sunxi_hdmi_edid_get_mode(&custom, true) == 0)
mode = &custom;
- } else if (hpd) {
+ else
+ hdmi_present = false;
+ }
+ /* Fall back to EDID in case HPD failed */
+ if (edid && !hdmi_present) {
+ if (sunxi_hdmi_edid_get_mode(&custom, false) == 0) {
+ mode = &custom;
+ hdmi_present = true;
+ }
+ }
+ /* Shut down when display was not found */
+ if ((hpd || edid) && !hdmi_present) {
sunxi_hdmi_shutdown();
sunxi_display.monitor = sunxi_get_default_mon(false);
} /* else continue with hdmi/dvi without a cable connected */
}
/*
- * We support displaying 8bpp BMPs on 16bpp LCDs
+ * We support displaying 8bpp and 24bpp BMPs on 16bpp LCDs
* and displaying 24bpp BMPs on 32bpp LCDs
- * */
+ */
if (bpix != bmp_bpix &&
!(bmp_bpix == 8 && bpix == 16) &&
+ !(bmp_bpix == 24 && bpix == 16) &&
!(bmp_bpix == 24 && bpix == 32)) {
printf("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
bpix, get_unaligned_le16(&bmp->header.bit_count));
case 24:
for (i = 0; i < height; ++i) {
for (j = 0; j < width; j++) {
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
- *(fb++) = *(bmap++);
- *(fb++) = 0;
+ if (bpix == 16) {
+ /* 16bit 555RGB format */
+ *(u16 *)fb = ((bmap[2] >> 3) << 10) |
+ ((bmap[1] >> 3) << 5) |
+ (bmap[0] >> 3);
+ bmap += 3;
+ fb += 2;
+ } else {
+ *(fb++) = *(bmap++);
+ *(fb++) = *(bmap++);
+ *(fb++) = *(bmap++);
+ *(fb++) = 0;
+ }
}
fb -= priv->line_length + width * (bpix / 8);
+ bmap += (padded_width - width) * 3;
}
break;
#endif /* CONFIG_BMP_24BPP */
echo >&2; \
/bin/false)
+PHONY += arch-dtbs
arch-dtbs:
$(Q)$(MAKE) $(build)=$(ARCH_PATH) dtbs
* into 'buffer'.
* Update the number of bytes read in *gotsize or return -1 on fatal errors.
*/
-__u8 get_contents_vfatname_block[MAX_CLUSTSIZE]
- __aligned(ARCH_DMA_MINALIGN);
-
static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos,
__u8 *buffer, loff_t maxsize, loff_t *gotsize)
{
/* align to beginning of next cluster if any */
if (pos) {
+ __u8 *tmp_buffer;
+
actsize = min(filesize, (loff_t)bytesperclust);
- if (get_cluster(mydata, curclust, get_contents_vfatname_block,
- (int)actsize) != 0) {
+ tmp_buffer = malloc_cache_aligned(actsize);
+ if (!tmp_buffer) {
+ debug("Error: allocating buffer\n");
+ return -ENOMEM;
+ }
+
+ if (get_cluster(mydata, curclust, tmp_buffer, actsize) != 0) {
printf("Error reading cluster\n");
+ free(tmp_buffer);
return -1;
}
filesize -= actsize;
actsize -= pos;
- memcpy(buffer, get_contents_vfatname_block + pos, actsize);
+ memcpy(buffer, tmp_buffer + pos, actsize);
+ free(tmp_buffer);
*gotsize += actsize;
if (!filesize)
return 0;
goto out_free_both;
debug("reading %s at pos %llu\n", filename, pos);
- ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
+
+ /* For saving default max clustersize memory allocated to malloc pool */
+ dir_entry *dentptr = itr->dent;
+
+ free(itr);
+
+ itr = NULL;
+
+ ret = get_contents(&fsdata, dentptr, pos, buffer, maxsize, actread);
out_free_both:
free(fsdata.fatbuf);
set_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos, __u8 *buffer,
loff_t maxsize, loff_t *gotsize)
{
- loff_t filesize;
unsigned int bytesperclust = mydata->clust_size * mydata->sect_size;
__u32 curclust = START(dentptr);
__u32 endclust = 0, newclust = 0;
- loff_t cur_pos, offset, actsize, wsize;
+ u64 cur_pos, filesize;
+ loff_t offset, actsize, wsize;
*gotsize = 0;
filesize = pos + maxsize;
curclust = endclust;
filesize -= cur_pos;
- assert(!(cur_pos % bytesperclust));
+ assert(!do_div(cur_pos, bytesperclust));
set_clusters:
/* allocate and write */
extern unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
char * const argv[]);
+
+#if defined(CONFIG_CMD_NVEDIT_EFI)
+extern int do_env_print_efi(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+extern int do_env_set_efi(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[]);
+#endif
+
/*
* Error codes that commands return to cmd_process(). We use the standard 0
* and 1 for success and failure, but add one more case - failure with a
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
/* NAND block size is 128 KiB. Synchronize these values with
* corresponding Device Tree entries in Linux:
* MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000
#define CONFIG_SYS_OMAP_ABE_SYSCK
+#ifdef CONFIG_SPL_DFU
+#ifndef CONFIG_SPL_BUILD
#define DFUARGS \
"dfu_bufsiz=0x10000\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_QSPI
+#else
+#undef CONFIG_CMD_BOOTD
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000
+#define DFUARGS \
+ "dfu_bufsiz=0x10000\0" \
+ DFU_ALT_INFO_RAM
+#endif
+#endif
#include <configs/ti_omap5_common.h>
#define CONFIG_ARCH_MISC_INIT
-/* High-level configuration options */
-
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* SD/MMC support */
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-
/* PCI host support */
#undef CONFIG_PCI_SCAN_SHOW
#include "tegra30-common.h"
-/* High-level configuration options */
-
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* PCI host support */
-
/* PCI networking support */
#define CONFIG_E1000_NO_NVM
#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* PCI host support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
-#define CONFIG_POWER_TPS65217
-
#define CONFIG_MACH_TYPE 3589
-/* I2C IP block */
-#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000
-
-/* MMC/SD IP block */
-#define CONFIG_SUPPORT_EMMC_BOOT
-
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE (64 << 10)
#ifndef CONFIG_SPL_BUILD
/* USB configuration */
#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_HOST
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+/* Environment */
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
+#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* PCI host support */
-
-/* General networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* PCI host support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#include "tegra20-common.h"
-/* High-level configuration options */
-
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_SDIO1
#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
-
-/* USB networking support */
-
/* General networking support */
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 1536
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* Dynamic MTD partition support */
-
/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
#define CONFIG_ENV_OFFSET (SZ_2M)
#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
/* General networking support */
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB2.0 Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define CONFIG_TEGRA_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/* Dynamic MTD partition support */
-
/* Environment in NAND (which is 512M), aligned to start of last sector */
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
"initrd_high=0xffffffffffffffff\0" \
BOOTENV
-/* Preserve environment on sd card */
+/* Preserve environment on eMMC */
#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* Use eMMC */
+#define CONFIG_SYS_MMC_ENV_PART 2 /* Use Boot1 partition */
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* PCI host support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#ifndef __LS1012A_COMMON_H
#define __LS1012A_COMMON_H
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
#include <asm/arch/config.h>
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
#include <asm/arch/stream_id_lsch2.h>
*/
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800)
-#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08)
+#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00)
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FW_IN_SPIFLASH
#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x81000000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x800000\0" \
"fdt_addr_r=0x90000000\0" \
"load_addr=0xa0000000\0" \
"kernelheader_addr=0x60800000\0" \
"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0" \
+ "nand_bootcmd=echo Trying load from NAND..;" \
+ "nand info; nand read $load_addr " \
+ "$kernel_start $kernel_size; env exists secureboot " \
+ "&& nand read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
+ "bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV2
#include <asm/arch/config.h>
#endif
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
#define __LS2_COMMON_H
#define CONFIG_REMAKE_ELF
-#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV3
-#define CONFIG_FSL_TZPC_BP147
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_COMMON_H
+#define __LX2_COMMON_H
+
+#include <asm/arch/stream_id_lsch3.h>
+#include <asm/arch/config.h>
+#include <asm/arch/soc.h>
+
+#define CONFIG_REMAKE_ELF
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_MEMAC
+
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_BASE 0x20000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+/* DDR */
+#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
+#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
+#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
+#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Generic Timer Definitions */
+/*
+ * This is not an accurate number. It is used in start.S. The frequency
+ * will be udpated later when get_bus_freq(0) is available.
+ */
+
+#define COUNTER_FREQUENCY 25000000 /* 25MHz */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
+
+/* Serial Port */
+#define CONFIG_PL01X_SERIAL
+#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
+#define CONFIG_SYS_SERIAL0 0x21c0000
+#define CONFIG_SYS_SERIAL1 0x21d0000
+#define CONFIG_SYS_SERIAL2 0x21e0000
+#define CONFIG_SYS_SERIAL3 0x21f0000
+/*below might needs to be removed*/
+#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1, \
+ (void *)CONFIG_SYS_SERIAL2, \
+ (void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/* Define phy_reset function to boot the MC based on mcinitcmd.
+ * This happens late enough to properly fixup u-boot env MAC addresses.
+ */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * Carve out a DDR region which will not be used by u-boot/Linux
+ *
+ * It will be used by MC and Debug Server. The MC region must be
+ * 512MB aligned, so the min size to hide is 512MB.
+ */
+#ifdef CONFIG_FSL_MC_ENET
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#endif
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
+#define I2C_MUX_CH_DEFAULT 0x8
+
+/* RTC */
+#define RTC
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Qixis */
+#define CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* MMC */
+#ifdef CONFIG_MMC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#endif
+
+/* SATA */
+
+#ifdef CONFIG_SCSI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
+#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* USB */
+#ifdef CONFIG_USB
+#define CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+/* FlexSPI */
+#ifdef CONFIG_NXP_FSPI
+#define NXP_FSPI_FLASH_SIZE SZ_64M
+#define NXP_FSPI_FLASH_NUM 1
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE 128
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OFFSET 0x500000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_ENV_OFFSET)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_SYS_MAXARGS 64 /* max command args */
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+/* Initial environment variables */
+#define XSPI_MC_INIT_CMD \
+ "env exists secureboot && " \
+ "esbc_validate 0x20700000 && " \
+ "esbc_validate 0x20740000 ;" \
+ "fsl_mc start mc 0x20a00000 0x20e00000\0"
+
+#define SD_MC_INIT_CMD \
+ "mmc read 0x80000000 0x5000 0x800;" \
+ "mmc read 0x80100000 0x7000 0x800;" \
+ "env exists secureboot && " \
+ "mmc read 0x80700000 0x3800 0x10 && " \
+ "mmc read 0x80740000 0x3A00 0x10 && " \
+ "esbc_validate 0x80700000 && " \
+ "esbc_validate 0x80740000 ;" \
+ "fsl_mc start mc 0x80000000 0x80100000\0"
+
+#define EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:bank_intlv=auto\0" \
+ "ramdisk_addr=0x800000\0" \
+ "ramdisk_size=0x2000000\0" \
+ "fdt_high=0xa0000000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "fdt_addr=0x64f00000\0" \
+ "kernel_start=0x1000000\0" \
+ "kernelheader_start=0x7C0000\0" \
+ "scriptaddr=0x80000000\0" \
+ "scripthdraddr=0x80080000\0" \
+ "fdtheader_addr_r=0x80100000\0" \
+ "kernelheader_addr_r=0x80200000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "kernelheader_size=0x40000\0" \
+ "fdt_addr_r=0x90000000\0" \
+ "load_addr=0xa0000000\0" \
+ "kernel_size=0x2800000\0" \
+ "kernel_addr_sd=0x8000\0" \
+ "kernelhdr_addr_sd=0x3E00\0" \
+ "kernel_size_sd=0x1d000\0" \
+ "kernelhdr_size_sd=0x10\0" \
+ "console=ttyAMA0,38400n8\0" \
+ BOOTENV \
+ "mcmemsize=0x70000000\0" \
+ XSPI_MC_INIT_CMD \
+ "boot_scripts=lx2160ardb_boot.scr\0" \
+ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
+ "scan_dev_for_boot_part=" \
+ "part list ${devtype} ${devnum} devplist; " \
+ "env exists devplist || setenv devplist 1; " \
+ "for distro_bootpart in ${devplist}; do " \
+ "if fstype ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "bootfstype; then " \
+ "run scan_dev_for_boot; " \
+ "fi; " \
+ "done\0" \
+ "scan_dev_for_boot=" \
+ "echo Scanning ${devtype} " \
+ "${devnum}:${distro_bootpart}...; " \
+ "for prefix in ${boot_prefixes}; do " \
+ "run scan_dev_for_scripts; " \
+ "done;\0" \
+ "boot_a_script=" \
+ "load ${devtype} ${devnum}:${distro_bootpart} " \
+ "${scriptaddr} ${prefix}${script}; " \
+ "env exists secureboot && load ${devtype} " \
+ "${devnum}:${distro_bootpart} " \
+ "${scripthdraddr} ${prefix}${boot_script_hdr} " \
+ "&& esbc_validate ${scripthdraddr};" \
+ "source ${scriptaddr}\0"
+
+#define XSPI_NOR_BOOTCOMMAND \
+ "env exists mcinitcmd && env exists secureboot "\
+ "&& esbc_validate 0x20780000; " \
+ "env exists mcinitcmd && " \
+ "fsl_mc lazyapply dpl 0x20d00000; " \
+ "run distro_bootcmd;run xspi_bootcmd; " \
+ "env exists secureboot && esbc_halt;"
+
+#define SD_BOOTCOMMAND \
+ "env exists mcinitcmd && mmcinfo; " \
+ "mmc read 0x80001000 0x6800 0x800; " \
+ "env exists mcinitcmd && env exists secureboot " \
+ " && mmc read 0x80780000 0x3C00 0x10 " \
+ "&& esbc_validate 0x80780000;env exists mcinitcmd " \
+ "&& fsl_mc lazyapply dpl 0x80001000;" \
+ "run distro_bootcmd;run sd_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0)
+#include <config_distro_bootcmd.h>
+
+#endif /* __LX2_COMMON_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __LX2_QDS_H
+#define __LX2_QDS_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK 0x07
+#define QIXIS_XMAP_SHIFT 5
+#define QIXIS_RST_CTL_RESET_EN 0x30
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x20
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD 0x08
+#define NON_EXTENDED_DUTCFG
+#define QIXIS_SDID_MASK 0x07
+#define QIXIS_ESDHC_NO_ADAPTER 0x7
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_100 0x0
+#define QIXIS_SYSCLK_125 0x1
+#define QIXIS_SYSCLK_133 0x2
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_100 0x0
+#define QIXIS_DDRCLK_125 0x1
+#define QIXIS_DDRCLK_133 0x2
+
+#define BRDCFG4_EMI1SEL_MASK 0xF8
+#define BRDCFG4_EMI1SEL_SHIFT 3
+#define BRDCFG4_EMI2SEL_MASK 0x07
+#define BRDCFG4_EMI2SEL_SHIFT 0
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 775
+#define VDD_MV_MAX 925
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 0
+#define I2C_MUX_CH_RTC 0xB
+
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#ifndef __ASSEMBLY__
+u8 qixis_esdhc_detect_quirk(void);
+#endif
+#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
+#endif
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
+
+#define AQ_PHY_ADDR1 0x00
+#define AQ_PHY_ADDR2 0x01
+#define AQ_PHY_ADDR3 0x02
+#define AQ_PHY_ADDR4 0x03
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1 0x0
+
+#define INPHI_PHY_ADDR1 0x0
+#define INPHI_PHY_ADDR2 0x1
+
+#define RGMII_PHY_ADDR1 0x01
+#define RGMII_PHY_ADDR2 0x02
+
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "lx2160aqds_vdd_mv=800\0" \
+ "BOARD=lx2160aqds\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_QDS_H */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __LX2_RDB_H
+#define __LX2_RDB_H
+
+#include "lx2160a_common.h"
+
+/* Qixis */
+#define QIXIS_XMAP_MASK 0x07
+#define QIXIS_XMAP_SHIFT 5
+#define QIXIS_RST_CTL_RESET_EN 0x30
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x20
+#define QIXIS_LBMAP_QSPI 0x00
+#define QIXIS_RCW_SRC_QSPI 0xff
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SD
+#define QIXIS_RCW_SRC_SD 0x08
+#define NON_EXTENDED_DUTCFG
+
+/* VID */
+
+#define I2C_MUX_CH_VOL_MONITOR 0xA
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR 0x63
+#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
+#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv"
+#define CONFIG_VID
+
+/* The lowest and highest voltage allowed*/
+#define VDD_MV_MIN 775
+#define VDD_MV_MAX 855
+
+/* PM Bus commands code for LTC3882*/
+#define PMBUS_CMD_PAGE 0x0
+#define PMBUS_CMD_READ_VOUT 0x8B
+#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
+#define PMBUS_CMD_VOUT_COMMAND 0x21
+#define PWM_CHANNEL0 0x0
+
+#define CONFIG_VOL_MONITOR_LTC3882_SET
+#define CONFIG_VOL_MONITOR_LTC3882_READ
+
+/* RTC */
+#define CONFIG_SYS_RTC_BUS_NUM 4
+
+/* MAC/PHY configuration */
+#if defined(CONFIG_FSL_MC_ENET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "DPMAC1@xgmii"
+
+#define AQR107_PHY_ADDR1 0x04
+#define AQR107_PHY_ADDR2 0x05
+
+#define CORTINA_NO_FW_UPLOAD
+#define CORTINA_PHY_ADDR1 0x0
+#define INPHI_PHY_ADDR1 0x0
+
+#define RGMII_PHY_ADDR1 0x01
+#define RGMII_PHY_ADDR2 0x02
+
+#endif
+
+/* EMC2305 */
+#define I2C_MUX_CH_EMC2305 0x09
+#define I2C_EMC2305_ADDR 0x4D
+#define I2C_EMC2305_CMD 0x40
+#define I2C_EMC2305_PWM 0x80
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ EXTRA_ENV_SETTINGS \
+ "lx2160ardb_vdd_mv=800\0" \
+ "BOARD=lx2160ardb\0" \
+ "xspi_bootcmd=echo Trying load from flexspi..;" \
+ "sf probe 0:0 && sf read $load_addr " \
+ "$kernel_start $kernel_size ; env exists secureboot &&" \
+ "sf read $kernelheader_addr_r $kernelheader_start " \
+ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ " bootm $load_addr#$BOARD\0" \
+ "sd_bootcmd=echo Trying load from sd card..;" \
+ "mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd " \
+ " && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0"
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LX2_RDB_H */
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
-#define CONFIG_KEYBOARD
-
#undef CONFIG_LOADADDR
#define CONFIG_LOADADDR 0x82408000
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB2.0 Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB2.0 Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* PCI host support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB2.0 Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
/* High-level configuration options */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
-/* PCI host support */
-
#define BOARD_EXTRA_ENV_SETTINGS \
"calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
"ramdisk_addr_r\0" \
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* Enable keyboard */
-#define CONFIG_TEGRA_KEYBOARD
-#define CONFIG_KEYBOARD
-
/* NAND support */
#define CONFIG_TEGRA_NAND
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_8M
+
+#define CONFIG_SYS_BOOTM_LEN SZ_16M
+
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+
+/* Environment options */
+#define CONFIG_ENV_SIZE SZ_4K
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "kernel_addr_r=0x80600000\0" \
+ "fdt_addr_r=0x82200000\0" \
+ "scriptaddr=0x82300000\0" \
+ "pxefile_addr_r=0x82400000\0" \
+ "ramdisk_addr_r=0x82500000\0" \
+ BOOTENV
+
+#endif /* __CONFIG_H */
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
/* Tag support */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/* Environment in NAND, aligned to start of last sector */
#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */
-/* USB host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
*/
#define CONFIG_SYS_MMC_MAX_DEVICE 4
-/*
- * select serial console configuration
- */
-
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-/* turn on command-line edit/hist/auto */
-
/*
* Increasing the size of the IO buffer as default nfsargs size is more
* than 256 and so it is not possible to edit it
/*
* Miscellaneous configurable options
*/
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+#define CONFIG_STACKBASE 0x83800000 /* 56MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
+ * this up to 32M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ * the compressed kernel to be up to 32M too.
*
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define CONFIG_LOADADDR 0x81000000
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "fdt_addr_r=0x82000000\0" \
- "ramdisk_addr_r=0x82100000\0"
+ "fdt_addr_r=0x83000000\0" \
+ "ramdisk_addr_r=0x83100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x80108000
/*
* Miscellaneous configurable options
*/
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+#define CONFIG_STACKBASE 0x83800000 /* 56MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
+ * this up to 32M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ * the compressed kernel to be up to 32M too.
*
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define CONFIG_LOADADDR 0x81000000
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "fdt_addr_r=0x82000000\0" \
- "ramdisk_addr_r=0x82100000\0"
+ "fdt_addr_r=0x83000000\0" \
+ "ramdisk_addr_r=0x83100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x80108000
/*
* Miscellaneous configurable options
*/
-#define CONFIG_STACKBASE 0x02800000 /* 40MB */
+#define CONFIG_STACKBASE 0x03800000 /* 56MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
+ * this up to 32M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ * the compressed kernel to be up to 32M too.
*
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define CONFIG_LOADADDR 0x01000000
"scriptaddr=0x10000000\0" \
"pxefile_addr_r=0x10100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "fdt_addr_r=0x02000000\0" \
- "ramdisk_addr_r=0x02100000\0"
+ "fdt_addr_r=0x03000000\0" \
+ "ramdisk_addr_r=0x03100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x00108000
* parameter, the default (2) causes occasional Data Buffer Errors in OUT
* packets depending on the buffer address and size.
*/
-#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
+#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_NAND_SELF_INIT
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
/* Generic Interrupt Controller */
#define CONFIG_GICV2
/*
* Miscellaneous configurable options
*/
-#define CONFIG_STACKBASE 0x82800000 /* 40MB */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
+#define CONFIG_STACKBASE 0x83800000 /* 56MB */
/*
* Memory layout for where various images get loaded by boot scripts:
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
+ * this up to 32M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ * the compressed kernel to be up to 32M too.
*
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define CONFIG_LOADADDR 0x81000000
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
- "fdt_addr_r=0x82000000\0" \
- "ramdisk_addr_r=0x82100000\0"
+ "fdt_addr_r=0x83000000\0" \
+ "ramdisk_addr_r=0x83100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x80108000
/* SPI */
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in SPI */
#define CONFIG_ENV_SPI_MAX_HZ 48000000
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
/* 1MiB flash, environment located as high as possible */
#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* PCI host support */
-
-/* General networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
"third_image=u-boot.bin\0"
#endif
-#define CONFIG_PREBOOT "env exist ${bootdev}preboot && run ${bootdev}preboot"
-
#define CONFIG_ROOTPATH "/nfs/root/path"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs $bootargs root=/dev/nfs rw " \
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
-/* I2C */
-#define CONFIG_SYS_I2C_TEGRA
-
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
-/* General networking support */
-
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
-/* USB Host support */
-#define CONFIG_USB_EHCI_TEGRA
-
-/* USB networking support */
-
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
UCLASS_VIRTIO, /* VirtIO transport device */
UCLASS_W1, /* Dallas 1-Wire bus */
UCLASS_W1_EEPROM, /* one-wire EEPROMs */
- UCLASS_WDT, /* Watchdot Timer driver */
+ UCLASS_WDT, /* Watchdog Timer driver */
UCLASS_COUNT,
UCLASS_INVALID = -1,
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Copyright (C) 2018 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SIFIVE_FU540_PRCI_H
+#define __LINUX_CLK_SIFIVE_FU540_PRCI_H
+
+/* Clock indexes for use by Device Tree data */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Intel HDA audio codec config. This is a mechanicm to configure codecs when
+ * using Intel HDA audio.
+ *
+ * Copyright 2018 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#ifndef __AZALIA_H
+#define __AZALIA_H
+
+#define AZALIA_CODEC_SHIFT 28
+#define AZALIA_NID_SHIFT 20
+#define AZALIA_VERB_SHIFT 8
+
+/* Supported opcodes */
+#define AZALIA_OPCODE_CONFIG_DEFAULT 0x71c
+#define AZALIA_OPCODE_IMPL_ID 0x720
+#define AZALIA_OPCODE_READ_PARAM 0xf00
+
+#define AZALIA_PARAM_VENDOR_ID 0
+
+/* Generate the register value to write a particular byte of a 32-bit value */
+#define AZALIA_SET_BYTE(codec, nid, opcode, val, byte) \
+ ((codec) << AZALIA_CODEC_SHIFT | \
+ (nid) << AZALIA_NID_SHIFT | \
+ ((opcode) + (byte)) << AZALIA_VERB_SHIFT | \
+ (((val) >> ((byte) * 8)) & 0xff))
+
+/* Generate the register value to write all bytes of a 32-bit value */
+#define AZALIA_WORD(codec, nid, opcode, val) \
+ (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
+ AZALIA_SET_BYTE(codec, nid, opcode, val, 1) | \
+ AZALIA_SET_BYTE(codec, nid, opcode, val, 2) | \
+ AZALIA_SET_BYTE(codec, nid, opcode, val, 3))
+
+#define AZALIA_PIN_CFG(codec, nid, val) \
+ AZALIA_WORD(codec, nid, AZALIA_OPCODE_CONFIG_DEFAULT, val)
+
+#define AZALIA_SUBVENDOR(codec, val) \
+ AZALIA_WORD(codec, 1, AZALIA_OPCODE_IMPL_ID, val)
+
+#endif /* __AZALIA_H */
/* UHS register */
#define DWMCI_DDR_MODE (1 << 16)
+/* Internal IDMAC interrupt defines */
+#define DWMCI_IDINTEN_RI BIT(1)
+#define DWMCI_IDINTEN_TI BIT(0)
+
+#define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \
+ DWMCI_IDINTEN_RI)
+
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
char *supported_languages;
};
+/* Boot manager load options */
+#define LOAD_OPTION_ACTIVE 0x00000001
+#define LOAD_OPTION_FORCE_RECONNECT 0x00000002
+#define LOAD_OPTION_HIDDEN 0x00000008
+/* All values 0x00000200-0x00001F00 are reserved */
+#define LOAD_OPTION_CATEGORY 0x00001F00
+#define LOAD_OPTION_CATEGORY_BOOT 0x00000000
+#define LOAD_OPTION_CATEGORY_APP 0x00000100
+
#endif
/* Called from places to check whether a timer expired */
void efi_timer_check(void);
/* PE loader implementation */
-void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
- struct efi_loaded_image *loaded_image_info);
+efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
+ struct efi_loaded_image *loaded_image_info);
/* Called once to store the pristine gd pointer */
void efi_save_gd(void);
/* Special case handler for error/abort that just tries to dtrt to get
void efi_delete_handle(efi_handle_t obj);
/* Call this to validate a handle and find the EFI object for it */
struct efi_object *efi_search_obj(const efi_handle_t handle);
+/* Start image */
+efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
+ efi_uintn_t *exit_data_size,
+ u16 **exit_data);
/* Find a protocol on a handle */
efi_status_t efi_search_protocol(const efi_handle_t handle,
const efi_guid_t *protocol_guid,
struct efi_loaded_image_obj **handle_ptr,
struct efi_loaded_image **info_ptr);
efi_status_t efi_load_image_from_path(struct efi_device_path *file_path,
- void **buffer);
+ void **buffer, efi_uintn_t *size);
/* Print information about all loaded images */
void efi_print_image_infos(void *pc);
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Support for Intel High-Definition Audio codec
+ *
+ * Copyright 2018 Google LLC
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef __HDA_CODEC_H_
+#define __HDA_CODEC_H_
+
+struct hda_regs;
+
+/**
+ * struct hda_codec_priv - Private data required by the HDA codec
+ *
+ * @regs: HDA registers
+ * @beep_nid: Node ID of beep node (>0)
+ */
+struct hda_codec_priv {
+ struct hda_regs *regs;
+ uint beep_nid;
+};
+
+/**
+ * hda_wait_for_ready() - Wait for the codec to indicate it is ready
+ *
+ * @regs: HDA registers
+ * @return 0 if OK -ETIMEDOUT if codec did not respond in time
+ */
+int hda_wait_for_ready(struct hda_regs *regs);
+
+/**
+ * hda_wait_for_valid() - Wait for the codec to accept the last command
+ *
+ * @regs: HDA registers
+ * @return 0 if OK -ETIMEDOUT if codec did not respond in time
+ */
+int hda_wait_for_valid(struct hda_regs *regs);
+
+/**
+ * hda_codec_detect() - Detect which codecs are present
+ *
+ * @regs: HDA registers
+ * @return bit mask of active codecs (0 if none)
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_detect(struct hda_regs *regs);
+
+/**
+ * hda_codecs_init() - Init all codecs
+ *
+ * @dev: Sound device
+ * @regs: HDA registers
+ * @codec_mask: Mask of codecs to init (bits 3:0)
+ * @return 0 if OK, -ve on error
+ */
+int hda_codecs_init(struct udevice *dev, struct hda_regs *regs, u32 codec_mask);
+
+/**
+ * hda_codec_start_beep() - Start beeping
+ *
+ * This tells the sound hardware to start a beep. It will continue until stopped
+ * by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ve on error
+ */
+int hda_codec_start_beep(struct udevice *dev, int frequency_hz);
+
+/**
+ * hda_codec_stop_beep() - Stop beeping
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+int hda_codec_stop_beep(struct udevice *dev);
+
+/**
+ * hda_codec_init() - Set up the HDA codec base address
+ *
+ * This should be called at the start of the probe() method.
+ *
+ * @dev: Sound device
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_init(struct udevice *dev);
+
+/**
+ * hda_codec_finish_init() - Finish setting up the HDA codec base address
+ *
+ * This should be called at the end of the probe() method.
+ *
+ * @dev: Sound device
+ * @return 0 if OK, -ve on error
+ */
+int hda_codec_finish_init(struct udevice *dev);
+
+#endif /* __HDA_CODEC_H_ */
/** Log levels supported, ranging from most to least important */
enum log_level_t {
- LOGL_EMERG = 0, /*U-Boot is unstable */
+ LOGL_EMERG = 0, /* U-Boot is unstable */
LOGL_ALERT, /* Action must be taken immediately */
LOGL_CRIT, /* Critical conditions */
LOGL_ERR, /* Error that prevents something from working */
#endif
#if CONFIG_IS_ENABLED(LOG)
+#ifdef LOG_DEBUG
+#define _LOG_DEBUG 1
+#else
+#define _LOG_DEBUG 0
+#endif
/* Emit a log record if the level is less that the maximum */
#define log(_cat, _level, _fmt, _args...) ({ \
int _l = _level; \
- if (CONFIG_IS_ENABLED(LOG) && _l <= _LOG_MAX_LEVEL) \
+ if (CONFIG_IS_ENABLED(LOG) && (_l <= _LOG_MAX_LEVEL || _LOG_DEBUG)) \
_log((enum log_category_t)(_cat), _l, __FILE__, __LINE__, \
__func__, \
pr_fmt(_fmt), ##_args); \
int mmc_init(struct mmc *mmc);
int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
+#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+int mmc_deinit(struct mmc *mmc);
+#endif
+
/**
* mmc_of_parse() - Parse the device tree to get the capabilities of the host
*
#define BIOS_CTRL_BIOSWE BIT(0)
-/* Operations for the Platform Controller Hub */
+/* All the supported PCH ioctls */
+enum pch_req_t {
+ /* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
+ PCH_REQ_HDA_CONFIG,
+
+ PCH_REQ_TEST1, /* Test requests for sandbox driver */
+ PCH_REQ_TEST2,
+ PCH_REQ_TEST3,
+
+ PCH_REQ_COUNT, /* Number of ioctrls supported */
+};
+
+/**
+ * struct pch_ops - Operations for the Platform Controller Hub
+ *
+ * Consider using ioctl() to add rarely used or driver-specific operations.
+ */
struct pch_ops {
/**
* get_spi_base() - get the address of SPI base
* @return 0 if OK, -ve on error (e.g. there is no IO base)
*/
int (*get_io_base)(struct udevice *dev, u32 *iobasep);
+
+ /**
+ * ioctl() - perform misc read/write operations
+ *
+ * This is a catch-all operation intended to avoid adding lots of
+ * methods to this uclass, of which few are commonly used. Uncommon
+ * operations that pertain only to a few devices in this uclass should
+ * use this method instead of adding new methods.
+ *
+ * @dev: PCH device to check
+ * @req: PCH request ID
+ * @data: Input/output data
+ * @size: Size of input data (and maximum size of output data)
+ * @return size of output data on sucesss, -ve on error
+ */
+ int (*ioctl)(struct udevice *dev, enum pch_req_t req, void *data,
+ int size);
};
#define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops)
*/
int pch_get_io_base(struct udevice *dev, u32 *iobasep);
+/**
+ * pch_ioctl() - perform misc read/write operations
+ *
+ * This is a catch-all operation intended to avoid adding lots of
+ * methods to this uclass, of which few are commonly used. Uncommon
+ * operations that pertain only to a few devices in this uclass should
+ * use this method instead of adding new methods.
+ *
+ * @dev: PCH device to check
+ * @req: PCH request ID
+ * @data: Input/output data
+ * @size: Size of input data (and maximum size of output data)
+ * @return size of output data on sucesss, -ve on error
+ */
+int pch_ioctl(struct udevice *dev, ulong req, void *data, int size);
+
#endif
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
pci_dev_t pci_find_class(unsigned int find_class, int index);
-extern int pci_hose_config_device(struct pci_controller *hose,
- pci_dev_t dev,
- unsigned long io,
- pci_addr_t mem,
- unsigned long command);
-
extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
int cap);
extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
*
* Every device on a PCI bus has this per-child data.
*
- * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
+ * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
* PCI bus (i.e. UCLASS_PCI)
*
* @devfn: Encoded device and function index - see PCI_DEVFN()
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
#define PCI_CLASS_MULTIMEDIA_PHONE 0x0402
+#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
#define PCI_BASE_CLASS_MEMORY 0x05
#define PCI_DEVICE_ID_CREATIVE_EMU10K1 0x0002
#define PCI_DEVICE_ID_CREATIVE_20K1 0x0005
#define PCI_DEVICE_ID_CREATIVE_20K2 0x000b
+#define PCI_DEVICE_ID_CREATIVE_CA01322 0x0011
#define PCI_SUBDEVICE_ID_CREATIVE_SB0760 0x0024
#define PCI_SUBDEVICE_ID_CREATIVE_SB08801 0x0041
#define PCI_SUBDEVICE_ID_CREATIVE_SB08802 0x0042
#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI 0x2806
#define PCI_DEVICE_ID_INTEL_ICH8_0 0x2810
#define PCI_DEVICE_ID_INTEL_ICH8_1 0x2811
#define PCI_DEVICE_ID_INTEL_ICH8_2 0x2812
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI 0x9c83
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_HDA 0x9ca0
+#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_ADSP 0x9cb6
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC 0x9cc3
#define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
/* Operations for sound */
struct sound_ops {
/**
- * setup() - Set up to play a sound
+ * setup() - Set up to play a sound (optional)
*/
int (*setup)(struct udevice *dev);
* @return 0 if OK, -ve on error
*/
int (*play)(struct udevice *dev, void *data, uint data_size);
+
+ /**
+ * start_beep() - Start beeping (optional)
+ *
+ * This tells the sound hardware to start a beep. It will continue until
+ * stopped by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ENOSYS if not supported, -ve on error
+ */
+ int (*start_beep)(struct udevice *dev, int frequency_hz);
+
+ /**
+ * stop_beep() - Stop beeping (optional)
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+ int (*stop_beep)(struct udevice *dev);
};
#define sound_get_ops(dev) ((struct sound_ops *)(dev)->driver->ops)
*/
int sound_beep(struct udevice *dev, int msecs, int frequency_hz);
+/**
+ * sound_start_beep() - Start beeping
+ *
+ * This tells the sound hardware to start a beep. It will continue until stopped
+ * by sound_stop_beep().
+ *
+ * @dev: Sound device
+ * @frequency_hz: Beep frequency in hertz
+ * @return if OK, -ve on error
+ */
+int sound_start_beep(struct udevice *dev, int frequency_hz);
+
+/**
+ * sound_stop_beep() - Stop beeping
+ *
+ * This tells the sound hardware to stop a previously started beep.
+ *
+ * @dev: Sound device
+ * @return if OK, -ve on error
+ */
+int sound_stop_beep(struct udevice *dev);
+
/**
* sound_find_codec_i2s() - Called by sound drivers to locate codec and i2s
*
u32 size;
u32 flags;
void *arg;
+#ifdef CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK
+ ulong dcrc_data;
+ ulong dcrc_length;
+ ulong dcrc;
+#endif
};
/*
static const struct efi_boot_services *bs;
static const struct efi_runtime_services *rs;
-#define LOAD_OPTION_ACTIVE 0x00000001
-#define LOAD_OPTION_FORCE_RECONNECT 0x00000002
-#define LOAD_OPTION_HIDDEN 0x00000008
-
/*
* bootmgr implements the logic of trying to find a payload to boot
* based on the BootOrder + BootXXXX variables, and then loading it.
debug("%s: trying to load \"%ls\" from %pD\n",
__func__, lo.label, lo.file_path);
- ret = efi_load_image_from_path(lo.file_path, &image);
+ ret = efi_load_image_from_path(lo.file_path, &image, &size);
if (ret != EFI_SUCCESS)
goto error;
void *image = NULL;
int i, num;
- __efi_entry_check();
-
bs = systab.boottime;
rs = systab.runtime;
bootorder = get_var(L"BootOrder", &efi_global_variable_guid, &size);
- if (!bootorder)
+ if (!bootorder) {
+ printf("BootOrder not defined\n");
goto error;
+ }
num = size / sizeof(uint16_t);
for (i = 0; i < num; i++) {
free(bootorder);
error:
- __efi_exit_check();
-
return image;
}
static volatile void *efi_gd, *app_gd;
#endif
-static int entry_count;
+/* 1 if inside U-Boot code, 0 if inside EFI payload code */
+static int entry_count = 1;
static int nesting_level;
/* GUID of the device tree table */
const efi_guid_t efi_guid_fdt = EFI_FDT_GUID;
/**
* efi_setup_loaded_image() - initialize a loaded image
- * @info: loaded image info to be passed to the entry point of the image
- * @obj: internal object associated with the loaded image
- * @device_path: device path of the loaded image
- * @file_path: file path of the loaded image
*
* Initialize a loaded_image_info and loaded_image_info object with correct
* protocols, boot-device, etc.
*
- * Return: status code
+ * In case of an error *handle_ptr and *info_ptr are set to NULL and an error
+ * code is returned.
+ *
+ * @device_path: device path of the loaded image
+ * @file_path: file path of the loaded image
+ * @handle_ptr: handle of the loaded image
+ * @info_ptr: loaded image protocol
+ * Return: status code
*/
efi_status_t efi_setup_loaded_image(struct efi_device_path *device_path,
struct efi_device_path *file_path,
struct efi_loaded_image **info_ptr)
{
efi_status_t ret;
- struct efi_loaded_image *info;
- struct efi_loaded_image_obj *obj;
+ struct efi_loaded_image *info = NULL;
+ struct efi_loaded_image_obj *obj = NULL;
+
+ /* In case of EFI_OUT_OF_RESOURCES avoid illegal free by caller. */
+ *handle_ptr = NULL;
+ *info_ptr = NULL;
info = calloc(1, sizeof(*info));
if (!info)
/* Add internal object to object list */
efi_add_handle(&obj->header);
- if (info_ptr)
- *info_ptr = info;
- if (handle_ptr)
- *handle_ptr = obj;
-
info->revision = EFI_LOADED_IMAGE_PROTOCOL_REVISION;
info->file_path = file_path;
info->system_table = &systab;
goto failure;
#endif
+ if (info_ptr)
+ *info_ptr = info;
+ if (handle_ptr)
+ *handle_ptr = obj;
+
return ret;
failure:
printf("ERROR: Failure to install protocols for loaded image\n");
+ efi_delete_handle(&obj->header);
+ free(info);
return ret;
}
/**
* efi_load_image_from_path() - load an image using a file path
- * @file_path: the path of the image to load
- * @buffer: buffer containing the loaded image
*
- * Return: status code
+ * Read a file into a buffer allocated as EFI_BOOT_SERVICES_DATA. It is the
+ * callers obligation to update the memory type as needed.
+ *
+ * @file_path: the path of the image to load
+ * @buffer: buffer containing the loaded image
+ * @size: size of the loaded image
+ * Return: status code
*/
efi_status_t efi_load_image_from_path(struct efi_device_path *file_path,
- void **buffer)
+ void **buffer, efi_uintn_t *size)
{
struct efi_file_info *info = NULL;
struct efi_file_handle *f;
static efi_status_t ret;
+ u64 addr;
efi_uintn_t bs;
+ /* In case of failure nothing is returned */
+ *buffer = NULL;
+ *size = 0;
+
+ /* Open file */
f = efi_file_from_path(file_path);
if (!f)
return EFI_DEVICE_ERROR;
+ /* Get file size */
bs = 0;
EFI_CALL(ret = f->getinfo(f, (efi_guid_t *)&efi_file_info_guid,
&bs, info));
- if (ret == EFI_BUFFER_TOO_SMALL) {
- info = malloc(bs);
- EFI_CALL(ret = f->getinfo(f, (efi_guid_t *)&efi_file_info_guid,
- &bs, info));
- }
- if (ret != EFI_SUCCESS)
+ if (ret != EFI_BUFFER_TOO_SMALL) {
+ ret = EFI_DEVICE_ERROR;
goto error;
+ }
- ret = efi_allocate_pool(EFI_LOADER_DATA, info->file_size, buffer);
- if (ret)
+ info = malloc(bs);
+ EFI_CALL(ret = f->getinfo(f, (efi_guid_t *)&efi_file_info_guid, &bs,
+ info));
+ if (ret != EFI_SUCCESS)
goto error;
+ /*
+ * When reading the file we do not yet know if it contains an
+ * application, a boottime driver, or a runtime driver. So here we
+ * allocate a buffer as EFI_BOOT_SERVICES_DATA. The caller has to
+ * update the reservation according to the image type.
+ */
bs = info->file_size;
- EFI_CALL(ret = f->read(f, &bs, *buffer));
-
-error:
- free(info);
- EFI_CALL(f->close(f));
-
+ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_BOOT_SERVICES_DATA,
+ efi_size_in_pages(bs), &addr);
if (ret != EFI_SUCCESS) {
- efi_free_pool(*buffer);
- *buffer = NULL;
+ ret = EFI_OUT_OF_RESOURCES;
+ goto error;
}
+ /* Read file */
+ EFI_CALL(ret = f->read(f, &bs, (void *)(uintptr_t)addr));
+ if (ret != EFI_SUCCESS)
+ efi_free_pages(addr, efi_size_in_pages(bs));
+ *buffer = (void *)(uintptr_t)addr;
+ *size = bs;
+error:
+ EFI_CALL(f->close(f));
+ free(info);
return ret;
}
efi_uintn_t source_size,
efi_handle_t *image_handle)
{
+ struct efi_device_path *dp, *fp;
struct efi_loaded_image *info = NULL;
struct efi_loaded_image_obj **image_obj =
(struct efi_loaded_image_obj **)image_handle;
}
if (!source_buffer) {
- struct efi_device_path *dp, *fp;
-
- ret = efi_load_image_from_path(file_path, &source_buffer);
+ ret = efi_load_image_from_path(file_path, &source_buffer,
+ &source_size);
if (ret != EFI_SUCCESS)
- goto failure;
+ goto error;
/*
* split file_path which contains both the device and
* file parts:
*/
efi_dp_split_file_path(file_path, &dp, &fp);
- ret = efi_setup_loaded_image(dp, fp, image_obj, &info);
- if (ret != EFI_SUCCESS)
- goto failure;
} else {
/* In this case, file_path is the "device" path, i.e.
* something like a HARDWARE_DEVICE:MEMORY_MAPPED
*/
- ret = efi_setup_loaded_image(file_path, NULL, image_obj, &info);
+ u64 addr;
+ void *dest_buffer;
+
+ ret = efi_allocate_pages(EFI_ALLOCATE_ANY_PAGES,
+ EFI_RUNTIME_SERVICES_CODE,
+ efi_size_in_pages(source_size), &addr);
if (ret != EFI_SUCCESS)
goto error;
+ dest_buffer = (void *)(uintptr_t)addr;
+ memcpy(dest_buffer, source_buffer, source_size);
+ source_buffer = dest_buffer;
+
+ dp = file_path;
+ fp = NULL;
}
- (*image_obj)->entry = efi_load_pe(*image_obj, source_buffer, info);
- if (!(*image_obj)->entry) {
- ret = EFI_UNSUPPORTED;
- goto failure;
- }
+ ret = efi_setup_loaded_image(dp, fp, image_obj, &info);
+ if (ret != EFI_SUCCESS)
+ goto error_invalid_image;
+ ret = efi_load_pe(*image_obj, source_buffer, info);
+ if (ret != EFI_SUCCESS)
+ goto error_invalid_image;
+ /* Update the type of the allocated memory */
+ efi_add_memory_map((uintptr_t)source_buffer,
+ efi_size_in_pages(source_size),
+ info->image_code_type, false);
info->system_table = &systab;
info->parent_handle = parent_image;
return EFI_EXIT(EFI_SUCCESS);
-failure:
+error_invalid_image:
+ /* The image is invalid. Release all associated resources. */
+ efi_free_pages((uintptr_t)source_buffer,
+ efi_size_in_pages(source_size));
efi_delete_handle(*image_handle);
*image_handle = NULL;
free(info);
*
* Return: status code
*/
-static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
- efi_uintn_t *exit_data_size,
- u16 **exit_data)
+efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
+ efi_uintn_t *exit_data_size,
+ u16 **exit_data)
{
struct efi_loaded_image_obj *image_obj =
(struct efi_loaded_image_obj *)image_handle;
return start;
}
-/*
- * Helper to split a full device path (containing both device and file
- * parts) into it's constituent parts.
+/**
+ * efi_dp_split_file_path() - split of relative file path from device path
+ *
+ * Given a device path indicating a file on a device, separate the device
+ * path in two: the device path of the actual device and the file path
+ * relative to this device.
+ *
+ * @full_path: device path including device and file path
+ * @device_path: path of the device
+ * @file_path: relative path of the file
+ * Return: status code
*/
efi_status_t efi_dp_split_file_path(struct efi_device_path *full_path,
struct efi_device_path **device_path,
while (!EFI_DP_TYPE(p, MEDIA_DEVICE, FILE_PATH)) {
p = efi_dp_next(p);
if (!p)
- return EFI_OUT_OF_RESOURCES;
+ return EFI_INVALID_PARAMETER;
}
fp = efi_dp_dup(p);
if (!fp)
.flush = efi_file_flush,
};
+/**
+ * efi_file_from_path() - open file via device path
+ *
+ * @fp: device path
+ * @return: EFI_FILE_PROTOCOL for the file or NULL
+ */
struct efi_file_handle *efi_file_from_path(struct efi_device_path *fp)
{
struct efi_simple_file_system_protocol *v;
if (ret != EFI_SUCCESS)
return NULL;
- /* skip over device-path nodes before the file path: */
+ /* Skip over device-path nodes before the file path. */
while (fp && !EFI_DP_TYPE(fp, MEDIA_DEVICE, FILE_PATH))
fp = efi_dp_next(fp);
+ /*
+ * Step through the nodes of the directory path until the actual file
+ * node is reached which is the final node in the device path.
+ */
while (fp) {
struct efi_device_path_file_path *fdp =
container_of(fp, struct efi_device_path_file_path, dp);
#endif
0 };
-/*
- * Print information about a loaded image.
+/**
+ * efi_print_image_info() - print information about a loaded image
*
* If the program counter is located within the image the offset to the base
* address is shown.
* @obj: EFI object
* @image: loaded image
* @pc: program counter (use NULL to suppress offset output)
- * @return: status code
+ * Return: status code
*/
static efi_status_t efi_print_image_info(struct efi_loaded_image_obj *obj,
struct efi_loaded_image *image,
return EFI_SUCCESS;
}
-/*
- * Print information about all loaded images.
+/**
+ * efi_print_image_infos() - print information about all loaded images
*
* @pc: program counter (use NULL to suppress offset output)
*/
}
}
+/**
+ * efi_loader_relocate() - relocate UEFI binary
+ *
+ * @rel: pointer to the relocation table
+ * @rel_size: size of the relocation table in bytes
+ * @efi_reloc: actual load address of the image
+ * @pref_address: preferred load address of the image
+ * Return: status code
+ */
static efi_status_t efi_loader_relocate(const IMAGE_BASE_RELOCATION *rel,
unsigned long rel_size, void *efi_reloc,
unsigned long pref_address)
return EFI_SUCCESS;
end = (const IMAGE_BASE_RELOCATION *)((const char *)rel + rel_size);
- while (rel < end - 1 && rel->SizeOfBlock) {
+ while (rel < end && rel->SizeOfBlock) {
const uint16_t *relocs = (const uint16_t *)(rel + 1);
i = (rel->SizeOfBlock - sizeof(*rel)) / sizeof(uint16_t);
while (i--) {
/* If the system doesn't support icache_all flush, cross our fingers */
}
-/*
- * Determine the memory types to be used for code and data.
+/**
+ * efi_set_code_and_data_type() - determine the memory types to be used for code
+ * and data.
*
- * @loaded_image_info image descriptor
- * @image_type field Subsystem of the optional header for
+ * @loaded_image_info: image descriptor
+ * @image_type: field Subsystem of the optional header for
* Windows specific field
*/
static void efi_set_code_and_data_type(
}
}
-/*
+/**
+ * efi_load_pe() - relocate EFI binary
+ *
* This function loads all sections from a PE binary into a newly reserved
- * piece of memory. On successful load it then returns the entry point for
- * the binary. Otherwise NULL.
+ * piece of memory. On success the entry point is returned as handle->entry.
+ *
+ * @handle: loaded image handle
+ * @efi: pointer to the EFI binary
+ * @loaded_image_info: loaded image protocol
+ * Return: status code
*/
-void *efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
- struct efi_loaded_image *loaded_image_info)
+efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, void *efi,
+ struct efi_loaded_image *loaded_image_info)
{
IMAGE_NT_HEADERS32 *nt;
IMAGE_DOS_HEADER *dos;
const IMAGE_BASE_RELOCATION *rel;
unsigned long rel_size;
int rel_idx = IMAGE_DIRECTORY_ENTRY_BASERELOC;
- void *entry;
uint64_t image_base;
uint64_t image_size;
unsigned long virt_size = 0;
dos = efi;
if (dos->e_magic != IMAGE_DOS_SIGNATURE) {
printf("%s: Invalid DOS Signature\n", __func__);
- return NULL;
+ return EFI_LOAD_ERROR;
}
nt = (void *) ((char *)efi + dos->e_lfanew);
if (nt->Signature != IMAGE_NT_SIGNATURE) {
printf("%s: Invalid NT Signature\n", __func__);
- return NULL;
+ return EFI_LOAD_ERROR;
}
for (i = 0; machines[i]; i++)
if (!supported) {
printf("%s: Machine type 0x%04x is not supported\n",
__func__, nt->FileHeader.Machine);
- return NULL;
+ return EFI_LOAD_ERROR;
}
/* Calculate upper virtual address boundary */
if (!efi_reloc) {
printf("%s: Could not allocate %lu bytes\n",
__func__, virt_size);
- return NULL;
+ return EFI_OUT_OF_RESOURCES;
}
- entry = efi_reloc + opt->AddressOfEntryPoint;
+ handle->entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
virt_size = ALIGN(virt_size, opt->SectionAlignment);
if (!efi_reloc) {
printf("%s: Could not allocate %lu bytes\n",
__func__, virt_size);
- return NULL;
+ return EFI_OUT_OF_RESOURCES;
}
- entry = efi_reloc + opt->AddressOfEntryPoint;
+ handle->entry = efi_reloc + opt->AddressOfEntryPoint;
rel_size = opt->DataDirectory[rel_idx].Size;
rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress;
virt_size = ALIGN(virt_size, opt->SectionAlignment);
} else {
printf("%s: Invalid optional header magic %x\n", __func__,
nt->OptionalHeader.Magic);
- return NULL;
+ return EFI_LOAD_ERROR;
}
/* Load sections into RAM */
(unsigned long)image_base) != EFI_SUCCESS) {
efi_free_pages((uintptr_t) efi_reloc,
(virt_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT);
- return NULL;
+ return EFI_LOAD_ERROR;
}
/* Flush cache */
handle->reloc_base = efi_reloc;
handle->reloc_size = virt_size;
- return entry;
+ return EFI_SUCCESS;
}
ifeq ($(CONFIG_SANDBOX)$(CONFIG_CPU_V7M)$(CONFIG_X86_64),)
obj-y += \
+efi_selftest_loadimage.o \
efi_selftest_startimage_exit.o \
efi_selftest_startimage_return.o
$(obj)/../../tools/file2include $(obj)/efi_selftest_miniapp_return.efi > \
$(obj)/efi_miniapp_file_image_return.h
+$(obj)/efi_selftest_loadimage.o: $(obj)/efi_miniapp_file_image_exit.h
+
$(obj)/efi_selftest_startimage_exit.o: $(obj)/efi_miniapp_file_image_exit.h
$(obj)/efi_selftest_startimage_return.o: $(obj)/efi_miniapp_file_image_return.h
}
if (image) {
- r = efi_free_pool(image);
+ r = boottime->free_pool(image);
if (r != EFI_SUCCESS) {
efi_st_error("Failed to free image\n");
return EFI_ST_FAILURE;
*/
#include <efi_selftest.h>
-#include <malloc.h>
#include "efi_selftest_hii_data.c"
#define PRINT_TESTNAME efi_st_printf("%s:\n", __func__)
(unsigned int)ret);
goto out;
}
- handles = malloc(handles_size);
- if (!handles) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
+ (void **)&handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
goto out;
}
ret = hii_database_protocol->list_package_lists(hii_database_protocol,
(unsigned int)ret);
goto out;
}
- free(handles);
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ goto out;
+ }
/* STRINGS */
handles = NULL;
ret = EFI_ST_FAILURE;
goto out;
}
- handles = malloc(handles_size);
- if (!handles) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
+ (void **)&handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
ret = EFI_ST_FAILURE;
goto out;
}
ret = EFI_ST_FAILURE;
goto out;
}
- free(handles);
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ goto out;
+ }
/* GUID */
handles = NULL;
ret = EFI_ST_FAILURE;
goto out;
}
- handles = malloc(handles_size);
- if (!handles) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
+ (void **)&handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
ret = EFI_ST_FAILURE;
goto out;
}
ret = EFI_ST_FAILURE;
goto out;
}
- free(handles);
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ ret = EFI_ST_FAILURE;
+ goto out;
+ }
/* KEYBOARD_LAYOUT */
handles = NULL;
ret = EFI_ST_FAILURE;
goto out;
}
- handles = malloc(handles_size);
- if (!handles) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, handles_size,
+ (void **)&handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
ret = EFI_ST_FAILURE;
goto out;
}
ret = EFI_ST_FAILURE;
goto out;
}
- free(handles);
+ ret = boottime->free_pool(handles);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ ret = EFI_ST_FAILURE;
+ goto out;
+ }
result = EFI_ST_SUCCESS;
(unsigned int)ret);
goto out;
}
- guids = malloc(guids_size);
- if (!guids) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, guids_size,
+ (void **)&guids);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
goto out;
}
ret = hii_database_protocol->find_keyboard_layouts(
(unsigned int)ret);
goto out;
}
- free(guids);
+ ret = boottime->free_pool(guids);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ goto out;
+ }
result = EFI_ST_SUCCESS;
(unsigned int)ret);
goto out;
}
- kb_layout = malloc(kb_layout_size);
- if (!kb_layout) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, kb_layout_size,
+ (void **)&kb_layout);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
goto out;
}
ret = hii_database_protocol->get_keyboard_layout(hii_database_protocol,
(unsigned int)ret);
goto out;
}
- free(kb_layout);
+ ret = boottime->free_pool(kb_layout);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("FreePool failed\n");
+ goto out;
+ }
/* current */
kb_layout = NULL;
goto out;
}
string_len += sizeof(u16);
- string = malloc(string_len);
- if (!string) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, string_len,
+ (void **)&string);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
goto out;
}
ret = hii_string_protocol->get_string(hii_string_protocol,
(unsigned int)ret);
goto out;
}
- languages = malloc(languages_len);
- if (!languages) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, languages_len,
+ (void **)&languages);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
goto out;
}
ret = hii_string_protocol->get_languages(hii_string_protocol, handle,
(unsigned int)ret);
goto out;
}
- languages = malloc(languages_len);
- if (!languages) {
- efi_st_error("malloc failed\n");
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, languages_len,
+ (void **)&languages);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("AllocatePool failed\n");
goto out;
}
ret = hii_string_protocol->get_secondary_languages(hii_string_protocol,
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_loadimage
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This test checks the LoadImage and StartImage boot service.
+ *
+ * The efi_selftest_miniapp_exit.efi application is loaded via a file device
+ * path and started.
+ */
+
+#include <efi_selftest.h>
+/* Include containing the efi_selftest_miniapp_exit.efi application */
+#include "efi_miniapp_file_image_exit.h"
+
+/* Block size of compressed disk image */
+#define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8
+
+/* Binary logarithm of the block size */
+#define LB_BLOCK_SIZE 9
+
+#define FILE_NAME L"app.efi"
+#define VOLUME_NAME L"EfiDisk"
+
+static struct efi_boot_services *boottime;
+static efi_handle_t handle_image;
+static efi_handle_t handle_volume;
+
+static const efi_guid_t guid_device_path = DEVICE_PATH_GUID;
+static const efi_guid_t guid_simple_file_system_protocol =
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
+static const efi_guid_t guid_file_info = EFI_FILE_INFO_GUID;
+static const efi_guid_t guid_file_system_info = EFI_FILE_SYSTEM_INFO_GUID;
+
+/* One 8 byte block of the compressed disk image */
+struct line {
+ size_t addr;
+ char *line;
+};
+
+/* Compressed file image */
+struct compressed_file_image {
+ size_t length;
+ struct line lines[];
+};
+
+/* File info including file name */
+struct file_info {
+ struct efi_file_info info;
+ u16 file_name[sizeof(FILE_NAME)];
+};
+
+/* File system info including volume name */
+struct file_system_info {
+ struct efi_file_system_info info;
+ u16 file_name[sizeof(VOLUME_NAME)];
+};
+
+/* Compressed file image */
+static struct compressed_file_image img = EFI_ST_DISK_IMG;
+
+/* Pointer to decompressed file image */
+static u8 *image;
+
+/* File info */
+static struct file_info priv_file_info = {
+ {
+ .size = sizeof(struct file_info),
+ .attribute = EFI_FILE_READ_ONLY,
+ },
+ FILE_NAME,
+};
+
+/* Pointer to file info */
+struct efi_file_info *file_info = &priv_file_info.info;
+
+/* Volume device path */
+static struct {
+ struct efi_device_path_vendor vendor;
+ struct efi_device_path end;
+} __packed dp_volume = {
+ .vendor = {
+ .dp = {
+ .type = DEVICE_PATH_TYPE_HARDWARE_DEVICE,
+ .sub_type = DEVICE_PATH_SUB_TYPE_VENDOR,
+ .length = sizeof(struct efi_device_path_vendor),
+ },
+ .guid = EFI_GUID(0x4f9a0ebf, 0xa179, 0x88a6, 0x25, 0x68,
+ 0x10, 0x72, 0xb1, 0x93, 0x51, 0x71),
+ },
+ .end = {
+ .type = DEVICE_PATH_TYPE_END,
+ .sub_type = DEVICE_PATH_SUB_TYPE_END,
+ .length = sizeof(struct efi_device_path),
+ }
+};
+
+/* File device path */
+static struct {
+ struct efi_device_path_vendor vendor;
+ struct efi_device_path path;
+ u16 file[sizeof(FILE_NAME)];
+ struct efi_device_path end;
+} __packed dp_file = {
+ .vendor = {
+ .dp = {
+ .type = DEVICE_PATH_TYPE_HARDWARE_DEVICE,
+ .sub_type = DEVICE_PATH_SUB_TYPE_VENDOR,
+ .length = sizeof(struct efi_device_path_vendor),
+ },
+ .guid = EFI_GUID(0x4f9a0ebf, 0xa179, 0x88a6, 0x25, 0x68,
+ 0x10, 0x72, 0xb1, 0x93, 0x51, 0x71),
+ },
+ .path = {
+ .type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+ .sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+ .length = sizeof(struct efi_device_path) + sizeof(dp_file.file),
+ },
+ .file = FILE_NAME,
+ .end = {
+ .type = DEVICE_PATH_TYPE_END,
+ .sub_type = DEVICE_PATH_SUB_TYPE_END,
+ .length = sizeof(struct efi_device_path),
+ }
+};
+
+/* File system info */
+static struct file_system_info priv_file_system_info = {
+ {
+ .size = sizeof(struct file_system_info),
+ .read_only = true,
+ .volume_size = 0x100000,
+ .free_space = 0x0,
+ .block_size = 0x200,
+ },
+ VOLUME_NAME
+};
+
+/* Pointer to file system info */
+static struct efi_file_system_info *file_system_info =
+ &priv_file_system_info.info;
+
+/* Forward definitions of file and file system functions */
+static efi_status_t EFIAPI open_volume
+ (struct efi_simple_file_system_protocol *this,
+ struct efi_file_handle **root);
+
+static efi_status_t EFIAPI open
+ (struct efi_file_handle *this,
+ struct efi_file_handle **new_handle,
+ u16 *file_name, u64 open_mode, u64 attributes);
+
+static efi_status_t EFIAPI close(struct efi_file_handle *this);
+
+static efi_status_t EFIAPI delete(struct efi_file_handle *this);
+
+static efi_status_t EFIAPI read
+ (struct efi_file_handle *this, efi_uintn_t *buffer_size, void *buffer);
+
+static efi_status_t EFIAPI write
+ (struct efi_file_handle *this, efi_uintn_t *buffer_size, void *buffer);
+
+static efi_status_t EFIAPI getpos(struct efi_file_handle *this, u64 *pos);
+
+static efi_status_t EFIAPI setpos(struct efi_file_handle *this, u64 pos);
+
+static efi_status_t EFIAPI getinfo
+ (struct efi_file_handle *this, const efi_guid_t *info_type,
+ efi_uintn_t *buffer_size, void *buffer);
+
+static efi_status_t EFIAPI setinfo
+ (struct efi_file_handle *this, const efi_guid_t *info_type,
+ efi_uintn_t buffer_size, void *buffer);
+
+static efi_status_t EFIAPI flush(struct efi_file_handle *this);
+
+/* Internal information about status of file system */
+static struct {
+ /* Difference of volume open count minus volume close count */
+ int volume_open_count;
+ /* Difference of file open count minus file close count */
+ int file_open_count;
+ /* File size */
+ u64 file_size;
+ /* Current position in file */
+ u64 file_pos;
+} priv;
+
+/* EFI_FILE_PROTOCOL for file */
+static struct efi_file_handle file = {
+ .rev = 0x00010000,
+ .open = open,
+ .close = close,
+ .delete = delete,
+ .read = read,
+ .write = write,
+ .getpos = getpos,
+ .setpos = setpos,
+ .getinfo = getinfo,
+ .setinfo = setinfo,
+ .flush = flush,
+};
+
+/* EFI_FILE_PROTOCOL for root directory */
+static struct efi_file_handle volume = {
+ .rev = 0x00010000,
+ .open = open,
+ .close = close,
+ .delete = delete,
+ .read = read,
+ .write = write,
+ .getpos = getpos,
+ .setpos = setpos,
+ .getinfo = getinfo,
+ .setinfo = setinfo,
+ .flush = flush,
+};
+
+/* EFI_SIMPLE_FILE_SYSTEM_PROTOCOL of the block device */
+struct efi_simple_file_system_protocol file_system = {
+ .rev = 0x00010000,
+ .open_volume = open_volume,
+};
+
+static efi_status_t EFIAPI open_volume
+ (struct efi_simple_file_system_protocol *this,
+ struct efi_file_handle **root)
+{
+ if (this != &file_system || !root)
+ return EFI_INVALID_PARAMETER;
+
+ *root = &volume;
+ priv.volume_open_count++;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI open
+ (struct efi_file_handle *this,
+ struct efi_file_handle **new_handle,
+ u16 *file_name, u64 open_mode, u64 attributes)
+{
+ if (this != &volume)
+ return EFI_INVALID_PARAMETER;
+
+ *new_handle = &file;
+ priv.file_pos = 0;
+ priv.file_open_count++;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI close(struct efi_file_handle *this)
+{
+ if (this == &file)
+ priv.file_open_count--;
+ else if (this == &volume)
+ priv.volume_open_count--;
+ else
+ return EFI_INVALID_PARAMETER;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI delete(struct efi_file_handle *this)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI read
+ (struct efi_file_handle *this, efi_uintn_t *buffer_size, void *buffer)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ if (priv.file_pos >= img.length)
+ *buffer_size = 0;
+ else if (priv.file_pos + *buffer_size > img.length)
+ *buffer_size = img.length - priv.file_pos;
+
+ boottime->copy_mem(buffer, &image[priv.file_pos], *buffer_size);
+ priv.file_pos += *buffer_size;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI write
+ (struct efi_file_handle *this, efi_uintn_t *buffer_size, void *buffer)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI getpos(struct efi_file_handle *this, u64 *pos)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ *pos = priv.file_pos;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI setpos(struct efi_file_handle *this, u64 pos)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ priv.file_pos = pos;
+
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI getinfo
+ (struct efi_file_handle *this, const efi_guid_t *info_type,
+ efi_uintn_t *buffer_size, void *buffer)
+{
+ if (this == &file) {
+ if (efi_st_memcmp(info_type, &guid_file_info,
+ sizeof(efi_guid_t)))
+ return EFI_INVALID_PARAMETER;
+ if (*buffer_size >= sizeof(struct file_info)) {
+ boottime->copy_mem(buffer, file_info,
+ sizeof(struct file_info));
+ } else {
+ *buffer_size = sizeof(struct file_info);
+ return EFI_BUFFER_TOO_SMALL;
+ }
+ } else if (this == &volume) {
+ if (efi_st_memcmp(info_type, &guid_file_system_info,
+ sizeof(efi_guid_t)))
+ return EFI_INVALID_PARAMETER;
+ if (*buffer_size >= sizeof(struct file_system_info)) {
+ boottime->copy_mem(buffer, file_system_info,
+ sizeof(struct file_system_info));
+ } else {
+ *buffer_size = sizeof(struct file_system_info);
+ return EFI_BUFFER_TOO_SMALL;
+ }
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+ return EFI_SUCCESS;
+}
+
+static efi_status_t EFIAPI setinfo
+ (struct efi_file_handle *this, const efi_guid_t *info_type,
+ efi_uintn_t buffer_size, void *buffer)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ return EFI_UNSUPPORTED;
+}
+
+static efi_status_t EFIAPI flush(struct efi_file_handle *this)
+{
+ if (this != &file)
+ return EFI_INVALID_PARAMETER;
+
+ return EFI_UNSUPPORTED;
+}
+
+/*
+ * Decompress the disk image.
+ *
+ * @image decompressed disk image
+ * @return status code
+ */
+static efi_status_t decompress(u8 **image)
+{
+ u8 *buf;
+ size_t i;
+ size_t addr;
+ size_t len;
+ efi_status_t ret;
+
+ ret = boottime->allocate_pool(EFI_LOADER_DATA, img.length,
+ (void **)&buf);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Out of memory\n");
+ return ret;
+ }
+ boottime->set_mem(buf, img.length, 0);
+
+ for (i = 0; ; ++i) {
+ if (!img.lines[i].line)
+ break;
+ addr = img.lines[i].addr;
+ len = COMPRESSED_DISK_IMAGE_BLOCK_SIZE;
+ if (addr + len > img.length)
+ len = img.length - addr;
+ boottime->copy_mem(buf + addr, img.lines[i].line, len);
+ }
+ *image = buf;
+ priv.file_size = img.length;
+ file_info->file_size = img.length;
+ return ret;
+}
+
+/*
+ * Setup unit test.
+ *
+ * Decompress application image and provide a handle for the in memory block
+ * device.
+ *
+ * @handle: handle of the loaded image
+ * @systable: system table
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int setup(const efi_handle_t handle,
+ const struct efi_system_table *systable)
+{
+ efi_status_t ret;
+
+ handle_image = handle;
+ boottime = systable->boottime;
+
+ /* Load the application image into memory */
+ decompress(&image);
+
+ ret = boottime->install_protocol_interface
+ (&handle_volume, &guid_device_path, EFI_NATIVE_INTERFACE,
+ &dp_volume);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to install device path\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->install_protocol_interface
+ (&handle_volume, &guid_simple_file_system_protocol,
+ EFI_NATIVE_INTERFACE, &file_system);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to install simple file system protocol\n");
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+/*
+ * Tear down unit test.
+ *
+ * Uninstall protocols and free memory.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int teardown(void)
+{
+ efi_status_t ret = EFI_ST_SUCCESS;
+
+ if (handle_volume) {
+ ret = boottime->uninstall_protocol_interface
+ (handle_volume, &guid_simple_file_system_protocol,
+ &file_system);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error
+ ("Failed to uninstall simple file system protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->uninstall_protocol_interface
+ (handle_volume, &guid_device_path, &dp_volume);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error
+ ("Failed to uninstall device path protocol\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+
+ if (image) {
+ ret = boottime->free_pool(image);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to free image\n");
+ return EFI_ST_FAILURE;
+ }
+ }
+ return ret;
+}
+
+/*
+ * Execute unit test.
+ *
+ * Load and start the application image.
+ *
+ * @return: EFI_ST_SUCCESS for success
+ */
+static int execute(void)
+{
+ efi_status_t ret;
+ efi_handle_t handle;
+
+ ret = boottime->load_image(false, handle_image, &dp_file.vendor.dp,
+ NULL, 0, &handle);
+ if (ret != EFI_SUCCESS) {
+ efi_st_error("Failed to load image\n");
+ return EFI_ST_FAILURE;
+ }
+ ret = boottime->start_image(handle, NULL, NULL);
+ if (ret != EFI_UNSUPPORTED) {
+ efi_st_error("Wrong return value from application\n");
+ return EFI_ST_FAILURE;
+ }
+
+ if (priv.file_open_count) {
+ efi_st_error("File open count = %d, expected 0\n",
+ priv.file_open_count);
+ return EFI_ST_FAILURE;
+ }
+ if (priv.volume_open_count) {
+ efi_st_error("Volume open count = %d, expected 0\n",
+ priv.volume_open_count);
+ return EFI_ST_FAILURE;
+ }
+
+ return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(loadimage) = {
+ .name = "load image from file",
+ .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
+ .setup = setup,
+ .execute = execute,
+ .teardown = teardown,
+};
efi_status_t r = EFI_ST_SUCCESS;
if (image) {
- r = efi_free_pool(image);
+ r = boottime->free_pool(image);
if (r != EFI_SUCCESS) {
efi_st_error("Failed to free image\n");
return EFI_ST_FAILURE;
efi_status_t r = EFI_ST_SUCCESS;
if (image) {
- r = efi_free_pool(image);
+ r = boottime->free_pool(image);
if (r != EFI_SUCCESS) {
efi_st_error("Failed to free image\n");
return EFI_ST_FAILURE;
uint32_t tpm_set_global_lock(struct udevice *dev)
{
- u32 x;
-
- return tpm_nv_write_value(dev, TPM_NV_INDEX_0, (uint8_t *)&x, 0);
+ return tpm_nv_write_value(dev, TPM_NV_INDEX_0, NULL, 0);
}
u32 tpm_extend(struct udevice *dev, u32 index, const void *in_digest,
for (i = 0; i < len && buf + utf16_utf8_strnlen(str, 1) <= end; ++i) {
s32 s = utf16_get(&str);
+ if (s < 0)
+ s = '?';
utf8_put(s, &buf);
}
for (; len < field_width; --field_width)
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
- cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ; \
+ sed -i "s:$(pre-tmp):$(<):" $(depfile)
$(obj)/%.dtb: $(src)/%.dts FORCE
$(call if_changed_dep,dtc)
# No generation of assembly file either
# Modified for U-Boot
cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \
- $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) - ; \
+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
$(DTC) -@ -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
CONFIG_FSL_I2C_CUSTOM_FDR
CONFIG_FSL_IIM
CONFIG_FSL_ISBC_KEY_EXT
-CONFIG_FSL_LAYERSCAPE
CONFIG_FSL_LBC
CONFIG_FSL_MC9SDZ60
CONFIG_FSL_MEMAC
CONFIG_FSL_SPI_INTERFACE
CONFIG_FSL_TBCLK_EXTRA_DIV
CONFIG_FSL_TRUST_ARCH_v1
-CONFIG_FSL_TZASC_400
-CONFIG_FSL_TZPC_BP147
CONFIG_FSL_USDHC
CONFIG_FSL_VIA
CONFIG_FSMC_NAND_BASE
CONFIG_SYS_I2C_SPEED3
CONFIG_SYS_I2C_TCA642X_ADDR
CONFIG_SYS_I2C_TCA642X_BUS_NUM
-CONFIG_SYS_I2C_TEGRA
CONFIG_SYS_I2C_W83782G_ADDR
CONFIG_SYS_IBAT
CONFIG_SYS_IBAT0L
CONFIG_SYS_OMAP24_I2C_SPEED2
CONFIG_SYS_OMAP24_I2C_SPEED3
CONFIG_SYS_OMAP24_I2C_SPEED4
-CONFIG_SYS_OMAP24_I2C_SPEED_PSOC
CONFIG_SYS_OMAP_ABE_SYSCK
CONFIG_SYS_ONENAND_BASE
CONFIG_SYS_ONENAND_BLOCK_SIZE
CONFIG_TEGRA_ENABLE_UARTD
CONFIG_TEGRA_ENABLE_UARTE
CONFIG_TEGRA_GPU
-CONFIG_TEGRA_KEYBOARD
CONFIG_TEGRA_LP0
CONFIG_TEGRA_NAND
CONFIG_TEGRA_PMU
CONFIG_USB_EHCI_MXC
CONFIG_USB_EHCI_MXS
CONFIG_USB_EHCI_SPEAR
-CONFIG_USB_EHCI_TEGRA
CONFIG_USB_EHCI_TXFIFO_THRESH
CONFIG_USB_EHCI_VCT
CONFIG_USB_EHCI_VF
CONFIG_ZLT
CONFIG_ZM7300
CONFIG_ZYNQMP_EEPROM
-CONFIG_ZYNQ_EEPROM
-CONFIG_ZYNQ_EEPROM_BUS
-CONFIG_ZYNQ_GEM_EEPROM_ADDR
CONFIG_ZYNQ_HISPD_BROKEN
-CONFIG_ZYNQ_SDHCI0
-CONFIG_ZYNQ_SDHCI1
CONFIG_eTSEC_MDIO_BUS
obj-$(CONFIG_OSD) += osd.o
obj-$(CONFIG_DM_VIDEO) += panel.o
obj-$(CONFIG_DM_PCI) += pci.o
+obj-$(CONFIG_PCH) += pch.o
obj-$(CONFIG_PHY) += phy.o
obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
obj-$(CONFIG_DM_PWM) += pwm.o
static int dm_test_clk(struct unit_test_state *uts)
{
- struct udevice *dev_fixed, *dev_clk, *dev_test;
+ struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
ulong rate;
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
&dev_fixed));
+ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
+ &dev_fixed_factor));
+
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
&dev_clk));
ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Test that sandbox PCH works correctly */
+static int dm_test_pch_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ u32 gbase, iobase;
+ ulong sbase;
+
+ ut_assertok(uclass_first_device_err(UCLASS_PCH, &dev));
+ ut_assertok(pch_get_spi_base(dev, &sbase));
+ ut_asserteq(0x10, sbase);
+
+ ut_asserteq(0, sandbox_get_pch_spi_protect(dev));
+ ut_assertok(pch_set_spi_protect(dev, true));
+ ut_asserteq(1, sandbox_get_pch_spi_protect(dev));
+
+ ut_assertok(pch_get_gpio_base(dev, &gbase));
+ ut_asserteq(0x20, gbase);
+
+ ut_assertok(pch_get_io_base(dev, &iobase));
+ ut_asserteq(0x30, iobase);
+
+ return 0;
+}
+DM_TEST(dm_test_pch_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test sandbox PCH ioctl */
+static int dm_test_pch_ioctl(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ char data;
+
+ ut_assertok(uclass_first_device_err(UCLASS_PCH, &dev));
+
+ ut_asserteq(-ENOSYS, pch_ioctl(dev, PCH_REQ_TEST1, NULL, 0));
+
+ ut_asserteq('a', pch_ioctl(dev, PCH_REQ_TEST2, "a", 1));
+
+ ut_asserteq(1, pch_ioctl(dev, PCH_REQ_TEST3, &data, 1));
+ ut_asserteq('x', data);
+
+ return 0;
+}
+DM_TEST(dm_test_pch_ioctl, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
return 0;
}
DM_TEST(dm_test_sound, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test of the 'start beep' operations */
+static int dm_test_sound_beep(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ /* check probe success */
+ ut_assertok(uclass_first_device_err(UCLASS_SOUND, &dev));
+ ut_asserteq(-ENOSYS, sound_start_beep(dev, 100));
+ ut_asserteq(0, sandbox_get_beep_frequency(dev));
+
+ sandbox_set_allow_beep(dev, true);
+ ut_asserteq(0, sound_start_beep(dev, 100));
+ ut_asserteq(100, sandbox_get_beep_frequency(dev));
+
+ ut_asserteq(0, sound_stop_beep(dev));
+ ut_asserteq(0, sandbox_get_beep_frequency(dev));
+
+ return 0;
+}
+DM_TEST(dm_test_sound_beep, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
mkdir_p(persistent_data_dir)
gdbserver = config.getoption('gdbserver')
- if gdbserver and board_type != 'sandbox':
- raise Exception('--gdbserver only supported with sandbox')
+ if gdbserver and not board_type.startswith('sandbox'):
+ raise Exception('--gdbserver only supported with sandbox targets')
import multiplexed_log
log = multiplexed_log.Logfile(result_dir + '/test-log.html')
static const char j2[] = {0x6a, 0x32, 0xc3, 0xc3, 0x6c, 0x00};
static const char j3[] = {0x6a, 0x33, 0xf0, 0x90, 0xf0, 0x00};
-static int ut_u16_strdup(struct unit_test_state *uts)
+static int unicode_test_u16_strdup(struct unit_test_state *uts)
{
u16 *copy = u16_strdup(c4);
free(copy);
return 0;
}
-UNICODE_TEST(ut_u16_strdup);
+UNICODE_TEST(unicode_test_u16_strdup);
-static int ut_u16_strcpy(struct unit_test_state *uts)
+static int unicode_test_u16_strcpy(struct unit_test_state *uts)
{
u16 *r;
u16 copy[10];
ut_assert(!memcmp(copy, c1, sizeof(c1)));
return 0;
}
-UNICODE_TEST(ut_u16_strcpy);
+UNICODE_TEST(unicode_test_u16_strcpy);
/* U-Boot uses UTF-16 strings in the EFI context only. */
#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
-static int ut_string16(struct unit_test_state *uts)
+static int unicode_test_string16(struct unit_test_state *uts)
{
char buf[20];
return 0;
}
-UNICODE_TEST(ut_string16);
+UNICODE_TEST(unicode_test_string16);
#endif
-static int ut_utf8_get(struct unit_test_state *uts)
+static int unicode_test_utf8_get(struct unit_test_state *uts)
{
const char *s;
s32 code;
return 0;
}
-UNICODE_TEST(ut_utf8_get);
+UNICODE_TEST(unicode_test_utf8_get);
-static int ut_utf8_put(struct unit_test_state *uts)
+static int unicode_test_utf8_put(struct unit_test_state *uts)
{
char buffer[8] = { 0, };
char *pos;
return 0;
}
-UNICODE_TEST(ut_utf8_put);
+UNICODE_TEST(unicode_test_utf8_put);
-static int ut_utf8_utf16_strlen(struct unit_test_state *uts)
+static int unicode_test_utf8_utf16_strlen(struct unit_test_state *uts)
{
ut_asserteq(6, utf8_utf16_strlen(d1));
ut_asserteq(8, utf8_utf16_strlen(d2));
return 0;
}
-UNICODE_TEST(ut_utf8_utf16_strlen);
+UNICODE_TEST(unicode_test_utf8_utf16_strlen);
-static int ut_utf8_utf16_strnlen(struct unit_test_state *uts)
+static int unicode_test_utf8_utf16_strnlen(struct unit_test_state *uts)
{
ut_asserteq(3, utf8_utf16_strnlen(d1, 3));
ut_asserteq(6, utf8_utf16_strnlen(d1, 13));
return 0;
}
-UNICODE_TEST(ut_utf8_utf16_strnlen);
+UNICODE_TEST(unicode_test_utf8_utf16_strnlen);
/**
* ut_u16_strcmp() - Compare to u16 strings.
* @count: number of u16 to compare
* Return: -1 if a1 < a2, 0 if a1 == a2, 1 if a1 > a2
*/
-static int ut_u16_strcmp(const u16 *a1, const u16 *a2, size_t count)
+static int unicode_test_u16_strcmp(const u16 *a1, const u16 *a2, size_t count)
{
for (; (*a1 || *a2) && count; ++a1, ++a2, --count) {
if (*a1 < *a2)
return 0;
}
-static int ut_utf8_utf16_strcpy(struct unit_test_state *uts)
+static int unicode_test_utf8_utf16_strcpy(struct unit_test_state *uts)
{
u16 buf[16];
u16 *pos;
pos = buf;
utf8_utf16_strcpy(&pos, d1);
ut_asserteq(6, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, c1, SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, c1, SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, d2);
ut_asserteq(8, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, c2, SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, c2, SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, d3);
ut_asserteq(3, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, c3, SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, c3, SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, d4);
ut_asserteq(6, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, c4, SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, c4, SIZE_MAX));
/* Illegal utf-8 strings */
pos = buf;
utf8_utf16_strcpy(&pos, j1);
ut_asserteq(4, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, L"j1?l", SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, L"j1?l", SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, j2);
ut_asserteq(4, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, L"j2?l", SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, L"j2?l", SIZE_MAX));
pos = buf;
utf8_utf16_strcpy(&pos, j3);
ut_asserteq(3, pos - buf);
- ut_assert(!ut_u16_strcmp(buf, L"j3?", SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, L"j3?", SIZE_MAX));
return 0;
}
-UNICODE_TEST(ut_utf8_utf16_strcpy);
+UNICODE_TEST(unicode_test_utf8_utf16_strcpy);
-int ut_utf8_utf16_strncpy(struct unit_test_state *uts)
+static int unicode_test_utf8_utf16_strncpy(struct unit_test_state *uts)
{
u16 buf[16];
u16 *pos;
utf8_utf16_strncpy(&pos, d1, 4);
ut_asserteq(4, pos - buf);
ut_assert(!buf[4]);
- ut_assert(!ut_u16_strcmp(buf, c1, 4));
+ ut_assert(!unicode_test_u16_strcmp(buf, c1, 4));
pos = buf;
memset(buf, 0, sizeof(buf));
utf8_utf16_strncpy(&pos, d2, 10);
ut_asserteq(8, pos - buf);
ut_assert(buf[4]);
- ut_assert(!ut_u16_strcmp(buf, c2, SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, c2, SIZE_MAX));
pos = buf;
memset(buf, 0, sizeof(buf));
utf8_utf16_strncpy(&pos, d3, 2);
ut_asserteq(2, pos - buf);
ut_assert(!buf[2]);
- ut_assert(!ut_u16_strcmp(buf, c3, 2));
+ ut_assert(!unicode_test_u16_strcmp(buf, c3, 2));
pos = buf;
memset(buf, 0, sizeof(buf));
utf8_utf16_strncpy(&pos, d4, 2);
ut_asserteq(4, pos - buf);
ut_assert(!buf[4]);
- ut_assert(!ut_u16_strcmp(buf, c4, 4));
+ ut_assert(!unicode_test_u16_strcmp(buf, c4, 4));
pos = buf;
memset(buf, 0, sizeof(buf));
utf8_utf16_strncpy(&pos, d4, 10);
ut_asserteq(6, pos - buf);
ut_assert(buf[5]);
- ut_assert(!ut_u16_strcmp(buf, c4, SIZE_MAX));
+ ut_assert(!unicode_test_u16_strcmp(buf, c4, SIZE_MAX));
return 0;
}
-UNICODE_TEST(ut_utf8_utf16_strncpy);
+UNICODE_TEST(unicode_test_utf8_utf16_strncpy);
-static int ut_utf16_get(struct unit_test_state *uts)
+static int unicode_test_utf16_get(struct unit_test_state *uts)
{
const u16 *s;
s32 code;
return 0;
}
-UNICODE_TEST(ut_utf16_get);
+UNICODE_TEST(unicode_test_utf16_get);
-static int ut_utf16_put(struct unit_test_state *uts)
+static int unicode_test_utf16_put(struct unit_test_state *uts)
{
u16 buffer[4] = { 0, };
u16 *pos;
return 0;
}
-UNICODE_TEST(ut_utf16_put);
+UNICODE_TEST(unicode_test_utf16_put);
-int ut_utf16_strnlen(struct unit_test_state *uts)
+static int unicode_test_utf16_strnlen(struct unit_test_state *uts)
{
ut_asserteq(3, utf16_strnlen(c1, 3));
ut_asserteq(6, utf16_strnlen(c1, 13));
return 0;
}
-UNICODE_TEST(ut_utf16_strnlen);
+UNICODE_TEST(unicode_test_utf16_strnlen);
-int ut_utf16_utf8_strlen(struct unit_test_state *uts)
+static int unicode_test_utf16_utf8_strlen(struct unit_test_state *uts)
{
ut_asserteq(6, utf16_utf8_strlen(c1));
ut_asserteq(9, utf16_utf8_strlen(c2));
return 0;
}
-UNICODE_TEST(ut_utf16_utf8_strlen);
+UNICODE_TEST(unicode_test_utf16_utf8_strlen);
-int ut_utf16_utf8_strnlen(struct unit_test_state *uts)
+static int unicode_test_utf16_utf8_strnlen(struct unit_test_state *uts)
{
ut_asserteq(3, utf16_utf8_strnlen(c1, 3));
ut_asserteq(6, utf16_utf8_strnlen(c1, 13));
ut_asserteq(12, utf16_utf8_strnlen(c4, 3));
return 0;
}
-UNICODE_TEST(ut_utf16_utf8_strnlen);
+UNICODE_TEST(unicode_test_utf16_utf8_strnlen);
-int ut_utf16_utf8_strcpy(struct unit_test_state *uts)
+static int unicode_test_utf16_utf8_strcpy(struct unit_test_state *uts)
{
char buf[16];
char *pos;
return 0;
}
-UNICODE_TEST(ut_utf16_utf8_strcpy);
+UNICODE_TEST(unicode_test_utf16_utf8_strcpy);
-int ut_utf16_utf8_strncpy(struct unit_test_state *uts)
+static int unicode_test_utf16_utf8_strncpy(struct unit_test_state *uts)
{
char buf[16];
char *pos;
return 0;
}
-UNICODE_TEST(ut_utf16_utf8_strncpy);
+UNICODE_TEST(unicode_test_utf16_utf8_strncpy);
-int ut_utf_to_lower(struct unit_test_state *uts)
+static int unicode_test_utf_to_lower(struct unit_test_state *uts)
{
ut_asserteq('@', utf_to_lower('@'));
ut_asserteq('a', utf_to_lower('A'));
#endif
return 0;
}
-UNICODE_TEST(ut_utf_to_lower);
+UNICODE_TEST(unicode_test_utf_to_lower);
-int ut_utf_to_upper(struct unit_test_state *uts)
+static int unicode_test_utf_to_upper(struct unit_test_state *uts)
{
ut_asserteq('`', utf_to_upper('`'));
ut_asserteq('A', utf_to_upper('a'));
#endif
return 0;
}
-UNICODE_TEST(ut_utf_to_upper);
+UNICODE_TEST(unicode_test_utf_to_upper);
int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
projects / oweals / u-boot.git / commitdiff