#define ZYNQ_SCU_BASEADDR 0xF8F00000
#define ZYNQ_GEM_BASEADDR0 0xE000B000
#define ZYNQ_GEM_BASEADDR1 0xE000C000
-#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
-#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
return ret;
}
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bd)
-{
- int ret = 0;
-
-#if defined(CONFIG_ZYNQ_SDHCI)
-# if defined(CONFIG_ZYNQ_SDHCI0)
- ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_SDHCI1)
- ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
-# endif
-#endif
- return ret;
-}
-#endif
-
int dram_init(void)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
}
#endif
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bd)
-{
- int ret = 0;
-
- u32 ver = zynqmp_get_silicon_version();
-
- if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
-#if defined(CONFIG_ZYNQ_SDHCI)
-# if defined(CONFIG_ZYNQ_SDHCI0)
- ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_SDHCI1)
- ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
-# endif
-#endif
- }
-
- return ret;
-}
-#endif
-
int board_late_init(void)
{
u32 reg = 0;
/*
- * (C) Copyright 2013 Inc.
+ * (C) Copyright 2013 - 2015 Xilinx, Inc.
*
* Xilinx Zynq SD Host Controller Interface
*
*/
#include <common.h>
+#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <malloc.h>
#include <sdhci.h>
-#include <asm/arch/sys_proto.h>
-int zynq_sdhci_init(phys_addr_t regbase)
+static int arasan_sdhci_probe(struct udevice *dev)
{
- struct sdhci_host *host = NULL;
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
- host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
- if (!host) {
- printf("zynq_sdhci_init: sdhci_host malloc fail\n");
- return 1;
- }
-
- host->name = "zynq_sdhci";
- host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 0);
+
+ upriv->mmc = host->mmc;
+
return 0;
}
+
+static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
+{
+ struct sdhci_host *host = dev_get_priv(dev);
+
+ host->name = (char *)dev->name;
+ host->ioaddr = (void *)dev_get_addr(dev);
+
+ return 0;
+}
+
+static const struct udevice_id arasan_sdhci_ids[] = {
+ { .compatible = "arasan,sdhci-8.9a" },
+ { }
+};
+
+U_BOOT_DRIVER(arasan_sdhci_drv) = {
+ .name = "arasan_sdhci",
+ .id = UCLASS_MMC,
+ .of_match = arasan_sdhci_ids,
+ .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
+ .probe = arasan_sdhci_probe,
+ .priv_auto_alloc_size = sizeof(struct sdhci_host),
+};