new boards should not use this option.
config SYS_TEXT_BASE
- depends on SPARC || ARC
+ depends on SPARC || ARC || X86
hex "Text Base"
help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
boot. See the documentation file README.video for a
description of this variable.
- CONFIG_VIDEO_VGA
-
- Enable the VGA video / BIOS for x86. The alternative if you
- are using coreboot is to use the coreboot frame buffer
- driver.
-
- Keyboard Support:
CONFIG_KEYBOARD
select DM
select DM_SERIAL
select DM_GPIO
+ select DM_SPI
+ select DM_SPI_FLASH
endchoice
bool "Marvell Kirkwood"
select CPU_ARM926EJS
+config TARGET_DB_88F6820_GP
+ bool "Support DB-88F6820-GP"
+ select CPU_V7
+ select SUPPORT_SPL
+
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select CPU_V7
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
+ select DM
+ select DM_GPIO
+ select OF_CONTROL
+ select OF_SEPARATE
+ select SPL_DISABLE_OF_CONTROL
config TARGET_SNOWBALL
bool "Support snowball"
source "board/BuR/tseries/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-88f6820-gp/Kconfig"
source "board/Marvell/db-mv784mp-gp/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/altera/socfpga/Kconfig"
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
# TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
machine-$(CONFIG_KIRKWOOD) += kirkwood
+machine-$(CONFIG_ARMADA_XP) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
endif
endif
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
-libs-y += arch/arm/mvebu-common/
+ifneq (,$(filter $(SOC), kirkwood))
+libs-y += arch/arm/mach-mvebu/
endif
# deprecated
endif
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
-obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
+++ /dev/null
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = cpu.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+++ /dev/null
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
-
-static struct mbus_win windows[] = {
- /* PCIE MEM address space */
- { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
-
- /* PCIE IO address space */
- { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
-
- /* SPI */
- { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_SPIFLASH },
-
- /* NOR */
- { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
- CPU_ATTR_BOOTROM },
-};
-
-void reset_cpu(unsigned long ignored)
-{
- struct mvebu_system_registers *reg =
- (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
-
- writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
- writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
- while (1)
- ;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
- u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
- u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
-
- puts("SoC: ");
-
- switch (devid) {
- case SOC_MV78460_ID:
- puts("MV78460-");
- break;
- default:
- puts("Unknown-");
- break;
- }
-
- switch (revid) {
- case 1:
- puts("A0\n");
- break;
- case 2:
- puts("B0\n");
- break;
- default:
- puts("??\n");
- break;
- }
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-/*
- * This function initialize Controller DRAM Fastpath windows.
- * It takes the CS size information from the 0x1500 scratch registers
- * and sets the correct windows sizes and base addresses accordingly.
- *
- * These values are set in the scratch registers by the Marvell
- * DDR3 training code, which is executed by the BootROM before the
- * main payload (U-Boot) is executed. This training code is currently
- * only available in the Marvell U-Boot version. It needs to be
- * ported to mainline U-Boot SPL at some point.
- */
-static void update_sdram_window_sizes(void)
-{
- u64 base = 0;
- u32 size, temp;
- int i;
-
- for (i = 0; i < SDRAM_MAX_CS; i++) {
- size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
- if (size != 0) {
- size |= ~(SDRAM_ADDR_MASK);
-
- /* Set Base Address */
- temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
- writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
-
- /*
- * Check if out of max window size and resize
- * the window
- */
- temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
- ~(SDRAM_ADDR_MASK)) | 1;
- temp |= (size & SDRAM_ADDR_MASK);
- writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
-
- base += ((u64)size + 1);
- } else {
- /*
- * Disable window if not used, otherwise this
- * leads to overlapping enabled windows with
- * pretty strange results
- */
- clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
- }
- }
-}
-
-#ifdef CONFIG_ARCH_CPU_INIT
-int arch_cpu_init(void)
-{
- /* Linux expects the internal registers to be at 0xf1000000 */
- writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
-
- /*
- * We need to call mvebu_mbus_probe() before calling
- * update_sdram_window_sizes() as it disables all previously
- * configured mbus windows and then configures them as
- * required for U-Boot. Calling update_sdram_window_sizes()
- * without this configuration will not work, as the internal
- * registers can't be accessed reliably because of potenial
- * double mapping.
- * After updating the SDRAM access windows we need to call
- * mvebu_mbus_probe() again, as this now correctly configures
- * the SDRAM areas that are later used by the MVEBU drivers
- * (e.g. USB, NETA).
- */
-
- /*
- * First disable all windows
- */
- mvebu_mbus_probe(NULL, 0);
-
- /*
- * Now the SDRAM access windows can be reconfigured using
- * the information in the SDRAM scratch pad registers
- */
- update_sdram_window_sizes();
-
- /*
- * Finally the mbus windows can be configured with the
- * updated SDRAM sizes
- */
- mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
-
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-/*
- * SOC specific misc init
- */
-#if defined(CONFIG_ARCH_MISC_INIT)
-int arch_misc_init(void)
-{
- /* Nothing yet, perhaps we need something here later */
- return 0;
-}
-#endif /* CONFIG_ARCH_MISC_INIT */
-
-#ifdef CONFIG_MVNETA
-int cpu_eth_init(bd_t *bis)
-{
- mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
- mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
- mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
- mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
-
- return 0;
-}
-#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
+++ /dev/null
-/*
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(save_boot_params)
- b save_boot_params_ret
-ENDPROC(save_boot_params)
-
-/*
- * cache_inv - invalidate Cache line
- * r0 - dest
- */
- .global cache_inv
- .type cache_inv, %function
- cache_inv:
-
- stmfd sp!, {r1-r12}
-
- mcr p15, 0, r0, c7, c6, 1
-
- ldmfd sp!, {r1-r12}
- bx lr
-
-
-/*
- * flush_l1_v6 - l1 cache clean invalidate
- * r0 - dest
- */
- .global flush_l1_v6
- .type flush_l1_v6, %function
- flush_l1_v6:
-
- stmfd sp!, {r1-r12}
-
- mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
- mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
- mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
-
- ldmfd sp!, {r1-r12}
- bx lr
-
-
-/*
- * flush_l1_v7 - l1 cache clean invalidate
- * r0 - dest
- */
- .global flush_l1_v7
- .type flush_l1_v7, %function
- flush_l1_v7:
-
- stmfd sp!, {r1-r12}
-
- dmb /* @data memory barrier */
- mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
- dsb /* @data sync barrier */
-
- ldmfd sp!, {r1-r12}
- bx lr
+++ /dev/null
-/*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
- /* Right now only booting via SPI NOR flash is supported */
- return BOOT_DEVICE_SPI;
-}
-
-void board_init_f(ulong dummy)
-{
- /* Set global data pointer */
- gd = &gdata;
-
- /* Linux expects the internal registers to be at 0xf1000000 */
- arch_cpu_init();
-
- preloader_console_init();
-
- /* First init the serdes PHY's */
- serdes_phy_config();
-
- /* Setup DDR */
- ddr3_init();
-
- board_init_r(NULL, 0);
-}
}
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ DSB;
}
static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
}
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ DSB;
}
static void v7_maint_dcache_level_setway(u32 level, u32 operation)
}
/* DSB to make sure the operation is complete */
- CP15DSB;
+ DSB;
}
/* Invalidate TLB */
/* Invalidate entire instruction TLB */
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
+ DSB;
/* Full system ISB - make sure the instruction stream sees it */
- CP15ISB;
+ ISB;
}
void invalidate_dcache_all(void)
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- CP15DSB;
+ DSB;
/* ISB - make sure the instruction stream sees it */
- CP15ISB;
+ ISB;
}
#else
void invalidate_icache_all(void)
obj-y += cpu_info.o
obj-y += dram_helpers.o
obj-y += pinmux.o
-obj-y += usbc.o
+obj-y += usb_phy.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
+obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
+obj-$(CONFIG_AXP221_POWER) += pmic_bus.o
+
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_ARMV7_PSCI
obj-y += psci.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
+obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o
+obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o
obj-y += fel_utils.o
endif
#include <common.h>
#include <i2c.h>
-#include <netdev.h>
-#include <miiphy.h>
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
void s_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
+#if defined CONFIG_MACH_SUN6I || \
+ defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN8I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
void reset_cpu(ulong addr)
{
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_SUNXI_GEN_SUN4I
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
mdelay(200);
#endif
-#ifdef CONFIG_SUNXI_EMAC
- rc = sunxi_emac_initialize(bis);
- if (rc < 0) {
- printf("sunxi: failed to initialize emac\n");
- return rc;
- }
-#endif
-
#ifdef CONFIG_SUNXI_GMAC
rc = sunxi_gmac_initialize(bis);
if (rc < 0) {
udelay(5500);
}
+#ifdef CONFIG_MACH_SUN8I_A33
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ if (sigma_delta_enable)
+ writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
+
+ writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
+ (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
+ CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
+
+ while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
+ ;
+}
+#endif
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
}
#elif defined CONFIG_MACH_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
-#elif defined CONFIG_MACH_SUN8I
+#elif defined CONFIG_MACH_SUN8I_A23
puts("CPU: Allwinner A23 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN8I_A33
+ puts("CPU: Allwinner A33 (SUN8I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
int sunxi_get_sid(unsigned int *sid)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
#ifdef CONFIG_AXP221_POWER
return axp221_get_sid(sid);
#else
+++ /dev/null
-/*
- * Sun8i platform dram controller init.
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * Note this code uses a lot of magic hex values, that is because this code
- * simply replays the init sequence as done by the Allwinner boot0 code, so
- * we do not know what these values mean. There are no symbolic constants for
- * these magic values, since we do not know how to name them and making up
- * names for them is not useful.
- *
- * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
- * found in the TI Keystone2 documentation:
- * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
- * "Table4-2 DDR3 PHY Registers"
- * This may be used as a (possible) reference for future work / cleanups.
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dram.h>
-#include <asm/arch/prcm.h>
-
-static const struct dram_para dram_para = {
- .clock = CONFIG_DRAM_CLK,
- .type = 3,
- .zq = CONFIG_DRAM_ZQ,
- .odt_en = 1,
- .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
- .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
- .mr0 = 6736,
- .mr1 = 4,
- .mr2 = 16,
- .mr3 = 0,
- /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
- .tpr0 = 0x2ab83def,
- .tpr1 = 0x18082356,
- .tpr2 = 0x00034156,
- .tpr3 = 0x448c5533,
- .tpr4 = 0x08010d00,
- .tpr5 = 0x0340b20f,
- .tpr6 = 0x20d118cc,
- .tpr7 = 0x14062485,
- .tpr8 = 0x220d1d52,
- .tpr9 = 0x1e078c22,
- .tpr10 = 0x3c,
- .tpr11 = 0, /* not used */
- .tpr12 = 0, /* not used */
- .tpr13 = 0x30000,
-};
-
-static void mctl_sys_init(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* enable pll5, note the divide by 2 is deliberate! */
- clock_set_pll5(dram_para.clock * 1000000 / 2,
- dram_para.tpr13 & 0x40000);
-
- /* deassert ahb mctl reset */
- setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
-
- /* enable ahb mctl clock */
- setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
-}
-
-static void mctl_apply_odt_correction(u32 *reg, int correction)
-{
- int val;
-
- val = (readl(reg) >> 8) & 0xff;
- val += correction;
-
- /* clamp */
- if (val < 0)
- val = 0;
- else if (val > 255)
- val = 255;
-
- clrsetbits_le32(reg, 0xff00, val << 8);
-}
-
-static void mctl_init(u32 *bus_width)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- struct sunxi_mctl_ctl_reg * const mctl_ctl =
- (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
- struct sunxi_mctl_phy_reg * const mctl_phy =
- (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
- int correction;
-
- if (dram_para.tpr13 & 0x20)
- writel(0x40b, &mctl_phy->dcr);
- else
- writel(0x1000040b, &mctl_phy->dcr);
-
- if (dram_para.clock >= 480)
- writel(0x5c000, &mctl_phy->dllgcr);
- else
- writel(0xdc000, &mctl_phy->dllgcr);
-
- writel(0x0a003e3f, &mctl_phy->pgcr0);
- writel(0x03008421, &mctl_phy->pgcr1);
-
- writel(dram_para.mr0, &mctl_phy->mr0);
- writel(dram_para.mr1, &mctl_phy->mr1);
- writel(dram_para.mr2, &mctl_phy->mr2);
- writel(dram_para.mr3, &mctl_phy->mr3);
-
- if (!(dram_para.tpr13 & 0x10000)) {
- clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
- clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
- }
-
- /*
- * All the masking and shifting below converts what I assume are DDR
- * timing constants from Allwinner dram_para tpr format to the actual
- * timing registers format.
- */
-
- writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
- writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
- writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
- (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
-
- writel(dram_para.tpr3, &mctl_phy->dtpr0);
- writel(dram_para.tpr4, &mctl_phy->dtpr2);
-
- writel(0x01000081, &mctl_phy->dtcr);
-
- if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) {
- clrbits_le32(&mctl_phy->dx0gcr, 0x600);
- clrbits_le32(&mctl_phy->dx1gcr, 0x600);
- }
- if (dram_para.clock <= 240) {
- writel(0, &mctl_phy->odtcr);
- writel(0, &mctl_ctl->odtmap);
- }
-
- writel(((dram_para.tpr5 & 0x0f00) << 12) |
- ((dram_para.tpr5 & 0x00f8) << 9) |
- ((dram_para.tpr5 & 0x0007) << 8),
- &mctl_ctl->rfshctl0);
-
- writel(((dram_para.tpr5 & 0x0003f000) << 12) |
- ((dram_para.tpr5 & 0x00fc0000) >> 2) |
- ((dram_para.tpr5 & 0x3f000000) >> 16) |
- ((dram_para.tpr6 & 0x0000003f) >> 0),
- &mctl_ctl->dramtmg0);
-
- writel(((dram_para.tpr6 & 0x000007c0) << 10) |
- ((dram_para.tpr6 & 0x0000f800) >> 3) |
- ((dram_para.tpr6 & 0x003f0000) >> 16),
- &mctl_ctl->dramtmg1);
-
- writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
- ((dram_para.tpr7 & 0x0000001f) << 16) |
- ((dram_para.tpr7 & 0x000003e0) << 3) |
- ((dram_para.tpr7 & 0x0000fc00) >> 10),
- &mctl_ctl->dramtmg2);
-
- writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
- ((dram_para.tpr6 & 0xf0000000) >> 16),
- &mctl_ctl->dramtmg3);
-
- writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
- ((dram_para.tpr8 & 0x00000007) << 16) |
- ((dram_para.tpr8 & 0x00000038) << 5) |
- ((dram_para.tpr8 & 0x000003c0) >> 6),
- &mctl_ctl->dramtmg4);
-
- writel(((dram_para.tpr8 & 0x00003c00) << 14) |
- ((dram_para.tpr8 & 0x0003c000) << 2) |
- ((dram_para.tpr8 & 0x00fc0000) >> 10) |
- ((dram_para.tpr8 & 0x0f000000) >> 24),
- &mctl_ctl->dramtmg5);
-
- writel(0x00000008, &mctl_ctl->dramtmg8);
-
- writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
- ((dram_para.tpr9 & 0x00007c00) << 6) |
- ((dram_para.tpr9 & 0x000003e0) << 3) |
- ((dram_para.tpr9 & 0x0000001f) >> 0),
- &mctl_ctl->pitmg0);
-
- setbits_le32(&mctl_ctl->pitmg1, 0x80000);
-
- writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
- &mctl_ctl->sched);
-
- writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
- writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
-
- writel(0x00000000, &mctl_ctl->pimisc);
- writel(0x80000000, &mctl_ctl->upd0);
-
- writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
- ((dram_para.tpr10 & 0x00000fff) << 16),
- &mctl_ctl->rfshtmg);
-
- if (dram_para.tpr13 & 0x20)
- writel(0x01040001, &mctl_ctl->mstr);
- else
- writel(0x01040401, &mctl_ctl->mstr);
-
- if (!(dram_para.tpr13 & 0x20000)) {
- writel(0x00000002, &mctl_ctl->pwrctl);
- writel(0x00008001, &mctl_ctl->pwrtmg);
- }
-
- writel(0x00000001, &mctl_ctl->rfshctl3);
- writel(0x00000001, &mctl_ctl->pimisc);
-
- /* deassert dram_clk_cfg reset */
- setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
-
- setbits_le32(&mctl_com->ccr, 0x80000);
-
- /* zq stuff */
- writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
-
- writel(0x00000003, &mctl_phy->pir);
- udelay(10);
- mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
-
- writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
- writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
-
- /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
- writel(0x000005f3, &mctl_phy->pir);
- udelay(10);
- mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
-
- if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
- *bus_width = 8;
- writel(0, &mctl_phy->dx1gcr);
- writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
- writel(0x5f3, &mctl_phy->pir);
- udelay(10000);
- setbits_le32(&mctl_ctl->mstr, 0x1000);
- } else
- *bus_width = 16;
-
- correction = (dram_para.odt_en >> 8) & 0xff;
- if (correction) {
- if (dram_para.odt_en & 0x80000000)
- correction = -correction;
-
- mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction);
- mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction);
- }
-
- mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
-
- writel(0x08003e3f, &mctl_phy->pgcr0);
- writel(0x00000000, &mctl_ctl->rfshctl3);
-}
-
-unsigned long sunxi_dram_init(void)
-{
- struct sunxi_mctl_com_reg * const mctl_com =
- (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
- const u32 columns = 13;
- u32 bus, bus_width, offset, page_size, rows;
-
- mctl_sys_init();
- mctl_init(&bus_width);
-
- if (bus_width == 16) {
- page_size = 8;
- bus = 1;
- } else {
- page_size = 7;
- bus = 0;
- }
-
- if (!(dram_para.tpr13 & 0x80000000)) {
- /* Detect and set rows */
- writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
- &mctl_com->cr);
- setbits_le32(&mctl_com->swonr, 0x0003ffff);
- for (rows = 11; rows < 16; rows++) {
- offset = 1 << (rows + columns + bus);
- if (mctl_mem_matches(offset))
- break;
- }
- clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
- MCTL_CR_ROW(rows));
- } else {
- rows = (dram_para.para1 >> 16) & 0xff;
- writel(((dram_para.para2 & 0x000000f0) << 11) |
- ((rows - 1) << 4) |
- ((dram_para.para1 & 0x0f000000) >> 22) |
- 0x31000 | MCTL_CR_PAGE_SIZE(page_size),
- &mctl_com->cr);
- setbits_le32(&mctl_com->swonr, 0x0003ffff);
- }
-
- /* Setup DRAM master priority? If this is left out things still work */
- writel(0x00000008, &mctl_com->mcr0_0);
- writel(0x0001000d, &mctl_com->mcr1_0);
- writel(0x00000004, &mctl_com->mcr0_1);
- writel(0x00000080, &mctl_com->mcr1_1);
- writel(0x00000004, &mctl_com->mcr0_2);
- writel(0x00000019, &mctl_com->mcr1_2);
- writel(0x00000004, &mctl_com->mcr0_3);
- writel(0x00000080, &mctl_com->mcr1_3);
- writel(0x00000004, &mctl_com->mcr0_4);
- writel(0x01010040, &mctl_com->mcr1_4);
- writel(0x00000004, &mctl_com->mcr0_5);
- writel(0x0001002f, &mctl_com->mcr1_5);
- writel(0x00000004, &mctl_com->mcr0_6);
- writel(0x00010020, &mctl_com->mcr1_6);
- writel(0x00000004, &mctl_com->mcr0_7);
- writel(0x00010020, &mctl_com->mcr1_7);
- writel(0x00000008, &mctl_com->mcr0_8);
- writel(0x00000001, &mctl_com->mcr1_8);
- writel(0x00000008, &mctl_com->mcr0_9);
- writel(0x00000005, &mctl_com->mcr1_9);
- writel(0x00000008, &mctl_com->mcr0_10);
- writel(0x00000003, &mctl_com->mcr1_10);
- writel(0x00000008, &mctl_com->mcr0_11);
- writel(0x00000005, &mctl_com->mcr1_11);
- writel(0x00000008, &mctl_com->mcr0_12);
- writel(0x00000003, &mctl_com->mcr1_12);
- writel(0x00000008, &mctl_com->mcr0_13);
- writel(0x00000004, &mctl_com->mcr1_13);
- writel(0x00000008, &mctl_com->mcr0_14);
- writel(0x00000002, &mctl_com->mcr1_14);
- writel(0x00000008, &mctl_com->mcr0_15);
- writel(0x00000003, &mctl_com->mcr1_15);
- writel(0x00010138, &mctl_com->bwcr);
-
- return 1 << (rows + columns + bus);
-}
--- /dev/null
+/*
+ * Sun8i platform dram controller init.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Note this code uses a lot of magic hex values, that is because this code
+ * simply replays the init sequence as done by the Allwinner boot0 code, so
+ * we do not know what these values mean. There are no symbolic constants for
+ * these magic values, since we do not know how to name them and making up
+ * names for them is not useful.
+ *
+ * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one
+ * found in the TI Keystone2 documentation:
+ * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf
+ * "Table4-2 DDR3 PHY Registers"
+ * This may be used as a (possible) reference for future work / cleanups.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+static const struct dram_para dram_para = {
+ .clock = CONFIG_DRAM_CLK,
+ .type = 3,
+ .zq = CONFIG_DRAM_ZQ,
+ .odt_en = 1,
+ .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
+ .mr0 = 6736,
+ .mr1 = 4,
+ .mr2 = 16,
+ .mr3 = 0,
+ /* tpr0 - 10 contain timing constants or-ed together in u32 vals */
+ .tpr0 = 0x2ab83def,
+ .tpr1 = 0x18082356,
+ .tpr2 = 0x00034156,
+ .tpr3 = 0x448c5533,
+ .tpr4 = 0x08010d00,
+ .tpr5 = 0x0340b20f,
+ .tpr6 = 0x20d118cc,
+ .tpr7 = 0x14062485,
+ .tpr8 = 0x220d1d52,
+ .tpr9 = 0x1e078c22,
+ .tpr10 = 0x3c,
+ .tpr11 = 0, /* not used */
+ .tpr12 = 0, /* not used */
+ .tpr13 = 0x30000,
+};
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable pll5, note the divide by 2 is deliberate! */
+ clock_set_pll5(dram_para.clock * 1000000 / 2,
+ dram_para.tpr13 & 0x40000);
+
+ /* deassert ahb mctl reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+ /* enable ahb mctl clock */
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_apply_odt_correction(u32 *reg, int correction)
+{
+ int val;
+
+ val = (readl(reg) >> 8) & 0xff;
+ val += correction;
+
+ /* clamp */
+ if (val < 0)
+ val = 0;
+ else if (val > 255)
+ val = 255;
+
+ clrsetbits_le32(reg, 0xff00, val << 8);
+}
+
+static void mctl_init(u32 *bus_width)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ int correction;
+
+ if (dram_para.tpr13 & 0x20)
+ writel(0x40b, &mctl_phy->dcr);
+ else
+ writel(0x1000040b, &mctl_phy->dcr);
+
+ if (dram_para.clock >= 480)
+ writel(0x5c000, &mctl_phy->dllgcr);
+ else
+ writel(0xdc000, &mctl_phy->dllgcr);
+
+ writel(0x0a003e3f, &mctl_phy->pgcr0);
+ writel(0x03008421, &mctl_phy->pgcr1);
+
+ writel(dram_para.mr0, &mctl_phy->mr0);
+ writel(dram_para.mr1, &mctl_phy->mr1);
+ writel(dram_para.mr2, &mctl_phy->mr2);
+ writel(dram_para.mr3, &mctl_phy->mr3);
+
+ if (!(dram_para.tpr13 & 0x10000)) {
+ clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000);
+ clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000);
+ }
+
+ /*
+ * All the masking and shifting below converts what I assume are DDR
+ * timing constants from Allwinner dram_para tpr format to the actual
+ * timing registers format.
+ */
+
+ writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2);
+ writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3);
+ writel((dram_para.tpr0 & 0x3ff00000) >> 2 |
+ (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4);
+
+ writel(dram_para.tpr3, &mctl_phy->dtpr0);
+ writel(dram_para.tpr4, &mctl_phy->dtpr2);
+
+ writel(0x01000081, &mctl_phy->dtcr);
+
+ if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) {
+ clrbits_le32(&mctl_phy->dx0gcr, 0x600);
+ clrbits_le32(&mctl_phy->dx1gcr, 0x600);
+ }
+ if (dram_para.clock <= 240) {
+ writel(0, &mctl_phy->odtcr);
+ writel(0, &mctl_ctl->odtmap);
+ }
+
+ writel(((dram_para.tpr5 & 0x0f00) << 12) |
+ ((dram_para.tpr5 & 0x00f8) << 9) |
+ ((dram_para.tpr5 & 0x0007) << 8),
+ &mctl_ctl->rfshctl0);
+
+ writel(((dram_para.tpr5 & 0x0003f000) << 12) |
+ ((dram_para.tpr5 & 0x00fc0000) >> 2) |
+ ((dram_para.tpr5 & 0x3f000000) >> 16) |
+ ((dram_para.tpr6 & 0x0000003f) >> 0),
+ &mctl_ctl->dramtmg0);
+
+ writel(((dram_para.tpr6 & 0x000007c0) << 10) |
+ ((dram_para.tpr6 & 0x0000f800) >> 3) |
+ ((dram_para.tpr6 & 0x003f0000) >> 16),
+ &mctl_ctl->dramtmg1);
+
+ writel(((dram_para.tpr6 & 0x0fc00000) << 2) |
+ ((dram_para.tpr7 & 0x0000001f) << 16) |
+ ((dram_para.tpr7 & 0x000003e0) << 3) |
+ ((dram_para.tpr7 & 0x0000fc00) >> 10),
+ &mctl_ctl->dramtmg2);
+
+ writel(((dram_para.tpr7 & 0x03ff0000) >> 16) |
+ ((dram_para.tpr6 & 0xf0000000) >> 16),
+ &mctl_ctl->dramtmg3);
+
+ writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) |
+ ((dram_para.tpr8 & 0x00000007) << 16) |
+ ((dram_para.tpr8 & 0x00000038) << 5) |
+ ((dram_para.tpr8 & 0x000003c0) >> 6),
+ &mctl_ctl->dramtmg4);
+
+ writel(((dram_para.tpr8 & 0x00003c00) << 14) |
+ ((dram_para.tpr8 & 0x0003c000) << 2) |
+ ((dram_para.tpr8 & 0x00fc0000) >> 10) |
+ ((dram_para.tpr8 & 0x0f000000) >> 24),
+ &mctl_ctl->dramtmg5);
+
+ writel(0x00000008, &mctl_ctl->dramtmg8);
+
+ writel(((dram_para.tpr8 & 0xf0000000) >> 4) |
+ ((dram_para.tpr9 & 0x00007c00) << 6) |
+ ((dram_para.tpr9 & 0x000003e0) << 3) |
+ ((dram_para.tpr9 & 0x0000001f) >> 0),
+ &mctl_ctl->pitmg0);
+
+ setbits_le32(&mctl_ctl->pitmg1, 0x80000);
+
+ writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001,
+ &mctl_ctl->sched);
+
+ writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3);
+ writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4);
+
+ writel(0x00000000, &mctl_ctl->pimisc);
+ writel(0x80000000, &mctl_ctl->upd0);
+
+ writel(((dram_para.tpr9 & 0xffc00000) >> 22) |
+ ((dram_para.tpr10 & 0x00000fff) << 16),
+ &mctl_ctl->rfshtmg);
+
+ if (dram_para.tpr13 & 0x20)
+ writel(0x01040001, &mctl_ctl->mstr);
+ else
+ writel(0x01040401, &mctl_ctl->mstr);
+
+ if (!(dram_para.tpr13 & 0x20000)) {
+ writel(0x00000002, &mctl_ctl->pwrctl);
+ writel(0x00008001, &mctl_ctl->pwrtmg);
+ }
+
+ writel(0x00000001, &mctl_ctl->rfshctl3);
+ writel(0x00000001, &mctl_ctl->pimisc);
+
+ /* deassert dram_clk_cfg reset */
+ setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
+
+ setbits_le32(&mctl_com->ccr, 0x80000);
+
+ /* zq stuff */
+ writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1);
+
+ writel(0x00000003, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09);
+
+ writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2);
+ writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
+
+ /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */
+ writel(0x000005f3, &mctl_phy->pir);
+ udelay(10);
+ mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03);
+
+ if (readl(&mctl_phy->dx1gsr0) & 0x1000000) {
+ *bus_width = 8;
+ writel(0, &mctl_phy->dx1gcr);
+ writel(dram_para.zq & 0xff, &mctl_phy->zqcr1);
+ writel(0x5f3, &mctl_phy->pir);
+ udelay(10000);
+ setbits_le32(&mctl_ctl->mstr, 0x1000);
+ } else
+ *bus_width = 16;
+
+ correction = (dram_para.odt_en >> 8) & 0xff;
+ if (correction) {
+ if (dram_para.odt_en & 0x80000000)
+ correction = -correction;
+
+ mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction);
+ mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction);
+ }
+
+ mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01);
+
+ writel(0x08003e3f, &mctl_phy->pgcr0);
+ writel(0x00000000, &mctl_ctl->rfshctl3);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ const u32 columns = 13;
+ u32 bus, bus_width, offset, page_size, rows;
+
+ mctl_sys_init();
+ mctl_init(&bus_width);
+
+ if (bus_width == 16) {
+ page_size = 8;
+ bus = 1;
+ } else {
+ page_size = 7;
+ bus = 0;
+ }
+
+ if (!(dram_para.tpr13 & 0x80000000)) {
+ /* Detect and set rows */
+ writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size),
+ &mctl_com->cr);
+ setbits_le32(&mctl_com->swonr, 0x0003ffff);
+ for (rows = 11; rows < 16; rows++) {
+ offset = 1 << (rows + columns + bus);
+ if (mctl_mem_matches(offset))
+ break;
+ }
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
+ MCTL_CR_ROW(rows));
+ } else {
+ rows = (dram_para.para1 >> 16) & 0xff;
+ writel(((dram_para.para2 & 0x000000f0) << 11) |
+ ((rows - 1) << 4) |
+ ((dram_para.para1 & 0x0f000000) >> 22) |
+ 0x31000 | MCTL_CR_PAGE_SIZE(page_size),
+ &mctl_com->cr);
+ setbits_le32(&mctl_com->swonr, 0x0003ffff);
+ }
+
+ /* Setup DRAM master priority? If this is left out things still work */
+ writel(0x00000008, &mctl_com->mcr0_0);
+ writel(0x0001000d, &mctl_com->mcr1_0);
+ writel(0x00000004, &mctl_com->mcr0_1);
+ writel(0x00000080, &mctl_com->mcr1_1);
+ writel(0x00000004, &mctl_com->mcr0_2);
+ writel(0x00000019, &mctl_com->mcr1_2);
+ writel(0x00000004, &mctl_com->mcr0_3);
+ writel(0x00000080, &mctl_com->mcr1_3);
+ writel(0x00000004, &mctl_com->mcr0_4);
+ writel(0x01010040, &mctl_com->mcr1_4);
+ writel(0x00000004, &mctl_com->mcr0_5);
+ writel(0x0001002f, &mctl_com->mcr1_5);
+ writel(0x00000004, &mctl_com->mcr0_6);
+ writel(0x00010020, &mctl_com->mcr1_6);
+ writel(0x00000004, &mctl_com->mcr0_7);
+ writel(0x00010020, &mctl_com->mcr1_7);
+ writel(0x00000008, &mctl_com->mcr0_8);
+ writel(0x00000001, &mctl_com->mcr1_8);
+ writel(0x00000008, &mctl_com->mcr0_9);
+ writel(0x00000005, &mctl_com->mcr1_9);
+ writel(0x00000008, &mctl_com->mcr0_10);
+ writel(0x00000003, &mctl_com->mcr1_10);
+ writel(0x00000008, &mctl_com->mcr0_11);
+ writel(0x00000005, &mctl_com->mcr1_11);
+ writel(0x00000008, &mctl_com->mcr0_12);
+ writel(0x00000003, &mctl_com->mcr1_12);
+ writel(0x00000008, &mctl_com->mcr0_13);
+ writel(0x00000004, &mctl_com->mcr1_13);
+ writel(0x00000008, &mctl_com->mcr0_14);
+ writel(0x00000002, &mctl_com->mcr1_14);
+ writel(0x00000008, &mctl_com->mcr0_15);
+ writel(0x00000003, &mctl_com->mcr1_15);
+ writel(0x00010138, &mctl_com->bwcr);
+
+ return 1 << (rows + columns + bus);
+}
--- /dev/null
+/*
+ * Sun8i a33 platform dram controller init.
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+/* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
+#define DRAM_CLK_MUL 2
+#define DRAM_CLK_DIV 4
+#define DRAM_SIGMA_DELTA_ENABLE 1
+#define DRAM_ODT_EN 0
+
+struct dram_para {
+ u8 cs1;
+ u8 seq;
+ u8 bank;
+ u8 rank;
+ u8 rows;
+ u8 bus_width;
+ u16 page_size;
+};
+
+static void mctl_set_cr(struct dram_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
+ MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
+ (para->seq ? MCTL_CR_SEQUENCE : 0) |
+ ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
+ MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+ MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
+ &mctl_com->cr);
+}
+
+static void auto_detect_dram_size(struct dram_para *para)
+{
+ u8 orig_rank = para->rank;
+ int rows, columns;
+
+ /* Row detect */
+ para->page_size = 512;
+ para->seq = 1;
+ para->rows = 16;
+ para->rank = 1;
+ mctl_set_cr(para);
+ for (rows = 11 ; rows < 16 ; rows++) {
+ if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
+ break;
+ }
+
+ /* Column (page size) detect */
+ para->rows = 11;
+ para->page_size = 8192;
+ mctl_set_cr(para);
+ for (columns = 9 ; columns < 13 ; columns++) {
+ if (mctl_mem_matches(1 << columns))
+ break;
+ }
+
+ para->seq = 0;
+ para->rank = orig_rank;
+ para->rows = rows;
+ para->page_size = 1 << columns;
+ mctl_set_cr(para);
+}
+
+static inline int ns_to_t(int nanoseconds)
+{
+ const unsigned int ctrl_freq =
+ CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
+
+ return (ctrl_freq * nanoseconds + 999) / 1000;
+}
+
+static void auto_set_timing_para(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ u32 reg_val;
+
+ u8 tccd = 2;
+ u8 tfaw = ns_to_t(50);
+ u8 trrd = max(ns_to_t(10), 4);
+ u8 trcd = ns_to_t(15);
+ u8 trc = ns_to_t(53);
+ u8 txp = max(ns_to_t(8), 3);
+ u8 twtr = max(ns_to_t(8), 4);
+ u8 trtp = max(ns_to_t(8), 4);
+ u8 twr = max(ns_to_t(15), 3);
+ u8 trp = ns_to_t(15);
+ u8 tras = ns_to_t(38);
+
+ u16 trefi = ns_to_t(7800) / 32;
+ u16 trfc = ns_to_t(350);
+
+ /* Fixed timing parameters */
+ u8 tmrw = 0;
+ u8 tmrd = 4;
+ u8 tmod = 12;
+ u8 tcke = 3;
+ u8 tcksrx = 5;
+ u8 tcksre = 5;
+ u8 tckesr = 4;
+ u8 trasmax = 24;
+ u8 tcl = 6; /* CL 12 */
+ u8 tcwl = 4; /* CWL 8 */
+ u8 t_rdata_en = 4;
+ u8 wr_latency = 2;
+
+ u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
+ u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
+ u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
+ u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
+
+ u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
+ u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
+ u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
+
+ /* Set work mode register */
+ mctl_set_cr(para);
+ /* Set mode register */
+ writel(MCTL_MR0, &mctl_ctl->mr0);
+ writel(MCTL_MR1, &mctl_ctl->mr1);
+ writel(MCTL_MR2, &mctl_ctl->mr2);
+ writel(MCTL_MR3, &mctl_ctl->mr3);
+ /* Set dram timing */
+ reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
+ writel(reg_val, &mctl_ctl->dramtmg0);
+ reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
+ writel(reg_val, &mctl_ctl->dramtmg1);
+ reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
+ writel(reg_val, &mctl_ctl->dramtmg2);
+ reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
+ writel(reg_val, &mctl_ctl->dramtmg3);
+ reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
+ writel(reg_val, &mctl_ctl->dramtmg4);
+ reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
+ writel(reg_val, &mctl_ctl->dramtmg5);
+ /* Set two rank timing and exit self-refresh timing */
+ reg_val = readl(&mctl_ctl->dramtmg8);
+ reg_val &= ~(0xff << 8);
+ reg_val &= ~(0xff << 0);
+ reg_val |= (0x33 << 8);
+ reg_val |= (0x8 << 0);
+ writel(reg_val, &mctl_ctl->dramtmg8);
+ /* Set phy interface time */
+ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
+ | (wr_latency << 0);
+ /* PHY interface write latency and read latency configure */
+ writel(reg_val, &mctl_ctl->pitmg0);
+ /* Set phy time PTR0-2 use default */
+ writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
+ writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
+ /* Set refresh timing */
+ reg_val = (trefi << 16) | (trfc << 0);
+ writel(reg_val, &mctl_ctl->rfshtmg);
+}
+
+static void mctl_set_pir(u32 val)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ writel(val, &mctl_ctl->pir);
+ mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
+}
+
+static void mctl_data_train_cfg(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ if (para->rank == 2)
+ clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
+ else
+ clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
+}
+
+static int mctl_train_dram(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ mctl_data_train_cfg(para);
+ mctl_set_pir(0x1f3);
+
+ return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
+}
+
+static int mctl_channel_init(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ u32 low_data_lines_status; /* Training status of datalines 0 - 7 */
+ u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
+
+ auto_set_timing_para(para);
+
+ /* Disable dram VTC */
+ clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0);
+
+ /* Set ODT */
+ if ((CONFIG_DRAM_CLK > 400) && DRAM_ODT_EN) {
+ setbits_le32(DXnGCR0(0), 0x3 << 9);
+ setbits_le32(DXnGCR0(1), 0x3 << 9);
+ } else {
+ clrbits_le32(DXnGCR0(0), 0x3 << 9);
+ clrbits_le32(DXnGCR0(1), 0x3 << 9);
+ }
+
+ /* set PLL configuration */
+ if (CONFIG_DRAM_CLK >= 480)
+ setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18);
+ else
+ setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18);
+
+ /* Auto detect dram config, set 2 rank and 16bit bus-width */
+ para->cs1 = 0;
+ para->rank = 2;
+ para->bus_width = 16;
+ mctl_set_cr(para);
+
+ /* Open DQS gating */
+ clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
+ clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
+
+ mctl_data_train_cfg(para);
+
+ /* ZQ calibration */
+ writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1);
+ /* CA calibration */
+ mctl_set_pir(0x00000003);
+ /* More ZQ calibration */
+ writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2);
+ writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1);
+
+ /* DQS gate training */
+ if (mctl_train_dram(para) != 0) {
+ low_data_lines_status = (readl(DXnGSR0(0)) >> 24) & 0x03;
+ high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
+
+ if (low_data_lines_status == 0x3)
+ return -EIO;
+
+ /* DRAM has only one rank */
+ para->rank = 1;
+ mctl_set_cr(para);
+
+ if (low_data_lines_status == high_data_lines_status)
+ goto done; /* 16 bit bus, 1 rank */
+
+ if (!(low_data_lines_status & high_data_lines_status)) {
+ /* Retry 16 bit bus-width with CS1 set */
+ para->cs1 = 1;
+ mctl_set_cr(para);
+ if (mctl_train_dram(para) == 0)
+ goto done;
+ }
+
+ /* Try 8 bit bus-width */
+ writel(0x0, DXnGCR0(1)); /* Disable high DQ */
+ para->cs1 = 0;
+ para->bus_width = 8;
+ mctl_set_cr(para);
+ if (mctl_train_dram(para) != 0)
+ return -EIO;
+ }
+done:
+ /* Check the dramc status */
+ mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
+
+ /* Close DQS gating */
+ setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
+
+ /* Enable master access */
+ writel(0xffffffff, &mctl_com->maer);
+
+ return 0;
+}
+
+static void mctl_sys_init(struct dram_para *para)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK,
+ CCM_DRAMPLL_CFG_SRC_PLL11);
+
+ clock_set_pll11(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL,
+ DRAM_SIGMA_DELTA_ENABLE);
+
+ clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
+ CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
+ CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
+ mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+ setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
+ setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
+
+ /* Set dram master access priority */
+ writel(0x0, &mctl_com->mapr);
+ writel(0x0f802f01, &mctl_ctl->sched);
+ writel(0x0000400f, &mctl_ctl->clken); /* normal */
+
+ udelay(250);
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ struct dram_para para = {
+ .cs1 = 0,
+ .bank = 1,
+ .rank = 1,
+ .rows = 15,
+ .bus_width = 16,
+ .page_size = 2048,
+ };
+
+ mctl_sys_init(¶);
+
+ if (mctl_channel_init(¶) != 0)
+ return 0;
+
+ auto_detect_dram_size(¶);
+
+ /* Enable master software clk */
+ writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
+
+ /* Set DRAM ODT MAP */
+ if (para.rank == 2)
+ writel(0x00000303, &mctl_ctl->odtmap);
+ else
+ writel(0x00000201, &mctl_ctl->odtmap);
+
+ return para.page_size * (para.bus_width / 8) *
+ (1 << (para.bank + para.rank + para.rows));
+}
--- /dev/null
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Sunxi PMIC bus access helpers
+ *
+ * The axp152 & axp209 use an i2c bus, the axp221 uses the p2wi bus and the
+ * axp223 uses the rsb bus, these functions abstract this.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/rsb.h>
+#include <i2c.h>
+#include <asm/arch/pmic_bus.h>
+
+#define AXP152_I2C_ADDR 0x30
+
+#define AXP209_I2C_ADDR 0x34
+
+#define AXP221_CHIP_ADDR 0x68
+#define AXP221_CTRL_ADDR 0x3e
+#define AXP221_INIT_DATA 0x3e
+
+#define AXP223_DEVICE_ADDR 0x3a3
+#define AXP223_RUNTIME_ADDR 0x2d
+
+int pmic_bus_init(void)
+{
+ /* This cannot be 0 because it is used in SPL before BSS is ready */
+ static int needs_init = 1;
+ __maybe_unused int ret;
+
+ if (!needs_init)
+ return 0;
+
+#ifdef CONFIG_AXP221_POWER
+# ifdef CONFIG_MACH_SUN6I
+ p2wi_init();
+ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
+ AXP221_INIT_DATA);
+# else
+ ret = rsb_init();
+ if (ret)
+ return ret;
+
+ ret = rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
+# endif
+ if (ret)
+ return ret;
+#endif
+
+ needs_init = 0;
+ return 0;
+}
+
+int pmic_bus_read(u8 reg, u8 *data)
+{
+#ifdef CONFIG_AXP152_POWER
+ return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
+#elif defined CONFIG_AXP209_POWER
+ return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
+#elif defined CONFIG_AXP221_POWER
+# ifdef CONFIG_MACH_SUN6I
+ return p2wi_read(reg, data);
+# else
+ return rsb_read(AXP223_RUNTIME_ADDR, reg, data);
+# endif
+#endif
+}
+
+int pmic_bus_write(u8 reg, u8 data)
+{
+#ifdef CONFIG_AXP152_POWER
+ return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
+#elif defined CONFIG_AXP209_POWER
+ return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
+#elif defined CONFIG_AXP221_POWER
+# ifdef CONFIG_MACH_SUN6I
+ return p2wi_write(reg, data);
+# else
+ return rsb_write(AXP223_RUNTIME_ADDR, reg, data);
+# endif
+#endif
+}
+
+int pmic_bus_setbits(u8 reg, u8 bits)
+{
+ int ret;
+ u8 val;
+
+ ret = pmic_bus_read(reg, &val);
+ if (ret)
+ return ret;
+
+ val |= bits;
+ return pmic_bus_write(reg, val);
+}
+
+int pmic_bus_clrbits(u8 reg, u8 bits)
+{
+ int ret;
+ u8 val;
+
+ ret = pmic_bus_read(reg, &val);
+ if (ret)
+ return ret;
+
+ val &= ~bits;
+ return pmic_bus_write(reg, val);
+}
isb
bl _nonsec_init
- bl psci_arch_init
adr r0, _target_pc
ldr r0, [r0]
--- /dev/null
+/*
+ * Sunxi usb-phy code
+ *
+ * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/usb_phy.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <errno.h>
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#endif
+#ifdef CONFIG_AXP209_POWER
+#include <axp209.h>
+#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
+
+#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
+#ifdef CONFIG_MACH_SUN8I_A33
+#define SUNXI_USB_CSR 0x410
+#else
+#define SUNXI_USB_CSR 0x404
+#endif
+#define SUNXI_USB_PASSBY_EN 1
+
+#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
+#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
+#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
+#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
+
+static struct sunxi_usb_phy {
+ int usb_rst_mask;
+ int gpio_vbus;
+ int gpio_vbus_det;
+ int id;
+ int init_count;
+ int power_on_count;
+} sunxi_usb_phy[] = {
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
+ .id = 0,
+ },
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
+ .id = 1,
+ },
+#if CONFIG_SUNXI_USB_PHYS >= 3
+ {
+ .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
+ .id = 2,
+ }
+#endif
+};
+
+static int get_vbus_gpio(int index)
+{
+ switch (index) {
+ case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
+ case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
+ case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ }
+ return -EINVAL;
+}
+
+static int get_vbus_detect_gpio(int index)
+{
+ switch (index) {
+ case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
+ }
+ return -EINVAL;
+}
+
+static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
+ int data, int len)
+{
+ int j = 0, usbc_bit = 0;
+ void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
+
+#ifdef CONFIG_MACH_SUN8I_A33
+ /* CSR needs to be explicitly initialized to 0 on A33 */
+ writel(0, dest);
+#endif
+
+ usbc_bit = 1 << (phy->id * 2);
+ for (j = 0; j < len; j++) {
+ /* set the bit address to be written */
+ clrbits_le32(dest, 0xff << 8);
+ setbits_le32(dest, (addr + j) << 8);
+
+ clrbits_le32(dest, usbc_bit);
+ /* set data bit */
+ if (data & 0x1)
+ setbits_le32(dest, 1 << 7);
+ else
+ clrbits_le32(dest, 1 << 7);
+
+ setbits_le32(dest, usbc_bit);
+
+ clrbits_le32(dest, usbc_bit);
+
+ data >>= 1;
+ }
+}
+
+static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
+{
+ /* The following comments are machine
+ * translated from Chinese, you have been warned!
+ */
+
+ /* Regulation 45 ohms */
+ if (phy->id == 0)
+ usb_phy_write(phy, 0x0c, 0x01, 1);
+
+ /* adjust PHY's magnitude and rate */
+ usb_phy_write(phy, 0x20, 0x14, 5);
+
+ /* threshold adjustment disconnect */
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I
+ usb_phy_write(phy, 0x2a, 3, 2);
+#else
+ usb_phy_write(phy, 0x2a, 2, 2);
+#endif
+
+ return;
+}
+
+static void sunxi_usb_phy_passby(int index, int enable)
+{
+ unsigned long bits = 0;
+ void *addr;
+
+ if (index == 1)
+ addr = (void *)SUNXI_USB1_BASE + SUNXI_USB_PMU_IRQ_ENABLE;
+ else
+ addr = (void *)SUNXI_USB2_BASE + SUNXI_USB_PMU_IRQ_ENABLE;
+
+ bits = SUNXI_EHCI_AHB_ICHR8_EN |
+ SUNXI_EHCI_AHB_INCR4_BURST_EN |
+ SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
+ SUNXI_EHCI_ULPI_BYPASS_EN;
+
+ if (enable)
+ setbits_le32(addr, bits);
+ else
+ clrbits_le32(addr, bits);
+
+ return;
+}
+
+void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
+}
+
+void sunxi_usb_phy_init(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ phy->init_count++;
+ if (phy->init_count != 1)
+ return;
+
+ setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
+
+ sunxi_usb_phy_config(phy);
+
+ if (phy->id != 0)
+ sunxi_usb_phy_passby(index, SUNXI_USB_PASSBY_EN);
+}
+
+void sunxi_usb_phy_exit(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ phy->init_count--;
+ if (phy->init_count != 0)
+ return;
+
+ if (phy->id != 0)
+ sunxi_usb_phy_passby(index, !SUNXI_USB_PASSBY_EN);
+
+ clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
+}
+
+void sunxi_usb_phy_power_on(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ phy->power_on_count++;
+ if (phy->power_on_count != 1)
+ return;
+
+ if (phy->gpio_vbus >= 0)
+ gpio_set_value(phy->gpio_vbus, 1);
+}
+
+void sunxi_usb_phy_power_off(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+
+ phy->power_on_count--;
+ if (phy->power_on_count != 0)
+ return;
+
+ if (phy->gpio_vbus >= 0)
+ gpio_set_value(phy->gpio_vbus, 0);
+}
+
+int sunxi_usb_phy_vbus_detect(int index)
+{
+ struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
+ int err, retries = 3;
+
+ if (phy->gpio_vbus_det < 0) {
+ eprintf("Error: invalid vbus detection pin\n");
+ return phy->gpio_vbus_det;
+ }
+
+ err = gpio_get_value(phy->gpio_vbus_det);
+ /*
+ * Vbus may have been provided by the board and just been turned of
+ * some milliseconds ago on reset, what we're measuring then is a
+ * residual charge on Vbus, sleep a bit and try again.
+ */
+ while (err > 0 && retries--) {
+ mdelay(100);
+ err = gpio_get_value(phy->gpio_vbus_det);
+ }
+
+ return err;
+}
+
+int sunxi_usb_phy_probe(void)
+{
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_usb_phy *phy;
+ int i, ret = 0;
+
+ for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
+ phy = &sunxi_usb_phy[i];
+
+ phy->gpio_vbus = get_vbus_gpio(i);
+ if (phy->gpio_vbus >= 0) {
+ ret = gpio_request(phy->gpio_vbus, "usb_vbus");
+ if (ret)
+ return ret;
+ ret = gpio_direction_output(phy->gpio_vbus, 0);
+ if (ret)
+ return ret;
+ }
+
+ phy->gpio_vbus_det = get_vbus_detect_gpio(i);
+ if (phy->gpio_vbus_det >= 0) {
+ ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
+ if (ret)
+ return ret;
+ ret = gpio_direction_input(phy->gpio_vbus_det);
+ if (ret)
+ return ret;
+ }
+ }
+
+ setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+ return 0;
+}
+
+int sunxi_usb_phy_remove(void)
+{
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_usb_phy *phy;
+ int i;
+
+ clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+
+ for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
+ phy = &sunxi_usb_phy[i];
+
+ if (phy->gpio_vbus >= 0)
+ gpio_free(phy->gpio_vbus);
+
+ if (phy->gpio_vbus_det >= 0)
+ gpio_free(phy->gpio_vbus_det);
+ }
+
+ return 0;
+}
+++ /dev/null
-/*
- * Sunxi usb-controller code shared between the ehci and musb controllers
- *
- * Copyright (C) 2014 Roman Byshko
- *
- * Roman Byshko <rbyshko@gmail.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/usbc.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <common.h>
-#ifdef CONFIG_AXP152_POWER
-#include <axp152.h>
-#endif
-#ifdef CONFIG_AXP209_POWER
-#include <axp209.h>
-#endif
-#ifdef CONFIG_AXP221_POWER
-#include <axp221.h>
-#endif
-
-#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
-#define SUNXI_USB_CSR 0x404
-#define SUNXI_USB_PASSBY_EN 1
-
-#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
-#define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
-#define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
-#define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
-
-static struct sunxi_usbc_hcd {
- struct usb_hcd *hcd;
- int usb_rst_mask;
- int ahb_clk_mask;
- int gpio_vbus;
- int gpio_vbus_det;
- int irq;
- int id;
-} sunxi_usbc_hcd[] = {
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
- .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB0,
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
- .irq = 71,
-#else
- .irq = 38,
-#endif
- .id = 0,
- },
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
- .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
- .irq = 72,
-#else
- .irq = 39,
-#endif
- .id = 1,
- },
-#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
- {
- .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
- .ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
-#ifdef CONFIG_MACH_SUN6I
- .irq = 74,
-#else
- .irq = 40,
-#endif
- .id = 2,
- }
-#endif
-};
-
-static int enabled_hcd_count;
-
-void *sunxi_usbc_get_io_base(int index)
-{
- switch (index) {
- case 0:
- return (void *)SUNXI_USB0_BASE;
- case 1:
- return (void *)SUNXI_USB1_BASE;
- case 2:
- return (void *)SUNXI_USB2_BASE;
- default:
- return NULL;
- }
-}
-
-static int get_vbus_gpio(int index)
-{
- switch (index) {
- case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
- case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
- case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
- }
- return -1;
-}
-
-static int get_vbus_detect_gpio(int index)
-{
- switch (index) {
- case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
- }
- return -1;
-}
-
-static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
- int data, int len)
-{
- int j = 0, usbc_bit = 0;
- void *dest = sunxi_usbc_get_io_base(0) + SUNXI_USB_CSR;
-
- usbc_bit = 1 << (sunxi_usbc->id * 2);
- for (j = 0; j < len; j++) {
- /* set the bit address to be written */
- clrbits_le32(dest, 0xff << 8);
- setbits_le32(dest, (addr + j) << 8);
-
- clrbits_le32(dest, usbc_bit);
- /* set data bit */
- if (data & 0x1)
- setbits_le32(dest, 1 << 7);
- else
- clrbits_le32(dest, 1 << 7);
-
- setbits_le32(dest, usbc_bit);
-
- clrbits_le32(dest, usbc_bit);
-
- data >>= 1;
- }
-}
-
-static void sunxi_usb_phy_init(struct sunxi_usbc_hcd *sunxi_usbc)
-{
- /* The following comments are machine
- * translated from Chinese, you have been warned!
- */
-
- /* Regulation 45 ohms */
- if (sunxi_usbc->id == 0)
- usb_phy_write(sunxi_usbc, 0x0c, 0x01, 1);
-
- /* adjust PHY's magnitude and rate */
- usb_phy_write(sunxi_usbc, 0x20, 0x14, 5);
-
- /* threshold adjustment disconnect */
-#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I
- usb_phy_write(sunxi_usbc, 0x2a, 3, 2);
-#else
- usb_phy_write(sunxi_usbc, 0x2a, 2, 2);
-#endif
-
- return;
-}
-
-static void sunxi_usb_passby(struct sunxi_usbc_hcd *sunxi_usbc, int enable)
-{
- unsigned long bits = 0;
- void *addr = sunxi_usbc_get_io_base(sunxi_usbc->id) +
- SUNXI_USB_PMU_IRQ_ENABLE;
-
- bits = SUNXI_EHCI_AHB_ICHR8_EN |
- SUNXI_EHCI_AHB_INCR4_BURST_EN |
- SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
- SUNXI_EHCI_ULPI_BYPASS_EN;
-
- if (enable)
- setbits_le32(addr, bits);
- else
- clrbits_le32(addr, bits);
-
- return;
-}
-
-void sunxi_usbc_enable_squelch_detect(int index, int enable)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
-
- usb_phy_write(sunxi_usbc, 0x3c, enable ? 0 : 2, 2);
-}
-
-int sunxi_usbc_request_resources(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
- int ret = 0;
-
- sunxi_usbc->gpio_vbus = get_vbus_gpio(index);
- if (sunxi_usbc->gpio_vbus != -1) {
- ret |= gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
- ret |= gpio_direction_output(sunxi_usbc->gpio_vbus, 0);
- }
-
- sunxi_usbc->gpio_vbus_det = get_vbus_detect_gpio(index);
- if (sunxi_usbc->gpio_vbus_det != -1) {
- ret |= gpio_request(sunxi_usbc->gpio_vbus_det, "usbc_vbus_det");
- ret |= gpio_direction_input(sunxi_usbc->gpio_vbus_det);
- }
-
- return ret;
-}
-
-int sunxi_usbc_free_resources(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
- int ret = 0;
-
- if (sunxi_usbc->gpio_vbus != -1)
- ret |= gpio_free(sunxi_usbc->gpio_vbus);
-
- if (sunxi_usbc->gpio_vbus_det != -1)
- ret |= gpio_free(sunxi_usbc->gpio_vbus_det);
-
- return ret;
-}
-
-void sunxi_usbc_enable(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- /* enable common PHY only once */
- if (enabled_hcd_count == 0)
- setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
- setbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
- setbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
- setbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
-#endif
-
- sunxi_usb_phy_init(sunxi_usbc);
-
- if (sunxi_usbc->id != 0)
- sunxi_usb_passby(sunxi_usbc, SUNXI_USB_PASSBY_EN);
-
- enabled_hcd_count++;
-}
-
-void sunxi_usbc_disable(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-
- if (sunxi_usbc->id != 0)
- sunxi_usb_passby(sunxi_usbc, !SUNXI_USB_PASSBY_EN);
-
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
- clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_usbc->ahb_clk_mask);
-#endif
- clrbits_le32(&ccm->ahb_gate0, sunxi_usbc->ahb_clk_mask);
- clrbits_le32(&ccm->usb_clk_cfg, sunxi_usbc->usb_rst_mask);
-
- /* disable common PHY only once, for the last enabled hcd */
- if (enabled_hcd_count == 1)
- clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
-
- enabled_hcd_count--;
-}
-
-void sunxi_usbc_vbus_enable(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
-
- if (sunxi_usbc->gpio_vbus != -1)
- gpio_set_value(sunxi_usbc->gpio_vbus, 1);
-}
-
-void sunxi_usbc_vbus_disable(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
-
- if (sunxi_usbc->gpio_vbus != -1)
- gpio_set_value(sunxi_usbc->gpio_vbus, 0);
-}
-
-int sunxi_usbc_vbus_detect(int index)
-{
- struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
- int err, retries = 3;
-
- if (sunxi_usbc->gpio_vbus_det == -1) {
- eprintf("Error: invalid vbus detection pin\n");
- return -1;
- }
-
- err = gpio_get_value(sunxi_usbc->gpio_vbus_det);
- /*
- * Vbus may have been provided by the board and just been turned of
- * some milliseconds ago on reset, what we're measuring then is a
- * residual charge on Vbus, sleep a bit and try again.
- */
- while (err > 0 && retries--) {
- mdelay(100);
- err = gpio_get_value(sunxi_usbc->gpio_vbus_det);
- }
-
- return err;
-}
-dtb-$(CONFIG_MACH_SUN7I) += sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr.dtb
+dtb-$(CONFIG_MACH_SUN4I) += \
+ sun4i-a10-a1000.dtb \
+ sun4i-a10-ba10-tvbox.dtb \
+ sun4i-a10-chuwi-v7-cw0825.dtb \
+ sun4i-a10-cubieboard.dtb \
+ sun4i-a10-gemei-g9.dtb \
+ sun4i-a10-hackberry.dtb \
+ sun4i-a10-hyundai-a7hd.dtb \
+ sun4i-a10-inet-3f.dtb \
+ sun4i-a10-inet-3w.dtb \
+ sun4i-a10-inet97fv2.dtb \
+ sun4i-a10-jesurun-q5.dtb \
+ sun4i-a10-marsboard.dtb \
+ sun4i-a10-mini-xplus.dtb \
+ sun4i-a10-mk802.dtb \
+ sun4i-a10-mk802ii.dtb \
+ sun4i-a10-olinuxino-lime.dtb \
+ sun4i-a10-pcduino.dtb
+dtb-$(CONFIG_MACH_SUN5I) += \
+ sun5i-a10s-auxtek-t004.dtb \
+ sun5i-a10s-mk802.dtb \
+ sun5i-a10s-olinuxino-micro.dtb \
+ sun5i-a10s-r7-tv-dongle.dtb \
+ sun5i-a13-ampe-a76.dtb \
+ sun5i-a13-forfun-q88db.dtb \
+ sun5i-a13-hsg-h702.dtb \
+ sun5i-a13-inet-86vs.dtb \
+ sun5i-a13-olinuxino.dtb \
+ sun5i-a13-olinuxino-micro.dtb \
+ sun5i-a13-tzx-q8-713b7.dtb \
+ sun5i-a13-utoo-p66.dtb
+dtb-$(CONFIG_MACH_SUN6I) += \
+ sun6i-a31-app4-evb1.dtb \
+ sun6i-a31-colombus.dtb \
+ sun6i-a31-hummingbird.dtb \
+ sun6i-a31-i7.dtb \
+ sun6i-a31-m9.dtb \
+ sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31s-cs908.dtb \
+ sun6i-a31s-primo81.dtb
+dtb-$(CONFIG_MACH_SUN7I) += \
+ sun7i-a20-ainol-aw1.dtb \
+ sun7i-a20-bananapi.dtb \
+ sun7i-a20-bananapro.dtb \
+ sun7i-a20-cubieboard2.dtb \
+ sun7i-a20-cubietruck.dtb \
+ sun7i-a20-hummingbird.dtb \
+ sun7i-a20-i12-tvbox.dtb \
+ sun7i-a20-m3.dtb \
+ sun7i-a20-m5.dtb \
+ sun7i-a20-mk808c.dtb \
+ sun7i-a20-olinuxino-lime.dtb \
+ sun7i-a20-olinuxino-lime2.dtb \
+ sun7i-a20-olinuxino-micro.dtb \
+ sun7i-a20-orangepi.dtb \
+ sun7i-a20-orangepi-mini.dtb \
+ sun7i-a20-pcduino3.dtb \
+ sun7i-a20-pcduino3-nano.dtb \
+ sun7i-a20-primo73.dtb \
+ sun7i-a20-wexler-tab7200.dtb \
+ sun7i-a20-wits-pro-a20-dkt.dtb \
+ sun7i-a20-yones-toptech-bd1078.dtb
+dtb-$(CONFIG_MACH_SUN8I_A23) += \
+ sun8i-a23-ippo-q8h-v5.dtb \
+ sun8i-a23-ippo-q8h-v1.2.dtb
+dtb-$(CONFIG_MACH_SUN8I_A33) += \
+ sun8i-a33-astar-mid756.dtb \
+ sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb
+dtb-$(CONFIG_MACH_SUN9I) += \
+ sun9i-a80-optimus.dtb \
+ sun9i-a80-cubieboard4.dtb
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
--- /dev/null
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP202/209 Integrated Power Management Chip
+ * http://www.x-powers.com/product/AXP20X.php
+ * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
+ */
+
+&axp209 {
+ compatible = "x-powers,axp209";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ /* Default work frequency for buck regulators */
+ x-powers,dcdc-freq = <1500>;
+
+ reg_dcdc2: dcdc2 {
+ regulator-name = "dcdc2";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "dcdc3";
+ };
+
+ reg_ldo1: ldo1 {
+ /* LDO1 is a fixed output regulator */
+ regulator-always-on;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "ldo1";
+ };
+
+ reg_ldo2: ldo2 {
+ regulator-name = "ldo2";
+ };
+
+ reg_ldo3: ldo3 {
+ regulator-name = "ldo3";
+ };
+
+ reg_ldo4: ldo4 {
+ regulator-name = "ldo4";
+ };
+
+ reg_ldo5: ldo5 {
+ regulator-name = "ldo5";
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013 Emilio López
+ *
+ * Emilio López <emilio@elopez.com.ar>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Mele A1000";
+ compatible = "mele,a1000", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_a1000>;
+
+ red {
+ label = "a1000:red:usr";
+ gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "a1000:blue:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_power_pin_a1000>;
+ regulator-name = "emac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ phy-supply = <®_emac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ emac_power_pin_a1000: emac_power_pin@0 {
+ allwinner,pins = "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_a1000: led_pins@0 {
+ allwinner,pins = "PH10", "PH20";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BA10 tvbox";
+ compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = "PH12";
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Chuwi V7 CW0825";
+ compatible = "chuwi,v7-cw0825", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@800 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button@1000 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+
+ button@1200 {
+ label = "Back";
+ linux,code = <KEY_BACK>;
+ channel = <0>;
+ voltage = <1200000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Stefan Roese
+ * Stefan Roese <sr@denx.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Cubietech Cubieboard";
+ compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_cubieboard>;
+
+ blue {
+ label = "cubieboard:blue:usr";
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
+ };
+
+ green {
+ label = "cubieboard:green:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_cubieboard: led_pins@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Priit Laes
+ *
+ * Priit Laes <plaes@plaes.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Gemei G9 Tablet";
+ compatible = "gemei,g9", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/*
+ * TODO:
+ * 2x cameras via CSI
+ * bma250 IRQs
+ * AXP battery management
+ * NAND
+ * OTG
+ * Touchscreen - gt801_2plus1 @ i2c adapter 2 @ 0x48
+ */
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+
+ /*
+ * TODO: interrupt pins:
+ * int1 - PH00
+ * int2 - PI10
+ */
+ };
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+
+ status = "okay";
+
+ button@158 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <158730>;
+ };
+
+ button@349 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <349206>;
+ };
+
+ button@1142 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1142856>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
+ cd-inverted;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Miniand Hackberry";
+ compatible = "miniand,hackberry", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "emac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy0>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ phy-supply = <®_emac_3v3>;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hackberry_hogs>;
+
+ hackberry_hogs: hogs@0 {
+ allwinner,pins = "PH19";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb2_vbus_pin_hackberry: usb2_vbus_pin@0 {
+ allwinner,pins = "PH12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ pinctrl-0 = <&usb2_vbus_pin_hackberry>;
+ gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Hyundai A7HD";
+ compatible = "hyundai,a7hd", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+®_usb2_vbus {
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb2_vbus_pin_a {
+ allwinner,pins = "PH6";
+};
+
+&usbphy {
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the iNet 3F for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+
+/ {
+ model = "iNet 3F";
+ compatible = "inet,3f", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the iNet 3W for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+
+/ {
+ model = "iNet 3W";
+ compatible = "inet,3w", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Open Source Support GmbH
+ *
+ * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "INet-97F Rev 02";
+ compatible = "primux,inet97fv2", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Gábor Nyers
+ *
+ * Gábor Nyers <gabor.nyers@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Jesurun Q5";
+ compatible = "jesurun,q5", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_q5>;
+
+ green {
+ label = "q5:green:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */
+ };
+
+ };
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_power_pin_q5>;
+ regulator-name = "emac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ phy-supply = <®_emac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ emac_power_pin_q5: emac_power_pin@0 {
+ allwinner,pins = "PH19";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_q5: led_pins@0 {
+ allwinner,pins = "PH20";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Aleksei Mamlin
+ * Aleksei Mamlin <mamlinav@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "HAOYU Electronics Marsboard A10";
+ compatible = "haoyu,a10-marsboard", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_marsboard>;
+
+ red1 {
+ label = "marsboard:red1:usr";
+ gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ red2 {
+ label = "marsboard:red2:usr";
+ gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ red3 {
+ label = "marsboard:red3:usr";
+ gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ red4 {
+ label = "marsboard:red4:usr";
+ gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_marsboard: led_pins@0 {
+ allwinner,pins = "PB5", "PB6", "PB7", "PB8";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "PineRiver Mini X-Plus";
+ compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&ir0_pins_a {
+ /* The ir receiver is not always populated */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "MK802";
+ compatible = "allwinner,mk802", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ usb2_vbus_pin_mk802: usb2_vbus_pin@0 {
+ allwinner,pins = "PH12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ pinctrl-0 = <&usb2_vbus_pin_mk802>;
+ gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "MK802ii";
+ compatible = "allwinner,mk802ii", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A10-OLinuXino-LIME";
+ compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxinolime>;
+
+ green {
+ label = "a10-olinuxino-lime:green:usr";
+ gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&cpu0 {
+ /*
+ * The A10-Lime is known to be unstable when running at 1008 MHz
+ */
+ operating-points = <
+ /* kHz uV */
+ 912000 1350000
+ 864000 1300000
+ 624000 1250000
+ >;
+ cooling-max-level = <2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+ allwinner,pins = "PC3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_olinuxinolime: led_pins@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+ gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "LinkSprite pcDuino";
+ compatible = "linksprite,a10-pcduino", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_pcduino>;
+
+ tx {
+ label = "pcduino:green:tx";
+ gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rx {
+ label = "pcduino:green:rx";
+ gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_pins_pcduino>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ label = "Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
+ };
+
+ button@1 {
+ label = "Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
+ };
+
+ button@2 {
+ label = "Key Menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_pcduino: led_pins@0 {
+ allwinner,pins = "PH15", "PH16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ key_pins_pcduino: key_pins@0 {
+ allwinner,pins = "PH17", "PH18", "PH19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Stefan Roese
+ * Stefan Roese <sr@denx.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/thermal/thermal.h>
+
+#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-hdmi";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+ <&ahb_gates 44>;
+ status = "disabled";
+ };
+
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+ <&ahb_gates 44>, <&ahb_gates 46>;
+ status = "disabled";
+ };
+
+ framebuffer@2 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_fe0-de_be0-lcd0";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
+ <&ahb_gates 46>;
+ status = "disabled";
+ };
+
+ framebuffer@3 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
+ clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
+ <&ahb_gates 44>, <&ahb_gates 46>;
+ status = "disabled";
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
+ clocks = <&cpu>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points = <
+ /* kHz uV */
+ 1008000 1400000
+ 912000 1350000
+ 864000 1300000
+ 624000 1250000
+ >;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <3>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&rtp>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ /* milliCelsius */
+ temperature = <850000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit {
+ /* milliCelsius */
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /*
+ * This is a dummy clock, to be used as placeholder on
+ * other mux clocks when a specific parent clock is not
+ * yet implemented. It should be dropped when the driver
+ * is complete.
+ */
+ dummy: dummy {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ osc24M: clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll4: clk@01c20018 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20018 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll5: clk@01c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ };
+
+ /* dummy is 200M */
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ axi_gates: clk@01c2005c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-axi-gates-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "axi_dram";
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "ahb";
+ };
+
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+ "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+ "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+ "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+ "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+ "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
+ };
+
+ apb1: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_can", "apb1_scr",
+ "apb1_ps20", "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2", "apb1_uart3",
+ "apb1_uart4", "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
+ };
+
+ nand_clk: clk@01c20080 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20080 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "nand";
+ };
+
+ ms_clk: clk@01c20084 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20084 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ms";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc3",
+ "mmc3_output",
+ "mmc3_sample";
+ };
+
+ ts_clk: clk@01c20098 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20098 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ts";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ss";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi2";
+ };
+
+ pata_clk: clk@01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "pata";
+ };
+
+ ir0_clk: clk@01c200b0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir0";
+ };
+
+ ir1_clk: clk@01c200b4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+ };
+
+ spi3_clk: clk@01c200d4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200d4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi3";
+ };
+ };
+
+ /*
+ * Note we use the address where the mmio registers start, not where
+ * the SRAM blocks start, this cannot be changed because that would be
+ * a devicetree ABI change.
+ */
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram@00000000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00000000 0x4000>;
+ allwinner,sram-name = "A1";
+ };
+
+ sram@00004000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00004000 0x4000>;
+ allwinner,sram-name = "A2";
+ };
+
+ sram@00008000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00008000 0x4000>;
+ allwinner,sram-name = "A3-A4";
+ };
+
+ sram@00010000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00010000 0x1000>;
+ allwinner,sram-name = "D";
+ };
+
+ sram-controller@01c00000 {
+ compatible = "allwinner,sun4i-a10-sram-controller";
+ reg = <0x01c00000 0x30>;
+ };
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun4i-a10-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <27>;
+ clocks = <&ahb_gates 6>;
+ #dma-cells = <2>;
+ };
+
+ spi0: spi@01c05000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 27>,
+ <&dma SUN4I_DMA_DEDICATED 26>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c06000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <11>;
+ clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 9>,
+ <&dma SUN4I_DMA_DEDICATED 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ clocks = <&ahb_gates 17>;
+ status = "disabled";
+ };
+
+ mdio: mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun4i-a10-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <32>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun4i-a10-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <33>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun4i-a10-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <34>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun4i-a10-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>,
+ <&mmc3_clk 0>,
+ <&mmc3_clk 1>,
+ <&mmc3_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <35>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy@01c13400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-phy";
+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+ reg-names = "phy_ctrl", "pmu1", "pmu2";
+ clocks = <&usb_clk 8>;
+ clock-names = "usb_phy";
+ resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+ reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c14000 {
+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
+ reg = <0x01c14000 0x100>;
+ interrupts = <39>;
+ clocks = <&ahb_gates 1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c14400 {
+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
+ reg = <0x01c14400 0x100>;
+ interrupts = <64>;
+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <12>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 29>,
+ <&dma SUN4I_DMA_DEDICATED 28>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ahci: sata@01c18000 {
+ compatible = "allwinner,sun4i-a10-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <56>;
+ clocks = <&pll6 0>, <&ahb_gates 25>;
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1c000 {
+ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <40>;
+ clocks = <&ahb_gates 3>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1c400 {
+ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <65>;
+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi3: spi@01c1f000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <50>;
+ clocks = <&ahb_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 31>,
+ <&dma SUN4I_DMA_DEDICATED 30>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ intc: interrupt-controller@01c20400 {
+ compatible = "allwinner,sun4i-a10-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun4i-a10-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <28>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ pwm0_pins_a: pwm0@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "pwm";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ pwm1_pins_a: pwm1@0 {
+ allwinner,pins = "PI3";
+ allwinner,function = "pwm";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB22", "PB23";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_b: uart0@1 {
+ allwinner,pins = "PF2", "PF4";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins_a: uart1@0 {
+ allwinner,pins = "PA10", "PA11";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PB18", "PB19";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PB20", "PB21";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ ir0_pins_a: ir0@0 {
+ allwinner,pins = "PB3","PB4";
+ allwinner,function = "ir0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ir1_pins_a: ir1@0 {
+ allwinner,pins = "PB22","PB23";
+ allwinner,function = "ir1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi0_pins_a: spi0@0 {
+ allwinner,pins = "PI10", "PI11", "PI12", "PI13";
+ allwinner,function = "spi0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi1_pins_a: spi1@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "spi1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ allwinner,pins = "PB14", "PB15", "PB16", "PB17";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi2_pins_b: spi2@1 {
+ allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ps20_pins_a: ps20@0 {
+ allwinner,pins = "PI20", "PI21";
+ allwinner,function = "ps2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ps21_pins_a: ps21@0 {
+ allwinner,pins = "PH12", "PH13";
+ allwinner,function = "ps2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <22>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@01c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ rtc: rtc@01c20d00 {
+ compatible = "allwinner,sun4i-a10-rtc";
+ reg = <0x01c20d00 0x20>;
+ interrupts = <24>;
+ };
+
+ pwm: pwm@01c20e00 {
+ compatible = "allwinner,sun4i-a10-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir0: ir@01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <5>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
+ ir1: ir@01c21c00 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 7>, <&ir1_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <6>;
+ reg = <0x01c21c00 0x40>;
+ status = "disabled";
+ };
+
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <31>;
+ status = "disabled";
+ };
+
+ sid: eeprom@01c23800 {
+ compatible = "allwinner,sun4i-a10-sid";
+ reg = <0x01c23800 0x10>;
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun4i-a10-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <29>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 16>;
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <17>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 20>;
+ status = "disabled";
+ };
+
+ uart5: serial@01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <18>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 21>;
+ status = "disabled";
+ };
+
+ uart6: serial@01c29800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29800 0x400>;
+ interrupts = <19>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 22>;
+ status = "disabled";
+ };
+
+ uart7: serial@01c29c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29c00 0x400>;
+ interrupts = <20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 23>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <7>;
+ clocks = <&apb1_gates 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <8>;
+ clocks = <&apb1_gates 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <9>;
+ clocks = <&apb1_gates 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ps20: ps2@01c2a000 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a000 0x400>;
+ interrupts = <62>;
+ clocks = <&apb1_gates 6>;
+ status = "disabled";
+ };
+
+ ps21: ps2@01c2a400 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a400 0x400>;
+ interrupts = <63>;
+ clocks = <&apb1_gates 7>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a10s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Auxtek t004 A10s hdmi tv-stick";
+ compatible = "allwinner,auxtek-t004", "allwinner,sun5i-a10s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_t004>;
+
+ red {
+ label = "t004-tv-dongle:red:usr";
+ gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
+ default-state = "on";
+ };
+ };
+
+ reg_vmmc1: vmmc1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_vcc_en_pin_t004>;
+ regulator-name = "vmmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 1 18 GPIO_ACTIVE_HIGH>; /* PB18 */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_vmmc1>;
+ bus-width = <4>;
+ non-removable;
+ cap-sdio-irq;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_t004: mmc0_cd_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 {
+ allwinner,pins = "PB18";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_t004: led_pins@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG13";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a10s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "MK802-A10s";
+ compatible = "allwinner,a10s-mk802", "allwinner,sun5i-a10s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_mk802>;
+
+ red {
+ label = "mk802:red:usr";
+ gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_mk802: led_pins@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_mk802: mmc0_cd_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb1_vbus_pin_mk802: usb1_vbus_pin@0 {
+ allwinner,pins = "PB10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_mk802>;
+ gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a10s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A10s-Olinuxino Micro";
+ compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxino>;
+
+ green {
+ label = "a10s-olinuxino-micro:green:usr";
+ gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_a>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c16";
+ pagesize = <16>;
+ reg = <0x50>;
+ read-only;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@191 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <191274>;
+ };
+
+ button@392 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <392644>;
+ };
+
+ button@601 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <601151>;
+ };
+
+ button@795 {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ channel = <0>;
+ voltage = <795090>;
+ };
+
+ button@987 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <987387>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
+ allwinner,pins = "PG13";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ led_pins_olinuxino: led_pins@0 {
+ allwinner,pins = "PE3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
+ allwinner,pins = "PB10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>;
+ gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_a>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
+
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a10s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "R7 A10s hdmi tv-stick";
+ compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_r7>;
+
+ green {
+ label = "r7-tv-dongle:green:usr";
+ gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_r7: mmc0_cd_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ led_pins_r7: led_pins@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_r7: usb1_vbus_pin@0 {
+ allwinner,pins = "PG13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_r7>;
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include "sun5i.dtsi"
+
+#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-hdmi";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+ <&ahb_gates 44>;
+ status = "disabled";
+ };
+
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ status = "disabled";
+ };
+ };
+
+ clocks {
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
+ "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
+ "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
+ "apb0_ir", "apb0_keypad";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3";
+ };
+ };
+
+ soc@01c00000 {
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <55>;
+ clocks = <&ahb_gates 17>;
+ status = "disabled";
+ };
+
+ mdio: mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <1>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 16>;
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ status = "disabled";
+ };
+ };
+};
+
+&pio {
+ compatible = "allwinner,sun5i-a10s-pinctrl";
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB19", "PB20";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart2_pins_a: uart2@0 {
+ allwinner,pins = "PC18", "PC19";
+ allwinner,function = "uart2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_a: uart3@0 {
+ allwinner,pins = "PG9", "PG10";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Ampe A76 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+
+/ {
+ model = "Ampe A76";
+ compatible = "ampe,a76", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Forfun Q88db for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+
+/ {
+ model = "Forfun Q88db";
+ compatible = "forfun,q88db", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "HSG H702";
+ compatible = "hsg,h702", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_h702: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the iNet 86VS for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+
+/ {
+ model = "iNet 86VS";
+ compatible = "inet,86vs", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
+ * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A13-Olinuxino Micro";
+ compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxinom>;
+
+ power {
+ label = "a13-olinuxino-micro:green:power";
+ gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ led_pins_olinuxinom: led_pins@0 {
+ allwinner,pins = "PG9";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
+ allwinner,pins = "PG11";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
+ gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A13-Olinuxino";
+ compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxino>;
+
+ power {
+ gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@191 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <191274>;
+ };
+
+ button@392 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <392644>;
+ };
+
+ button@601 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <601151>;
+ };
+
+ button@795 {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ channel = <0>;
+ voltage = <795090>;
+ };
+
+ button@987 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <987387>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ led_pins_olinuxino: led_pins@0 {
+ allwinner,pins = "PG9";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
+ allwinner,pins = "PG11";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
+ gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the TZX Q8 713b7 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+
+/ {
+ model = "TZX Q8 713b7";
+ compatible = "tzx,q8-713b7", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Utoo P66";
+ compatible = "utoo,p66", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ i2c_lcd: i2c@0 {
+ /* The lcd panel i2c interface is hooked up via gpios */
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_lcd_pins>;
+ gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */
+ <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */
+ i2c-gpio,delay-us = <5>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_p66>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+
+ mmccard: mmccard@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
+
+&pio {
+ mmc0_cd_pin_p66: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ i2c_lcd_pins: i2c_lcd_pin@0 {
+ allwinner,pins = "PG10", "PG12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_pin_a: usb0_vbus_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include "sun5i.dtsi"
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ status = "disabled";
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&rtp>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ /* milliCelsius */
+ temperature = <850000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit {
+ /* milliCelsius */
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ clocks {
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+ "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
+ "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
+ "ahb_de_fe", "ahb_iep", "ahb_mali400";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_uart1", "apb1_uart3";
+ };
+ };
+};
+
+&cpu0 {
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points = <
+ /* kHz uV */
+ 1008000 1400000
+ 912000 1350000
+ 864000 1300000
+ 624000 1200000
+ 576000 1200000
+ 432000 1200000
+ >;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <5>;
+};
+
+&pio {
+ compatible = "allwinner,sun5i-a13-pinctrl";
+
+ uart1_pins_a: uart1@0 {
+ allwinner,pins = "PE10", "PE11";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_pins_b: uart1@1 {
+ allwinner,pins = "PG3", "PG4";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
--- /dev/null
+/*
+ * Copyright 2012-2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
+ clocks = <&cpu>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /*
+ * This is a dummy clock, to be used as placeholder on
+ * other mux clocks when a specific parent clock is not
+ * yet implemented. It should be dropped when the driver
+ * is complete.
+ */
+ dummy: dummy {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ osc24M: clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll4: clk@01c20018 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20018 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll5: clk@01c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ };
+
+ /* dummy is 200M */
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "ahb";
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ clock-output-names = "apb0";
+ };
+
+ apb1: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+ clock-output-names = "apb1";
+ };
+
+ axi_gates: clk@01c2005c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-axi-gates-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "axi_dram";
+ };
+
+ nand_clk: clk@01c20080 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20080 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "nand";
+ };
+
+ ms_clk: clk@01c20084 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20084 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ms";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ ts_clk: clk@01c20098 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20098 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ts";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ss";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi2";
+ };
+
+ ir0_clk: clk@01c200b0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir0";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun5i-a13-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_phy";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun5i-a13-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mbus";
+ };
+ };
+
+ /*
+ * Note we use the address where the mmio registers start, not where
+ * the SRAM blocks start, this cannot be changed because that would be
+ * a devicetree ABI change.
+ */
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram@00000000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00000000 0x4000>;
+ allwinner,sram-name = "A1";
+ };
+
+ sram@00004000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00004000 0x4000>;
+ allwinner,sram-name = "A2";
+ };
+
+ sram@00008000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00008000 0x4000>;
+ allwinner,sram-name = "A3-A4";
+ };
+
+ sram@00010000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00010000 0x1000>;
+ allwinner,sram-name = "D";
+ };
+
+ sram-controller@01c00000 {
+ compatible = "allwinner,sun4i-a10-sram-controller";
+ reg = <0x01c00000 0x30>;
+ };
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun4i-a10-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <27>;
+ clocks = <&ahb_gates 6>;
+ #dma-cells = <2>;
+ };
+
+ spi0: spi@01c05000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 27>,
+ <&dma SUN4I_DMA_DEDICATED 26>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c06000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <11>;
+ clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 9>,
+ <&dma SUN4I_DMA_DEDICATED 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <32>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <33>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <34>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy@01c13400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun5i-a13-usb-phy";
+ reg = <0x01c13400 0x10 0x01c14800 0x4>;
+ reg-names = "phy_ctrl", "pmu1";
+ clocks = <&usb_clk 8>;
+ clock-names = "usb_phy";
+ resets = <&usb_clk 0>, <&usb_clk 1>;
+ reset-names = "usb0_reset", "usb1_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c14000 {
+ compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
+ reg = <0x01c14000 0x100>;
+ interrupts = <39>;
+ clocks = <&ahb_gates 1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c14400 {
+ compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
+ reg = <0x01c14400 0x100>;
+ interrupts = <40>;
+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <12>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 29>,
+ <&dma SUN4I_DMA_DEDICATED 28>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ intc: interrupt-controller@01c20400 {
+ compatible = "allwinner,sun4i-a10-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pio: pinctrl@01c20800 {
+ reg = <0x01c20800 0x400>;
+ interrupts = <28>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PB15", "PB16";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PB17", "PB18";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12", "PC13",
+ "PC14", "PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <22>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@01c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <31>;
+ status = "disabled";
+ };
+
+ sid: eeprom@01c23800 {
+ compatible = "allwinner,sun4i-a10-sid";
+ reg = <0x01c23800 0x10>;
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun5i-a13-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <29>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <7>;
+ clocks = <&apb1_gates 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <8>;
+ clocks = <&apb1_gates 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <9>;
+ clocks = <&apb1_gates 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer@01c60000 {
+ compatible = "allwinner,sun5i-a13-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <82>, <83>;
+ clocks = <&ahb_gates 28>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Boris Brezillon
+ *
+ * Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Allwinner A31 APP4 EVB1 Evaluation Board";
+ compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&pio {
+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
+ allwinner,pins = "PH27";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_a>;
+ gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "WITS A31 Colombus Evaluation Board";
+ compatible = "wits,colombus", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "fail";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&pio {
+ mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
+ allwinner,pins = "PA8";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
+ allwinner,pins = "PH24";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb2_vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_pin_colombus>;
+ gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Merrii A31 Hummingbird";
+ compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ /* pull-ups and devices require AXP221 DLDO3 */
+ status = "failed";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
+ vmmc-supply = <&vcc_3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ /* external pull-ups missing for some pins */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>;
+ vmmc-supply = <&vcc_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
+ allwinner,pins = "PA8";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ wifi_reset_pin_hummingbird: wifi_reset_pin@0 {
+ allwinner,pins = "PG10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp221: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ dcdc1-supply = <&vcc_3v0>;
+ dcdc5-supply = <&vcc_dram>;
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ vcc_3v0: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ vdd_gpu: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ vdd_sys_dll: dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys-dll";
+ };
+
+ vcc_dram: dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+ };
+
+ vcc_wifi: aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+
+ avcc: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+ };
+ };
+ };
+};
+
+®_usb1_vbus {
+ gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ /* different pin from sunxi-common-regulators */
+ allwinner,pins = "PH24";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Marcus Cooper <codekipper@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Mele I7 Quad top set box";
+ compatible = "mele,i7", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_i7>;
+
+ blue {
+ label = "i7:blue:usr";
+ gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ led_pins_i7: led_pins@0 {
+ allwinner,pins = "PH13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_i7: mmc0_cd_pin@0 {
+ allwinner,pins = "PH22";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb1_vbus_pin_i7: usb1_vbus_pin@0 {
+ allwinner,pins = "PC27";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_pin_i7>;
+ gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Mele M9 / A1000G Quad top set box";
+ compatible = "mele,m9", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_m9>;
+
+ blue {
+ label = "m9:blue:usr";
+ gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ led_pins_m9: led_pins@0 {
+ allwinner,pins = "PH13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_m9: mmc0_cd_pin@0 {
+ allwinner,pins = "PH22";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb1_vbus_pin_m9: usb1_vbus_pin@0 {
+ allwinner,pins = "PC27";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_pin_m9>;
+ gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Mixtile LOFT-Q for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+
+/ {
+ model = "Mixtile LOFT-Q";
+ compatible = "mixtile,loft-q", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ ethernet0 = &gmac;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-hdmi";
+ clocks = <&pll6 0>;
+ status = "disabled";
+ };
+
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&pll6 0>;
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ cpus {
+ enable-method = "allwinner,sun6i-a31";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&cpu>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points = <
+ /* kHz uV */
+ 1008000 1200000
+ 864000 1200000
+ 720000 1100000
+ 480000 1000000
+ >;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <3>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&rtp>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ /* milliCelsius */
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit {
+ /* milliCelsius */
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2";
+ };
+
+ cpu: cpu@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+
+ /*
+ * PLL1 is listed twice here.
+ * While it looks suspicious, it's actually documented
+ * that way both in the datasheet and in the code from
+ * Allwinner.
+ */
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_ss",
+ "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
+ "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
+ "ahb1_nand0", "ahb1_sdram",
+ "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
+ "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
+ "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
+ "ahb1_ehci1", "ahb1_ohci0",
+ "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
+ "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
+ "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
+ "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
+ "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
+ "ahb1_drc0", "ahb1_drc1";
+ };
+
+ apb1: apb1@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb1-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_codec", "apb1_digital_mic",
+ "apb1_pio", "apb1_daudio0",
+ "apb1_daudio1";
+ };
+
+ apb2: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+ clock-output-names = "apb2";
+ };
+
+ apb2_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb2-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb2>;
+ clock-output-names = "apb2_i2c0", "apb2_i2c1",
+ "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
+ "apb2_uart1", "apb2_uart2", "apb2_uart3",
+ "apb2_uart4", "apb2_uart5";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc3",
+ "mmc3_output",
+ "mmc3_sample";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "spi2";
+ };
+
+ spi3_clk: clk@01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "spi3";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
+ "usb_ohci0", "usb_ohci1",
+ "usb_ohci2";
+ };
+
+ /*
+ * The following two are dummy clocks, placeholders used in the gmac_tx
+ * clock. The gmac driver will choose one parent depending on the PHY
+ * interface mode, using clk_set_rate auto-reparenting.
+ * The actual TX clock rate is not controlled by the gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk@1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@01c200d0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x01c200d0 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun6i-a31-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 6>;
+ resets = <&ahb1_rst 6>;
+ #dma-cells = <1>;
+
+ /* DMA controller requires AHB1 clocked from PLL6 */
+ assigned-clocks = <&ahb1>;
+ assigned-clock-parents = <&pll6 0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb1_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb1_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb1_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb1_gates 11>,
+ <&mmc3_clk 0>,
+ <&mmc3_clk 1>,
+ <&mmc3_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 11>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbphy: phy@01c19400 {
+ compatible = "allwinner,sun6i-a31-usb-phy";
+ reg = <0x01c19400 0x10>,
+ <0x01c1a800 0x4>,
+ <0x01c1b800 0x4>;
+ reg-names = "phy_ctrl",
+ "pmu1",
+ "pmu2";
+ clocks = <&usb_clk 8>,
+ <&usb_clk 9>,
+ <&usb_clk 10>;
+ clock-names = "usb0_phy",
+ "usb1_phy",
+ "usb2_phy";
+ resets = <&usb_clk 0>,
+ <&usb_clk 1>,
+ <&usb_clk 2>;
+ reset-names = "usb0_reset",
+ "usb1_reset",
+ "usb2_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 26>;
+ resets = <&ahb1_rst 26>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 29>, <&usb_clk 16>;
+ resets = <&ahb1_rst 29>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1b000 {
+ compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+ reg = <0x01c1b000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 27>;
+ resets = <&ahb1_rst 27>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1b400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1b400 0x100>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 30>, <&usb_clk 17>;
+ resets = <&ahb1_rst 30>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@01c1c400 {
+ compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 31>, <&usb_clk 18>;
+ resets = <&ahb1_rst 31>;
+ status = "disabled";
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun6i-a31-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PH14", "PH15";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PH16", "PH17";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PH18", "PH19";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA8", "PA9", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA26", "PA27";
+ allwinner,function = "gmac";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_pins_gmii_a: gmac_gmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA4", "PA5", "PA6", "PA7",
+ "PA8", "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA15",
+ "PA16", "PA17", "PA18", "PA19",
+ "PA20", "PA21", "PA22", "PA23",
+ "PA24", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in GMII mode run at 125MHz and
+ * might need a higher signal drive strength
+ */
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+ "PA9", "PA10", "PA11",
+ "PA12", "PA13", "PA14", "PA19",
+ "PA20", "PA25", "PA26", "PA27";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ ahb1_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt1: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun6i-a31-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 16>;
+ resets = <&apb2_rst 16>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 17>;
+ resets = <&apb2_rst 17>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 18>;
+ resets = <&apb2_rst 18>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 19>;
+ resets = <&apb2_rst 19>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 20>;
+ resets = <&apb2_rst 20>;
+ dmas = <&dma 10>, <&dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 21>;
+ resets = <&apb2_rst 21>;
+ dmas = <&dma 22>, <&dma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 0>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 1>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 2>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@01c2b800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 3>;
+ resets = <&apb2_rst 3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac: ethernet@01c30000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c30000 0x1054>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ resets = <&ahb1_rst 17>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer@01c60000 {
+ compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1_rst 19>;
+ };
+
+ spi0: spi@01c68000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 20>;
+ status = "disabled";
+ };
+
+ spi1: spi@01c69000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 21>;
+ status = "disabled";
+ };
+
+ spi2: spi@01c6a000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6a000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 25>, <&dma 25>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 22>;
+ status = "disabled";
+ };
+
+ spi3: spi@01c6b000 {
+ compatible = "allwinner,sun6i-a31-spi";
+ reg = <0x01c6b000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 26>, <&dma 26>;
+ dma-names = "rx", "tx";
+ resets = <&ahb1_rst 23>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ nmi_intc: interrupt-controller@01f00c0c {
+ compatible = "allwinner,sun6i-a31-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01f00c0c 0x38>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ prcm@01f01400 {
+ compatible = "allwinner,sun6i-a31-prcm";
+ reg = <0x01f01400 0x200>;
+
+ ar100: ar100_clk {
+ compatible = "allwinner,sun6i-a31-ar100-clk";
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+ clock-output-names = "ar100";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&ar100>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: apb0_clk {
+ compatible = "allwinner,sun6i-a31-apb0-clk";
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible = "allwinner,sun6i-a31-apb0-gates-clk";
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_pio", "apb0_ir",
+ "apb0_timer", "apb0_p2wi",
+ "apb0_uart", "apb0_1wire",
+ "apb0_i2c";
+ };
+
+ ir_clk: ir_clk {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpucfg@01f01c00 {
+ compatible = "allwinner,sun6i-a31-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
+
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_rst 1>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun6i-a31-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_rst 0>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ ir_pins_a: ir@0 {
+ allwinner,pins = "PL4";
+ allwinner,function = "s_ir";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ p2wi_pins: p2wi {
+ allwinner,pins = "PL0", "PL1";
+ allwinner,function = "s_p2wi";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ p2wi: i2c@01f03400 {
+ compatible = "allwinner,sun6i-a31-p2wi";
+ reg = <0x01f03400 0x400>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 3>;
+ clock-frequency = <100000>;
+ resets = <&apb0_rst 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&p2wi_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31s.dtsi"
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "CSQ CS908 top set box";
+ compatible = "csq,cs908", "allwinner,sun6i-a31s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the MSI Primo81 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun6i-a31s.dtsi"
+
+/ {
+ model = "MSI Primo81";
+ compatible = "msi,primo81", "allwinner,sun6i-a31s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The A31s is the same die as the A31 in a different package, this is
+ * reflected by it having different pinctrl compatible everything else is
+ * identical.
+ */
+
+#include "sun6i-a31.dtsi"
+
+&pio {
+ compatible = "allwinner,sun6i-a31s-pinctrl";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Ainol AW1 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+
+/ {
+ model = "Ainol AW1";
+ compatible = "ainol,aw1", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "LeMaker Banana Pi";
+ compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart3;
+ serial2 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_bananapi>;
+
+ green {
+ label = "bananapi:green:usr";
+ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_bananapi>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
+ allwinner,pins = "PH10";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ gmac_power_pin_bananapi: gmac_power_pin@0 {
+ allwinner,pins = "PH23";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_bananapi: led_pins@0 {
+ allwinner,pins = "PH24";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_b>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "LeMaker Banana Pro";
+ compatible = "lemaker,bananapro", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart2;
+ serial2 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_bananapro>;
+
+ blue {
+ label = "bananapro:blue:usr";
+ gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "bananapro:green:usr";
+ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_bananapro>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vmmc3: vmmc3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc3_pin_bananapro>;
+ regulator-name = "vmmc3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapro>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vmmc3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ gmac_power_pin_bananapro: gmac_power_pin@0 {
+ allwinner,pins = "PH23";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_bananapro: led_pins@0 {
+ allwinner,pins = "PH24", "PG2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_bananapro: mmc0_cd_pin@0 {
+ allwinner,pins = "PH10";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
+ allwinner,pins = "PH0";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ vmmc3_pin_bananapro: vmmc3_pin@0 {
+ allwinner,pins = "PH22";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_bananapro>;
+ gpio = <&pio 7 0 GPIO_ACTIVE_HIGH>; /* PH0 */
+ status = "okay";
+};
+
+®_usb2_vbus {
+ pinctrl-0 = <&usb2_vbus_pin_bananapro>;
+ gpio = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_a>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Cubietech Cubieboard2";
+ compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_cubieboard2>;
+
+ blue {
+ label = "cubieboard2:blue:usr";
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "cubieboard2:green:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_cubieboard2: led_pins@0 {
+ allwinner,pins = "PH20", "PH21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Oliver Schinagl
+ *
+ * Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Cubietech Cubietruck";
+ compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_cubietruck>;
+
+ blue {
+ label = "cubietruck:blue:usr";
+ gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ orange {
+ label = "cubietruck:orange:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ white {
+ label = "cubietruck:white:usr";
+ gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "cubietruck:green:usr";
+ gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vmmc3: vmmc3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc3_pin_cubietruck>;
+ regulator-name = "vmmc3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vmmc3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc3_pins_a {
+ /* AP6210 requires pull-up */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vmmc3_pin_cubietruck: vmmc3_pin@0 {
+ allwinner,pins = "PH9";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
+ allwinner,pins = "PH12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_cubietruck: led_pins@0 {
+ allwinner,pins = "PH7", "PH11", "PH20", "PH21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_vbus_pin_a: usb0_vbus_pin@0 {
+ allwinner,pins = "PH17";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>;
+ status = "okay";
+};
+
+®_ahci_5v {
+ pinctrl-0 = <&ahci_pwr_pin_cubietruck>;
+ gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ pinctrl-0 = <&usb0_vbus_pin_a>;
+ gpio = <&pio 7 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Wills Wang
+ *
+ * Wills Wang <wills.wang.open@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Merrii A20 Hummingbird";
+ compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_mmc3_vdd: mmc3_vdd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>;
+ regulator-name = "mmc3_vdd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ enable-active-high;
+ gpio = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ };
+
+ reg_gmac_vdd: gmac_vdd {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>;
+ regulator-name = "gmac_vdd";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ enable-active-high;
+ gpio = <&pio 7 16 GPIO_ACTIVE_HIGH>; /* PH16 */
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_vdd>;
+ /* phy reset config */
+ snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
+ snps,reset-active-low;
+ /* wait 1s after reset, otherwise fail to read phy id */
+ snps,reset-delays-us = <0 10000 1000000>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_mmc3_vdd>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 {
+ allwinner,pins = "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 {
+ allwinner,pins = "PH9";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 {
+ allwinner,pins = "PH16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ status = "okay";
+};
+
+®_ahci_5v {
+ pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>;
+ gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+ status = "okay";
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>;
+ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_b>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins_a>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins_a>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "I12 / Q5 / QT840A A20 tvbox";
+ compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_i12_tvbox>;
+
+ red {
+ label = "i12_tvbox:red:usr";
+ gpios = <&pio 7 9 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ label = "i12_tvbox:blue:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vmmc3: vmmc3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc3_pin_i12_tvbox>;
+ regulator-name = "vmmc3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vmmc3_io: vmmc3-io {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>;
+ regulator-name = "vmmc3-io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ /* This controls VCC-PI, must be always on! */
+ regulator-always-on;
+ enable-active-high;
+ gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_i12_tvbox>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ enable-active-high;
+ gpio = <&pio 7 21 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vmmc3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc3_pins_a {
+ /* AP6210 / AP6330 requires pull-up */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vmmc3_pin_i12_tvbox: vmmc3_pin@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 {
+ allwinner,pins = "PH12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_power_pin_i12_tvbox: gmac_power_pin@0 {
+ allwinner,pins = "PH21";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_i12_tvbox: led_pins@0 {
+ allwinner,pins = "PH9", "PH20";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Mele M3";
+ compatible = "mele,m3", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_m3>;
+
+ blue {
+ label = "m3:blue:usr";
+ gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_m3: led_pins@0 {
+ allwinner,pins = "PH20";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Mele M5 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+
+/ {
+ model = "Mele M5";
+ compatible = "mele,m5", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the MK808C for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+
+/ {
+ model = "MK808C";
+ compatible = "allwinner,mk808c", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * This is based on sun4i-a10-olinuxino-lime.dts
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A20-OLinuXino-LIME";
+ compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxinolime>;
+
+ green {
+ label = "a20-olinuxino-lime:green:usr";
+ gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+ allwinner,pins = "PC3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_olinuxinolime: led_pins@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+ gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 - Iain Paton <ipaton0@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A20-OLinuXino-LIME2";
+ compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxinolime>;
+
+ green {
+ label = "a20-olinuxino-lime2:green:usr";
+ gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_axp_ipsout: axp_ipsout {
+ compatible = "regulator-fixed";
+ regulator-name = "axp-ipsout";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ acin-supply = <®_axp_ipsout>;
+ vin2-supply = <®_axp_ipsout>;
+ vin3-supply = <®_axp_ipsout>;
+ ldo24in-supply = <®_axp_ipsout>;
+ ldo3in-supply = <®_axp_ipsout>;
+
+ regulators {
+ vdd_rtc: ldo1 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+
+ avcc: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vcc_csi0: ldo3 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-always-on;
+ };
+
+ vcc_csi1: ldo4 {
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <2275000>;
+ regulator-always-on;
+ };
+
+ vdd_int: dcdc3 {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3500000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
+ allwinner,pins = "PC3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_olinuxinolime: led_pins@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
+ gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Olimex A20-Olinuxino Micro";
+ compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart6;
+ serial2 = &uart7;
+ spi0 = &spi1;
+ spi1 = &spi2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_olinuxino>;
+
+ green {
+ label = "a20-olinuxino-micro:green:usr";
+ gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@191 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <191274>;
+ };
+
+ button@392 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <392644>;
+ };
+
+ button@601 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <601151>;
+ };
+
+ button@795 {
+ label = "Search";
+ linux,code = <KEY_SEARCH>;
+ channel = <0>;
+ voltage = <795090>;
+ };
+
+ button@987 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <987387>;
+ };
+
+ button@1184 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1184678>;
+ };
+
+ button@1398 {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ channel = <0>;
+ voltage = <1398804>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
+ allwinner,pins = "PH11";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ led_pins_olinuxino: led_pins@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pins_a>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Orange Pi Mini";
+ compatible = "xunlong,orangepi-mini", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_orangepi>;
+
+ green {
+ label = "orangepi:green:usr";
+ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+ };
+
+ blue {
+ label = "orangepi:blue:usr";
+ gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_orangepi>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_orangepi>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
+ allwinner,pins = "PH10";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc3_cd_pin_orangepi: mmc3_cd_pin@0 {
+ allwinner,pins = "PH11";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
+ allwinner,pins = "PH22";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_power_pin_orangepi: gmac_power_pin@0 {
+ allwinner,pins = "PH23";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_orangepi: led_pins@0 {
+ allwinner,pins = "PH24", "PH25";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
+ allwinner,pins = "PH26";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_bananapro>;
+ gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
+ status = "okay";
+};
+
+®_usb2_vbus {
+ pinctrl-0 = <&usb2_vbus_pin_bananapro>;
+ gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Orange Pi";
+ compatible = "xunlong,orangepi", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_orangepi>;
+
+ green {
+ label = "orangepi:green:usr";
+ gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_power_pin_orangepi>;
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ };
+};
+
+&ahci {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ phy-supply = <®_gmac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_orangepi>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_orangepi: mmc0_cd_pin@0 {
+ allwinner,pins = "PH10";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb2_vbus_pin_bananapro: usb2_vbus_pin@0 {
+ allwinner,pins = "PH22";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ gmac_power_pin_orangepi: gmac_power_pin@0 {
+ allwinner,pins = "PH23";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_orangepi: led_pins@0 {
+ allwinner,pins = "PH24";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_bananapro: usb1_vbus_pin@0 {
+ allwinner,pins = "PH26";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_bananapro>;
+ gpio = <&pio 7 26 GPIO_ACTIVE_HIGH>; /* PH26 */
+ status = "okay";
+};
+
+®_usb2_vbus {
+ pinctrl-0 = <&usb2_vbus_pin_bananapro>;
+ gpio = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Adam Sampson <ats@offog.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "LinkSprite pcDuino3 Nano";
+ compatible = "linksprite,pcduino3-nano", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_pcduino3_nano>;
+
+ /* Marked "LED3" on the PCB. */
+ usr1 {
+ label = "pcduino3-nano:green:usr1";
+ gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */
+ };
+
+ /* Marked "LED4" on the PCB. */
+ usr2 {
+ label = "pcduino3-nano:green:usr2";
+ gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ ahci_pwr_pin_pcduino3_nano: ahci_pwr_pin@0 {
+ allwinner,pins = "PH2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ led_pins_pcduino3_nano: led_pins@0 {
+ allwinner,pins = "PH16", "PH15";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
+ allwinner,pins = "PH11";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+®_ahci_5v {
+ pinctrl-0 = <&ahci_pwr_pin_pcduino3_nano>;
+ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ status = "okay";
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_pcduino3_nano>;
+ gpio = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
* Copyright 2014 Zoltan HERPAI
* Zoltan HERPAI <wigyori@uid0.hu>
*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
*
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
-/include/ "sun7i-a20.dtsi"
-/include/ "sunxi-common-regulators.dtsi"
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
model = "LinkSprite pcDuino3";
compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
- chosen {
- stdout-path = &uart0;
+ aliases {
+ serial0 = &uart0;
};
- soc@01c00000 {
- mmc0: mmc@01c0f000 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 7 1 0>; /* PH1 */
- cd-inverted;
- status = "okay";
- };
-
- usbphy: phy@01c13400 {
- usb1_vbus-supply = <®_usb1_vbus>;
- usb2_vbus-supply = <®_usb2_vbus>;
- status = "okay";
- };
-
- ehci0: usb@01c14000 {
- status = "okay";
- };
-
- ohci0: usb@01c14400 {
- status = "okay";
- };
-
- ahci: sata@01c18000 {
- target-supply = <®_ahci_5v>;
- status = "okay";
- };
-
- ehci1: usb@01c1c000 {
- status = "okay";
- };
-
- ohci1: usb@01c1c400 {
- status = "okay";
- };
-
- pinctrl@01c20800 {
- ahci_pwr_pin_a: ahci_pwr_pin@0 {
- allwinner,pins = "PH2";
- };
-
- led_pins_pcduino3: led_pins@0 {
- allwinner,pins = "PH15", "PH16";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
-
- key_pins_pcduino3: key_pins@0 {
- allwinner,pins = "PH17", "PH18", "PH19";
- allwinner,function = "gpio_in";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
- };
-
- ir0: ir@01c21800 {
- pinctrl-names = "default";
- pinctrl-0 = <&ir0_pins_a>;
- status = "okay";
- };
-
- uart0: serial@01c28000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
- };
-
- i2c0: i2c@01c2ac00 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-
- axp209: pmic@34 {
- compatible = "x-powers,axp209";
- reg = <0x34>;
- interrupt-parent = <&nmi_intc>;
- interrupts = <0 8>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- };
-
- gmac: ethernet@01c50000 {
- pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
- phy-mode = "mii";
- status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
+ chosen {
+ stdout-path = "serial0:115200n8";
};
leds {
gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
};
};
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&ahci_pwr_pin_a {
+ allwinner,pins = "PH2";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
- reg_usb1_vbus: usb1-vbus {
- status = "okay";
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
};
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
- reg_usb2_vbus: usb2-vbus {
- status = "okay";
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_pcduino3: led_pins@0 {
+ allwinner,pins = "PH15", "PH16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- reg_ahci_5v: ahci-5v {
- gpio = <&pio 7 2 0>;
- status = "okay";
+ key_pins_pcduino3: key_pins@0 {
+ allwinner,pins = "PH17", "PH18", "PH19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
+
+®_ahci_5v {
+ gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Siarhei Siamashka <siarhei.siamashka@xxxxxxxxx>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "MSI Primo73 tablet";
+ compatible = "msi,primo73", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+ };
+
+ usbphy: phy@01c13400 {
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+ };
+
+ ehci1: usb@01c1c000 {
+ /* rtl8188etv wifi is connected here */
+ status = "okay";
+ };
+
+ pinctrl@01c20800 {
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = "PH12";
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ gpio = <&pio 7 12 0>; /* PH12 */
+ status = "okay";
+ };
+};
--- /dev/null
+/*
+ * Copyright 2015 Aleksei Mamlin
+ * Aleksei Mamlin <mamlinav@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "Wexler TAB7200";
+ compatible = "wexler,tab7200", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@571 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <571428>;
+ };
+
+ button@761 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <761904>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Wits Pro A20 DKT for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+
+/ {
+ model = "Wits Pro A20 DKT";
+ compatible = "wits,pro-a20-dkt", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Yones Toptech BD1078 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+
+/ {
+ model = "Yones Toptech BD1078";
+ compatible = "yones,toptech-bd1078", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
*
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*/
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
interrupt-parent = <&gic>;
aliases {
ethernet0 = &gmac;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- serial5 = &uart5;
- serial6 = &uart6;
- serial7 = &uart7;
+ };
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-hdmi";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
+ <&ahb_gates 44>;
+ status = "disabled";
+ };
+
+ framebuffer@1 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ status = "disabled";
+ };
+
+ framebuffer@2 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-tve0";
+ clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
+ <&ahb_gates 44>;
+ status = "disabled";
+ };
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
+ clocks = <&cpu>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points = <
+ /* kHz uV */
+ 960000 1400000
+ 912000 1400000
+ 864000 1300000
+ 720000 1200000
+ 528000 1100000
+ 312000 1000000
+ 144000 900000
+ >;
+ #cooling-cells = <2>;
+ cooling-min-level = <0>;
+ cooling-max-level = <6>;
};
cpu@1 {
};
};
+ thermal-zones {
+ cpu_thermal {
+ /* milliseconds */
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&rtp>;
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ /* milliCelsius */
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit {
+ /* milliCelsius */
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
memory {
reg = <0x40000000 0x80000000>;
};
timer {
compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
- interrupts = <0 120 4>,
- <0 121 4>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
};
clocks {
"apb0_iis2", "apb0_keypad";
};
- apb1_mux: apb1_mux@01c20058 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb1-mux-clk";
- reg = <0x01c20058 0x4>;
- clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
- clock-output-names = "apb1_mux";
- };
-
- apb1: apb1@01c20058 {
+ apb1: clk@01c20058 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-apb1-clk";
reg = <0x01c20058 0x4>;
- clocks = <&apb1_mux>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
clock-output-names = "apb1";
};
};
mmc0_clk: clk@01c20088 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc0";
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
};
mmc1_clk: clk@01c2008c {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc1";
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
};
mmc2_clk: clk@01c20090 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc2";
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
};
mmc3_clk: clk@01c20094 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20094 0x4>;
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
- clock-output-names = "mmc3";
+ clock-output-names = "mmc3",
+ "mmc3_output",
+ "mmc3_sample";
};
ts_clk: clk@01c20098 {
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-mod0-clk";
+ compatible = "allwinner,sun5i-a13-mbus-clk";
reg = <0x01c2015c 0x4>;
clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
clock-output-names = "mbus";
};
};
+ /*
+ * Note we use the address where the mmio registers start, not where
+ * the SRAM blocks start, this cannot be changed because that would be
+ * a devicetree ABI change.
+ */
soc@01c00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ sram@00000000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00000000 0x4000>;
+ allwinner,sram-name = "A1";
+ };
+
+ sram@00004000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00004000 0x4000>;
+ allwinner,sram-name = "A2";
+ };
+
+ sram@00008000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00008000 0x4000>;
+ allwinner,sram-name = "A3-A4";
+ };
+
+ sram@00010000 {
+ compatible = "allwinner,sun4i-a10-sram";
+ reg = <0x00010000 0x1000>;
+ allwinner,sram-name = "D";
+ };
+
+ sram-controller@01c00000 {
+ compatible = "allwinner,sun4i-a10-sram-controller";
+ reg = <0x01c00000 0x30>;
+ };
+
nmi_intc: interrupt-controller@01c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x01c00030 0x0c>;
- interrupts = <0 0 4>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun4i-a10-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb_gates 6>;
+ #dma-cells = <2>;
};
spi0: spi@01c05000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c05000 0x1000>;
- interrupts = <0 10 4>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 20>, <&spi0_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 27>,
+ <&dma SUN4I_DMA_DEDICATED 26>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
spi1: spi@01c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
- interrupts = <0 11 4>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 9>,
+ <&dma SUN4I_DMA_DEDICATED 8>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
emac: ethernet@01c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
- interrupts = <0 55 4>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 17>;
status = "disabled";
};
- mdio@01c0b080 {
+ mdio: mdio@01c0b080 {
compatible = "allwinner,sun4i-a10-mdio";
reg = <0x01c0b080 0x14>;
status = "disabled";
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
- clocks = <&ahb_gates 8>, <&mmc0_clk>;
- clock-names = "ahb", "mmc";
- interrupts = <0 32 4>;
+ clocks = <&ahb_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
mmc1: mmc@01c10000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c10000 0x1000>;
- clocks = <&ahb_gates 9>, <&mmc1_clk>;
- clock-names = "ahb", "mmc";
- interrupts = <0 33 4>;
+ clocks = <&ahb_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
mmc2: mmc@01c11000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c11000 0x1000>;
- clocks = <&ahb_gates 10>, <&mmc2_clk>;
- clock-names = "ahb", "mmc";
- interrupts = <0 34 4>;
+ clocks = <&ahb_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
mmc3: mmc@01c12000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c12000 0x1000>;
- clocks = <&ahb_gates 11>, <&mmc3_clk>;
- clock-names = "ahb", "mmc";
- interrupts = <0 35 4>;
+ clocks = <&ahb_gates 11>,
+ <&mmc3_clk 0>,
+ <&mmc3_clk 1>,
+ <&mmc3_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
usbphy: phy@01c13400 {
reg-names = "phy_ctrl", "pmu1", "pmu2";
clocks = <&usb_clk 8>;
clock-names = "usb_phy";
- resets = <&usb_clk 1>, <&usb_clk 2>;
- reset-names = "usb1_reset", "usb2_reset";
+ resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+ reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
status = "disabled";
};
ehci0: usb@01c14000 {
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
reg = <0x01c14000 0x100>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 1>;
phys = <&usbphy 1>;
phy-names = "usb";
ohci0: usb@01c14400 {
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
reg = <0x01c14400 0x100>;
- interrupts = <0 64 4>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk 6>, <&ahb_gates 2>;
phys = <&usbphy 1>;
phy-names = "usb";
spi2: spi@01c17000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c17000 0x1000>;
- interrupts = <0 12 4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 22>, <&spi2_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 29>,
+ <&dma SUN4I_DMA_DEDICATED 28>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
ahci: sata@01c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
- interrupts = <0 56 4>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pll6 0>, <&ahb_gates 25>;
status = "disabled";
};
ehci1: usb@01c1c000 {
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
reg = <0x01c1c000 0x100>;
- interrupts = <0 40 4>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 3>;
phys = <&usbphy 2>;
phy-names = "usb";
ohci1: usb@01c1c400 {
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk 7>, <&ahb_gates 4>;
phys = <&usbphy 2>;
phy-names = "usb";
spi3: spi@01c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
- interrupts = <0 50 4>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 23>, <&spi3_clk>;
clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 31>,
+ <&dma SUN4I_DMA_DEDICATED 30>;
+ dma-names = "rx", "tx";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
pio: pinctrl@01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
- interrupts = <0 28 4>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 5>;
gpio-controller;
interrupt-controller;
pwm0_pins_a: pwm0@0 {
allwinner,pins = "PB2";
allwinner,function = "pwm";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
pwm1_pins_a: pwm1@0 {
allwinner,pins = "PI3";
allwinner,function = "pwm";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart0_pins_a: uart0@0 {
allwinner,pins = "PB22", "PB23";
allwinner,function = "uart0";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart2_pins_a: uart2@0 {
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
allwinner,function = "uart2";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_a: uart3@0 {
+ allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart3_pins_b: uart3@1 {
+ allwinner,pins = "PH0", "PH1";
+ allwinner,function = "uart3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_pins_a: uart4@0 {
+ allwinner,pins = "PG10", "PG11";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart5_pins_a: uart5@0 {
+ allwinner,pins = "PI10", "PI11";
+ allwinner,function = "uart5";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart6_pins_a: uart6@0 {
allwinner,pins = "PI12", "PI13";
allwinner,function = "uart6";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
uart7_pins_a: uart7@0 {
allwinner,pins = "PI20", "PI21";
allwinner,function = "uart7";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PB0", "PB1";
allwinner,function = "i2c0";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c1_pins_a: i2c1@0 {
allwinner,pins = "PB18", "PB19";
allwinner,function = "i2c1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
i2c2_pins_a: i2c2@0 {
allwinner,pins = "PB20", "PB21";
allwinner,function = "i2c2";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PI0", "PI1";
+ allwinner,function = "i2c3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
emac_pins_a: emac0@0 {
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "emac";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
clk_out_a_pins_a: clk_out_a@0 {
allwinner,pins = "PI12";
allwinner,function = "clk_out_a";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
clk_out_b_pins_a: clk_out_b@0 {
allwinner,pins = "PI13";
allwinner,function = "clk_out_b";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_mii_a: gmac_mii@0 {
"PA11", "PA12", "PA13", "PA14",
"PA15", "PA16";
allwinner,function = "gmac";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
gmac_pins_rgmii_a: gmac_rgmii@0 {
* data lines in RGMII mode use DDR mode
* and need a higher signal drive strength
*/
- allwinner,drive = <3>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi0_pins_a: spi0@0 {
+ allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
+ allwinner,function = "spi0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi1_pins_a: spi1@0 {
allwinner,pins = "PI16", "PI17", "PI18", "PI19";
allwinner,function = "spi1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
spi2_pins_a: spi2@0 {
allwinner,pins = "PC19", "PC20", "PC21", "PC22";
allwinner,function = "spi2";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi2_pins_b: spi2@1 {
+ allwinner,pins = "PB14", "PB15", "PB16", "PB17";
+ allwinner,function = "spi2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_pins_a: mmc0@0 {
allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
allwinner,function = "mmc0";
- allwinner,drive = <2>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
allwinner,pins = "PH1";
allwinner,function = "gpio_in";
- allwinner,drive = <0>;
- allwinner,pull = <1>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
};
mmc3_pins_a: mmc3@0 {
allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
allwinner,function = "mmc3";
- allwinner,drive = <2>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir0_pins_a: ir0@0 {
allwinner,pins = "PB3","PB4";
allwinner,function = "ir0";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
ir1_pins_a: ir1@0 {
allwinner,pins = "PB22","PB23";
allwinner,function = "ir1";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ps20_pins_a: ps20@0 {
+ allwinner,pins = "PI20", "PI21";
+ allwinner,function = "ps2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ps21_pins_a: ps21@0 {
+ allwinner,pins = "PH12", "PH13";
+ allwinner,function = "ps2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
};
timer@01c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <0 22 4>,
- <0 23 4>,
- <0 24 4>,
- <0 25 4>,
- <0 67 4>,
- <0 68 4>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
rtc: rtc@01c20d00 {
compatible = "allwinner,sun7i-a20-rtc";
reg = <0x01c20d00 0x20>;
- interrupts = <0 24 4>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
pwm: pwm@01c20e00 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 6>, <&ir0_clk>;
clock-names = "apb", "ir";
- interrupts = <0 5 4>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c21800 0x40>;
status = "disabled";
};
compatible = "allwinner,sun4i-a10-ir";
clocks = <&apb0_gates 7>, <&ir1_clk>;
clock-names = "apb", "ir";
- interrupts = <0 6 4>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x01c21c00 0x40>;
status = "disabled";
};
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
sid: eeprom@01c23800 {
compatible = "allwinner,sun7i-a20-sid";
reg = <0x01c23800 0x200>;
};
rtp: rtp@01c25000 {
- compatible = "allwinner,sun4i-a10-ts";
+ compatible = "allwinner,sun5i-a13-ts";
reg = <0x01c25000 0x100>;
- interrupts = <0 29 4>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <0>;
};
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
- interrupts = <0 1 4>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 16>;
uart1: serial@01c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
- interrupts = <0 2 4>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 17>;
uart2: serial@01c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 18>;
uart3: serial@01c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
- interrupts = <0 4 4>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 19>;
uart4: serial@01c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
- interrupts = <0 17 4>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 20>;
uart5: serial@01c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
- interrupts = <0 18 4>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 21>;
uart6: serial@01c29800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29800 0x400>;
- interrupts = <0 19 4>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 22>;
uart7: serial@01c29c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29c00 0x400>;
- interrupts = <0 20 4>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&apb1_gates 23>;
i2c0: i2c@01c2ac00 {
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
reg = <0x01c2ac00 0x400>;
- interrupts = <0 7 4>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 0>;
- clock-frequency = <100000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
i2c1: i2c@01c2b000 {
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
reg = <0x01c2b000 0x400>;
- interrupts = <0 8 4>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 1>;
- clock-frequency = <100000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
i2c2: i2c@01c2b400 {
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
reg = <0x01c2b400 0x400>;
- interrupts = <0 9 4>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 2>;
- clock-frequency = <100000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
i2c3: i2c@01c2b800 {
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
reg = <0x01c2b800 0x400>;
- interrupts = <0 88 4>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 3>;
- clock-frequency = <100000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
i2c4: i2c@01c2c000 {
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
reg = <0x01c2c000 0x400>;
- interrupts = <0 89 4>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 15>;
- clock-frequency = <100000>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
gmac: ethernet@01c50000 {
compatible = "allwinner,sun7i-a20-gmac";
reg = <0x01c50000 0x10000>;
- interrupts = <0 85 4>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
clock-names = "stmmaceth", "allwinner_gmac_tx";
hstimer@01c60000 {
compatible = "allwinner,sun7i-a20-hstimer";
reg = <0x01c60000 0x1000>;
- interrupts = <0 81 4>,
- <0 82 4>,
- <0 83 4>,
- <0 84 4>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ahb_gates 28>;
};
<0x01c86000 0x2000>;
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 0xf04>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ ps20: ps2@01c2a000 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a000 0x400>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 6>;
+ status = "disabled";
+ };
+
+ ps21: ps2@01c2a400 {
+ compatible = "allwinner,sun4i-a10-ps2";
+ reg = <0x01c2a400 0x400>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 7>;
+ status = "disabled";
};
};
};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The Ippo Q8H v1.2 is almost identical to the v5, still it needs a separate
+ * dtb file since some gpio-s surrounding the wlan/bluetooth are different,
+ * and it uses different camera sensors.
+ */
+
+#include "sun8i-a23-ippo-q8h-v5.dts"
+
+/ {
+ model = "Ippo Q8H Dual Core Tablet (v1.2)";
+ compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
+};
--- /dev/null
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Ippo Q8H Dual Core Tablet (v5)";
+ compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
+
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ /* pull-ups and devices require PMIC regulator */
+ status = "failed";
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&pll6 0>;
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ cpus {
+ enable-method = "allwinner,sun8i-a23";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "pll5";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2";
+ };
+
+ cpu: cpu_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+
+ /*
+ * PLL1 is listed twice here.
+ * While it looks suspicious, it's actually documented
+ * that way both in the datasheet and in the code from
+ * Allwinner.
+ */
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1: ahb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_dma",
+ "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
+ "ahb1_nand", "ahb1_sdram",
+ "ahb1_hstimer", "ahb1_spi0",
+ "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
+ "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
+ "ahb1_csi", "ahb1_be", "ahb1_fe",
+ "ahb1_gpu", "ahb1_spinlock",
+ "ahb1_drc";
+ };
+
+ apb1_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-apb1-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_codec", "apb1_pio",
+ "apb1_daudio0", "apb1_daudio1";
+ };
+
+ apb2: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+ clock-output-names = "apb2";
+ };
+
+ apb2_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-apb2-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb2>;
+ clock-output-names = "apb2_i2c0", "apb2_i2c1",
+ "apb2_i2c2", "apb2_uart0",
+ "apb2_uart1", "apb2_uart2",
+ "apb2_uart3", "apb2_uart4";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+ clock-output-names = "mbus";
+ };
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun8i-a23-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 6>;
+ resets = <&ahb1_rst 6>;
+ #dma-cells = <1>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb1_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb1_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb1_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun8i-a23-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PF2", "PF4";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PH2", "PH3";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PH4", "PH5";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PE12", "PE13";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ ahb1_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 16>;
+ resets = <&apb2_rst 16>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 17>;
+ resets = <&apb2_rst 17>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 18>;
+ resets = <&apb2_rst 18>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 19>;
+ resets = <&apb2_rst 19>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 20>;
+ resets = <&apb2_rst 20>;
+ dmas = <&dma 10>, <&dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 0>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 1>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 2>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ prcm@01f01400 {
+ compatible = "allwinner,sun8i-a23-prcm";
+ reg = <0x01f01400 0x200>;
+
+ ar100: ar100_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "ar100";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&ar100>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: apb0_clk {
+ compatible = "allwinner,sun8i-a23-apb0-clk";
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible = "allwinner,sun8i-a23-apb0-gates-clk";
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_pio", "apb0_timer",
+ "apb0_rsb", "apb0_uart",
+ "apb0_i2c";
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpucfg@01f01c00 {
+ compatible = "allwinner,sun8i-a23-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
+
+ r_uart: serial@01f02800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01f02800 0x400>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb0_gates 4>;
+ resets = <&apb0_rst 4>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-a23-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_rst 0>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ r_uart_pins_a: r_uart@0 {
+ allwinner,pins = "PL2", "PL3";
+ allwinner,function = "s_uart";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Astar MID756 for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+
+/ {
+ model = "Astar MID756";
+ compatible = "astar,mid756", "allwinner,sun8i-a23";
+
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Minimal dts file for the Ippo Q8H V1.2 (A33, 1024x600) for u-boot only
+ *
+ * SPDX-License-Identifier: GPL-2.0+ or X11
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+
+/ {
+ model = "Ippo Q8H V1.2 (A33, 1024x600)";
+ compatible = "ippo,q8h-v1.2-a33-lcd1024x600", "allwinner,sun8i-a23";
+
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2015 Tyler Baker
+ *
+ * Tyler Baker <tyler.baker@linaro.org>
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun9i-a80.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Cubietech Cubieboard4";
+ compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+};
+
+&pio {
+ mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 {
+ allwinner,pins = "PH18";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun9i-a80.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Merrii A80 Optimus Board";
+ compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_optimus>;
+
+ /* The LED names match those found on the board */
+
+ led2 {
+ label = "optimus:led2:usr";
+ gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* led3 is on PM15, in R_PIO */
+
+ led4 {
+ label = "optimus:led4:usr";
+ gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_vbus_pin_optimus>;
+ regulator-name = "usb3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ status = "okay";
+};
+
+&i2c3_pins_a {
+ /* Enable internal pull-up */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&pio {
+ led_pins_optimus: led-pins@0 {
+ allwinner,pins = "PH0", "PH1";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_optimus: mmc0_cd_pin@0 {
+ allwinner,pins = "PH18";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb1_vbus_pin_optimus: usb1_vbus_pin@1 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb3_vbus_pin_optimus: usb3_vbus_pin@1 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_optimus>;
+ gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+&uart4_pins_a {
+ /* Enable internal pull-up */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&usbphy1 {
+ phy-supply = <®_usb1_vbus>;
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usbphy3 {
+ phy-supply = <®_usb3_vbus>;
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton64.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0x3>;
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x100>;
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x101>;
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x102>;
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a15";
+ device_type = "cpu";
+ reg = <0x103>;
+ };
+ };
+
+ memory {
+ /* 8GB max. with LPAE */
+ reg = <0 0x20000000 0x02 0>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * map 64 bit address range down to 32 bits,
+ * as the peripherals are all under 512MB.
+ */
+ ranges = <0 0 0 0x20000000>;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ usb_mod_clk: clk@00a08000 {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun9i-a80-usb-mod-clk";
+ reg = <0x00a08000 0x4>;
+ clocks = <&ahb1_gates 1>;
+ clock-output-names = "usb0_ahb", "usb_ohci0",
+ "usb1_ahb", "usb_ohci1",
+ "usb2_ahb", "usb_ohci2";
+ };
+
+ usb_phy_clk: clk@00a08004 {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun9i-a80-usb-phy-clk";
+ reg = <0x00a08004 0x4>;
+ clocks = <&ahb1_gates 1>;
+ clock-output-names = "usb_phy0", "usb_hsic1_480M",
+ "usb_phy1", "usb_hsic2_480M",
+ "usb_phy2", "usb_hsic_12M";
+ };
+
+ pll4: clk@0600000c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-pll4-clk";
+ reg = <0x0600000c 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll12: clk@0600002c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-pll4-clk";
+ reg = <0x0600002c 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll12";
+ };
+
+ gt_clk: clk@0600005c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-gt-clk";
+ reg = <0x0600005c 0x4>;
+ clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
+ clock-output-names = "gt";
+ };
+
+ ahb0: clk@06000060 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-ahb-clk";
+ reg = <0x06000060 0x4>;
+ clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
+ clock-output-names = "ahb0";
+ };
+
+ ahb1: clk@06000064 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-ahb-clk";
+ reg = <0x06000064 0x4>;
+ clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
+ clock-output-names = "ahb1";
+ };
+
+ ahb2: clk@06000068 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-ahb-clk";
+ reg = <0x06000068 0x4>;
+ clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>;
+ clock-output-names = "ahb2";
+ };
+
+ apb0: clk@06000070 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-apb0-clk";
+ reg = <0x06000070 0x4>;
+ clocks = <&osc24M>, <&pll4>;
+ clock-output-names = "apb0";
+ };
+
+ apb1: clk@06000074 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-apb1-clk";
+ reg = <0x06000074 0x4>;
+ clocks = <&osc24M>, <&pll4>;
+ clock-output-names = "apb1";
+ };
+
+ cci400_clk: clk@06000078 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun9i-a80-gt-clk";
+ reg = <0x06000078 0x4>;
+ clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
+ clock-output-names = "cci400";
+ };
+
+ mmc0_clk: clk@06000410 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-mmc-clk";
+ reg = <0x06000410 0x4>;
+ clocks = <&osc24M>, <&pll4>;
+ clock-output-names = "mmc0", "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@06000414 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-mmc-clk";
+ reg = <0x06000414 0x4>;
+ clocks = <&osc24M>, <&pll4>;
+ clock-output-names = "mmc1", "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@06000418 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-mmc-clk";
+ reg = <0x06000418 0x4>;
+ clocks = <&osc24M>, <&pll4>;
+ clock-output-names = "mmc2", "mmc2_output",
+ "mmc2_sample";
+ };
+
+ mmc3_clk: clk@0600041c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-mmc-clk";
+ reg = <0x0600041c 0x4>;
+ clocks = <&osc24M>, <&pll4>;
+ clock-output-names = "mmc3", "mmc3_output",
+ "mmc3_sample";
+ };
+
+ ahb0_gates: clk@06000580 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
+ reg = <0x06000580 0x4>;
+ clocks = <&ahb0>;
+ clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
+ <14>, <15>, <16>, <18>, <20>, <21>,
+ <22>, <23>;
+ clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
+ "ahb0_ss", "ahb0_sd", "ahb0_nand1",
+ "ahb0_nand0", "ahb0_sdram",
+ "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
+ "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
+ "ahb0_spi3";
+ };
+
+ ahb1_gates: clk@06000584 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
+ reg = <0x06000584 0x4>;
+ clocks = <&ahb1>;
+ clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+ clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
+ "ahb1_gmac", "ahb1_msgbox",
+ "ahb1_spinlock", "ahb1_hstimer",
+ "ahb1_dma";
+ };
+
+ ahb2_gates: clk@06000588 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
+ reg = <0x06000588 0x4>;
+ clocks = <&ahb2>;
+ clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
+ <11>;
+ clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
+ "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
+ "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
+ };
+
+ apb0_gates: clk@06000590 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-apb0-gates-clk";
+ reg = <0x06000590 0x4>;
+ clocks = <&apb0>;
+ clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
+ <17>, <18>, <19>;
+ clock-output-names = "apb0_spdif", "apb0_pio",
+ "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
+ "apb0_lradc", "apb0_gpadc", "apb0_twd",
+ "apb0_cirtx";
+ };
+
+ apb1_gates: clk@06000594 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun9i-a80-apb1-gates-clk";
+ reg = <0x06000594 0x4>;
+ clocks = <&apb1>;
+ clock-indices = <0>, <1>, <2>, <3>, <4>,
+ <16>, <17>, <18>, <19>, <20>, <21>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
+ "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3",
+ "apb1_uart4", "apb1_uart5";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * map 64 bit address range down to 32 bits,
+ * as the peripherals are all under 512MB.
+ */
+ ranges = <0 0 0 0x20000000>;
+
+ ehci0: usb@00a00000 {
+ compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
+ reg = <0x00a00000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_mod_clk 1>;
+ resets = <&usb_mod_clk 17>;
+ phys = <&usbphy1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@00a00400 {
+ compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
+ reg = <0x00a00400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
+ resets = <&usb_mod_clk 17>;
+ phys = <&usbphy1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy1: phy@00a00800 {
+ compatible = "allwinner,sun9i-a80-usb-phy";
+ reg = <0x00a00800 0x4>;
+ clocks = <&usb_phy_clk 1>;
+ clock-names = "phy";
+ resets = <&usb_phy_clk 17>;
+ reset-names = "phy";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ ehci1: usb@00a01000 {
+ compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
+ reg = <0x00a01000 0x100>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_mod_clk 3>;
+ resets = <&usb_mod_clk 18>;
+ phys = <&usbphy2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy2: phy@00a01800 {
+ compatible = "allwinner,sun9i-a80-usb-phy";
+ reg = <0x00a01800 0x4>;
+ clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>,
+ <&usb_phy_clk 3>;
+ clock-names = "hsic_480M", "hsic_12M", "phy";
+ resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>;
+ reset-names = "hsic", "phy";
+ status = "disabled";
+ #phy-cells = <0>;
+ /* usb1 is always used with HSIC */
+ phy_type = "hsic";
+ };
+
+ ehci2: usb@00a02000 {
+ compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
+ reg = <0x00a02000 0x100>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_mod_clk 5>;
+ resets = <&usb_mod_clk 19>;
+ phys = <&usbphy3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci2: usb@00a02400 {
+ compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
+ reg = <0x00a02400 0x100>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>;
+ resets = <&usb_mod_clk 19>;
+ phys = <&usbphy3>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy3: phy@00a02800 {
+ compatible = "allwinner,sun9i-a80-usb-phy";
+ reg = <0x00a02800 0x4>;
+ clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>,
+ <&usb_phy_clk 5>;
+ clock-names = "hsic_480M", "hsic_12M", "phy";
+ resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>;
+ reset-names = "hsic", "phy";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
+ <&mmc0_clk 1>, <&mmc0_clk 2>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&mmc_config_clk 0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
+ <&mmc1_clk 1>, <&mmc1_clk 2>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&mmc_config_clk 1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
+ <&mmc2_clk 1>, <&mmc2_clk 2>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&mmc_config_clk 2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
+ <&mmc3_clk 1>, <&mmc3_clk 2>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&mmc_config_clk 3>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc_config_clk: clk@01c13000 {
+ compatible = "allwinner,sun9i-a80-mmc-config-clk";
+ reg = <0x01c13000 0x10>;
+ clocks = <&ahb0_gates 8>;
+ clock-names = "ahb";
+ resets = <&ahb0_resets 8>;
+ reset-names = "ahb";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clock-output-names = "mmc0_config", "mmc1_config",
+ "mmc2_config", "mmc3_config";
+ };
+
+ gic: interrupt-controller@01c41000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c41000 0x1000>,
+ <0x01c42000 0x1000>,
+ <0x01c44000 0x2000>,
+ <0x01c46000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ ahb0_resets: reset@060005a0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x060005a0 0x4>;
+ };
+
+ ahb1_resets: reset@060005a4 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x060005a4 0x4>;
+ };
+
+ ahb2_resets: reset@060005a8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x060005a8 0x4>;
+ };
+
+ apb0_resets: reset@060005b0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x060005b0 0x4>;
+ };
+
+ apb1_resets: reset@060005b4 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x060005b4 0x4>;
+ };
+
+ timer@06000c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x06000c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&osc24M>;
+ };
+
+ pio: pinctrl@06000800 {
+ compatible = "allwinner,sun9i-a80-pinctrl";
+ reg = <0x06000800 0x400>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PG10", "PG11";
+ allwinner,function = "i2c3";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins: mmc0 {
+ allwinner,pins = "PF0", "PF1" ,"PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_8bit_pins: mmc2_8bit {
+ allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+ "PC10", "PC11", "PC12",
+ "PC13", "PC14", "PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PH12", "PH13";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart4_pins_a: uart4@0 {
+ allwinner,pins = "PG12", "PG13", "PG14", "PG15";
+ allwinner,function = "uart4";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ uart0: serial@07000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 16>;
+ resets = <&apb1_resets 16>;
+ status = "disabled";
+ };
+
+ uart1: serial@07000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ resets = <&apb1_resets 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@07000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ resets = <&apb1_resets 18>;
+ status = "disabled";
+ };
+
+ uart3: serial@07000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07000c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ resets = <&apb1_resets 19>;
+ status = "disabled";
+ };
+
+ uart4: serial@07001000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07001000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 20>;
+ resets = <&apb1_resets 20>;
+ status = "disabled";
+ };
+
+ uart5: serial@07001400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x07001400 0x400>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 21>;
+ resets = <&apb1_resets 21>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@07002800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07002800 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 0>;
+ resets = <&apb1_resets 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@07002c00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07002c00 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 1>;
+ resets = <&apb1_resets 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@07003000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07003000 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 2>;
+ resets = <&apb1_resets 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@07003400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07003400 0x400>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 3>;
+ resets = <&apb1_resets 3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@07003800 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x07003800 0x400>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 4>;
+ resets = <&apb1_resets 4>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ r_wdt: watchdog@08001000 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x08001000 0x20>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ r_uart: serial@08002800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x08002800 0x400>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&osc24M>;
+ status = "disabled";
+ };
+ };
+};
*
* Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
*
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
*/
-/ {
- soc@01c00000 {
- pio: pinctrl@01c20800 {
- ahci_pwr_pin_a: ahci_pwr_pin@0 {
- allwinner,pins = "PB8";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
- usb1_vbus_pin_a: usb1_vbus_pin@0 {
- allwinner,pins = "PH6";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
+&pio {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PB8";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_vbus_pin_a: usb0_vbus_pin@0 {
+ allwinner,pins = "PB9";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
- usb2_vbus_pin_a: usb2_vbus_pin@0 {
- allwinner,pins = "PH3";
- allwinner,function = "gpio_out";
- allwinner,drive = <0>;
- allwinner,pull = <0>;
- };
- };
+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = "PH3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+/ {
reg_ahci_5v: ahci-5v {
compatible = "regulator-fixed";
pinctrl-names = "default";
regulator-name = "ahci-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
enable-active-high;
- gpio = <&pio 1 8 0>;
+ gpio = <&pio 1 8 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_vbus_pin_a>;
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 1 9 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&pio 7 6 0>;
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
- gpio = <&pio 7 3 0>;
+ gpio = <&pio 7 3 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
};
+++ /dev/null
-/*
- * (C) Copyright 2011
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Lei Wen <leiwen@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * This file should be included in board config header file.
- *
- * It supports common definitions for Armada XP platforms
- */
-
-#ifndef _ARMADA_XP_CONFIG_H
-#define _ARMADA_XP_CONFIG_H
-
-#include <asm/arch/soc.h>
-
-#define MV88F78X60 /* for the DDR training bin_hdr code */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-/*
- * By default kwbimage.cfg from board specific folder is used
- * If for some board, different configuration file need to be used,
- * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
- */
-#ifndef CONFIG_SYS_KWD_CONFIG
-#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
-#endif /* CONFIG_SYS_KWD_CONFIG */
-
-/* Add target to build it automatically upon "make" */
-#ifdef CONFIG_SPL
-#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
-#else
-#define CONFIG_BUILD_TARGET "u-boot.kwb"
-#endif
-
-/* end of 16M scrubbed by training in bootrom */
-#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
-#define CONFIG_NR_DRAM_BANKS_MAX 2
-
-#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
-
-/*
- * SPI Flash configuration
- */
-#ifdef CONFIG_CMD_SF
-#define CONFIG_HARD_SPI 1
-#define CONFIG_KIRKWOOD_SPI 1
-#ifndef CONFIG_ENV_SPI_BUS
-# define CONFIG_ENV_SPI_BUS 0
-#endif
-#ifndef CONFIG_ENV_SPI_CS
-# define CONFIG_ENV_SPI_CS 0
-#endif
-#ifndef CONFIG_ENV_SPI_MAX_HZ
-# define CONFIG_ENV_SPI_MAX_HZ 50000000
-#endif
-#endif
-
-/*
- * Ethernet Driver configuration
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_CMD_MII
-#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
-#define CONFIG_PHYLIB
-#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
-#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
-#endif /* CONFIG_CMD_NET */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#ifndef CONFIG_SYS_I2C_SOFT
-#define CONFIG_I2C_MVTWSI
-#endif
-#define CONFIG_SYS_I2C_SLAVE 0x0
-#define CONFIG_SYS_I2C_SPEED 100000
-#endif
-
-#endif /* _ARMADA_XP_CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ARMADA_XP_CPU_H
-#define _ARMADA_XP_CPU_H
-
-#include <asm/system.h>
-
-#ifndef __ASSEMBLY__
-
-#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
-#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
-
-enum memory_bank {
- BANK0,
- BANK1,
- BANK2,
- BANK3
-};
-
-enum cpu_winen {
- CPU_WIN_DISABLE,
- CPU_WIN_ENABLE
-};
-
-enum cpu_target {
- CPU_TARGET_DRAM = 0x0,
- CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
- CPU_TARGET_ETH23 = 0x3,
- CPU_TARGET_PCIE02 = 0x4,
- CPU_TARGET_ETH01 = 0x7,
- CPU_TARGET_PCIE13 = 0x8,
- CPU_TARGET_SASRAM = 0x9,
- CPU_TARGET_NAND = 0xd,
-};
-
-enum cpu_attrib {
- CPU_ATTR_SASRAM = 0x01,
- CPU_ATTR_DRAM_CS0 = 0x0e,
- CPU_ATTR_DRAM_CS1 = 0x0d,
- CPU_ATTR_DRAM_CS2 = 0x0b,
- CPU_ATTR_DRAM_CS3 = 0x07,
- CPU_ATTR_NANDFLASH = 0x2f,
- CPU_ATTR_SPIFLASH = 0x1e,
- CPU_ATTR_BOOTROM = 0x1d,
- CPU_ATTR_PCIE_IO = 0xe0,
- CPU_ATTR_PCIE_MEM = 0xe8,
- CPU_ATTR_DEV_CS0 = 0x3e,
- CPU_ATTR_DEV_CS1 = 0x3d,
- CPU_ATTR_DEV_CS2 = 0x3b,
- CPU_ATTR_DEV_CS3 = 0x37,
-};
-
-/*
- * Default Device Address MAP BAR values
- */
-#define DEFADR_PCI_MEM 0x90000000
-#define DEFADR_PCI_IO 0xC0000000
-#define DEFADR_SPIF 0xF4000000
-#define DEFADR_BOOTROM 0xF8000000
-
-struct mbus_win {
- u32 base;
- u32 size;
- u8 target;
- u8 attr;
-};
-
-/*
- * System registers
- * Ref: Datasheet sec:A.28
- */
-struct mvebu_system_registers {
- u8 pad1[0x60];
- u32 rstoutn_mask; /* 0x60 */
- u32 sys_soft_rst; /* 0x64 */
-};
-
-/*
- * GPIO Registers
- * Ref: Datasheet sec:A.19
- */
-struct kwgpio_registers {
- u32 dout;
- u32 oe;
- u32 blink_en;
- u32 din_pol;
- u32 din;
- u32 irq_cause;
- u32 irq_mask;
- u32 irq_level;
-};
-
-/* Needed for dynamic (board-specific) mbus configuration */
-extern struct mvebu_mbus_state mbus_state;
-
-/*
- * functions
- */
-unsigned int mvebu_sdram_bar(enum memory_bank bank);
-unsigned int mvebu_sdram_bs(enum memory_bank bank);
-void mvebu_sdram_size_adjust(enum memory_bank bank);
-int mvebu_mbus_probe(struct mbus_win windows[], int count);
-
-/*
- * Highspeed SERDES PHY config init, ported from bin_hdr
- * to mainline U-Boot
- */
-int serdes_phy_config(void);
-
-/*
- * DDR3 init / training code ported from Marvell bin_hdr. Now
- * available in mainline U-Boot in:
- * drivers/ddr/mvebu/
- */
-int ddr3_init(void);
-#endif /* __ASSEMBLY__ */
-#endif /* _ARMADA_XP_CPU_H */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * Header file for the Marvell's Feroceon CPU core.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_ARMADA_XP_H
-#define _ASM_ARCH_ARMADA_XP_H
-
-#define SOC_MV78460_ID 0x7846
-
-/* TCLK Core Clock definition */
-#ifndef CONFIG_SYS_TCLK
-#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
-#endif
-
-/* SOC specific definations */
-#define INTREG_BASE 0xd0000000
-#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
-#define SOC_REGS_PHY_BASE 0xf1000000
-#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
-
-#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
-#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
-#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
-#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
-#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
-#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
-#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
-#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
-#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
-#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
-#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
-#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
-#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
-#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
-#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
-#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
-#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
-#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
-
-#define SDRAM_MAX_CS 4
-#define SDRAM_ADDR_MASK 0xFF000000
-
-/* Armada XP GbE controller has 4 ports */
-#define MAX_MVNETA_DEVS 4
-
-/* Kirkwood CPU memory windows */
-#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
-#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
-#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
-
-#endif /* _ASM_ARCH_ARMADA_XP_H */
u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
u32 pll9_cfg; /* 0x44 pll9 control */
u32 pll10_cfg; /* 0x48 pll10 control */
- u32 reserved8;
+ u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */
u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
u32 apb2_div; /* 0x58 APB2 divide ratio */
u32 reserved12[7];
u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
- u32 reserved13[2];
+ u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
+ u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
u32 dram_clk_gate; /* 0x100 DRAM module gating */
u32 be0_clk_cfg; /* 0x104 BE0 module clock */
u32 be1_clk_cfg; /* 0x108 BE1 module clock */
u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
- u32 reserved22[5];
+ u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
+ u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
+ u32 reserved22[3];
u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8)
+#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24)
+#define CCM_PLL11_CTRL_UPD (0x1 << 30)
+#define CCM_PLL11_CTRL_EN (0x1 << 31)
+
#define AHB1_ABP1_DIV_DEFAULT 0x00002020
#define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate1 offsets */
#define AHB_GATE_OFFSET_DRC0 25
+#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
+#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
+#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET (0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0 24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1 25
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
#else
#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
#endif
+#define MBUS_CLK_GATE (0x1 << 31)
#define CCM_PLL5_PATTERN 0xd1303333
+#define CCM_PLL11_PATTERN 0xf5860000
/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_SS 5
/* ahb_reset1 offsets */
+#define AHB_RESET_OFFSET_SAT 26
#define AHB_RESET_OFFSET_DRC0 25
+#define AHB_RESET_OFFSET_DE_FE0 14
#define AHB_RESET_OFFSET_DE_BE0 12
#define AHB_RESET_OFFSET_HDMI 11
#define AHB_RESET_OFFSET_LCD1 5
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
unsigned int clock_get_pll6(void);
#endif
#define SUNXI_MMC1_BASE 0x01c10000
#define SUNXI_MMC2_BASE 0x01c11000
#define SUNXI_MMC3_BASE 0x01c12000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN4I
#define SUNXI_USB0_BASE 0x01c13000
#define SUNXI_USB1_BASE 0x01c14000
#endif
#define SUNXI_HDMI_BASE 0x01c16000
#define SUNXI_SPI2_BASE 0x01c17000
#define SUNXI_SATA_BASE 0x01c18000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN4I
#define SUNXI_PATA_BASE 0x01c19000
#define SUNXI_ACE_BASE 0x01c1a000
#define SUNXI_TVE1_BASE 0x01c1b000
#define SUNXI_USB2_BASE 0x01c1c000
-#else
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
#define SUNXI_USB0_BASE 0x01c19000
#define SUNXI_USB1_BASE 0x01c1a000
#define SUNXI_USB2_BASE 0x01c1b000
/* dram regs definition */
#if defined(CONFIG_MACH_SUN6I)
#include <asm/arch/dram_sun6i.h>
-#elif defined(CONFIG_MACH_SUN8I)
-#include <asm/arch/dram_sun8i.h>
+#elif defined(CONFIG_MACH_SUN8I_A23)
+#include <asm/arch/dram_sun8i_a23.h>
+#elif defined(CONFIG_MACH_SUN8I_A33)
+#include <asm/arch/dram_sun8i_a33.h>
#else
#include <asm/arch/dram_sun4i.h>
#endif
+++ /dev/null
-/*
- * Sun8i platform dram controller register and constant defines
- *
- * (C) Copyright 2007-2013
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * CPL <cplanxy@allwinnertech.com>
- * Jerry Wang <wangflord@allwinnertech.com>
- *
- * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SUNXI_DRAM_SUN8I_H
-#define _SUNXI_DRAM_SUN8I_H
-
-struct dram_para {
- u32 clock;
- u32 type;
- u32 zq;
- u32 odt_en;
- u32 para1;
- u32 para2;
- u32 mr0;
- u32 mr1;
- u32 mr2;
- u32 mr3;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 tpr3;
- u32 tpr4;
- u32 tpr5;
- u32 tpr6;
- u32 tpr7;
- u32 tpr8;
- u32 tpr9;
- u32 tpr10;
- u32 tpr11;
- u32 tpr12;
- u32 tpr13;
-};
-
-struct sunxi_mctl_com_reg {
- u32 cr; /* 0x00 */
- u32 ccr; /* 0x04 controller configuration register */
- u32 dbgcr; /* 0x08 */
- u8 res0[0x4]; /* 0x0c */
- u32 mcr0_0; /* 0x10 */
- u32 mcr1_0; /* 0x14 */
- u32 mcr0_1; /* 0x18 */
- u32 mcr1_1; /* 0x1c */
- u32 mcr0_2; /* 0x20 */
- u32 mcr1_2; /* 0x24 */
- u32 mcr0_3; /* 0x28 */
- u32 mcr1_3; /* 0x2c */
- u32 mcr0_4; /* 0x30 */
- u32 mcr1_4; /* 0x34 */
- u32 mcr0_5; /* 0x38 */
- u32 mcr1_5; /* 0x3c */
- u32 mcr0_6; /* 0x40 */
- u32 mcr1_6; /* 0x44 */
- u32 mcr0_7; /* 0x48 */
- u32 mcr1_7; /* 0x4c */
- u32 mcr0_8; /* 0x50 */
- u32 mcr1_8; /* 0x54 */
- u32 mcr0_9; /* 0x58 */
- u32 mcr1_9; /* 0x5c */
- u32 mcr0_10; /* 0x60 */
- u32 mcr1_10; /* 0x64 */
- u32 mcr0_11; /* 0x68 */
- u32 mcr1_11; /* 0x6c */
- u32 mcr0_12; /* 0x70 */
- u32 mcr1_12; /* 0x74 */
- u32 mcr0_13; /* 0x78 */
- u32 mcr1_13; /* 0x7c */
- u32 mcr0_14; /* 0x80 */
- u32 mcr1_14; /* 0x84 */
- u32 mcr0_15; /* 0x88 */
- u32 mcr1_15; /* 0x8c */
- u32 bwcr; /* 0x90 */
- u32 maer; /* 0x94 */
- u8 res1[0x4]; /* 0x98 */
- u32 mcgcr; /* 0x9c */
- u32 bwctr; /* 0xa0 */
- u8 res2[0x4]; /* 0xa4 */
- u32 swonr; /* 0xa8 */
- u32 swoffr; /* 0xac */
-};
-
-struct sunxi_mctl_ctl_reg {
- u32 mstr; /* 0x00 */
- u32 statr; /* 0x04 */
- u8 res0[0x08]; /* 0x08 */
- u32 mrctrl0; /* 0x10 */
- u32 mrctrl1; /* 0x14 */
- u32 mrstatr; /* 0x18 */
- u8 res1[0x04]; /* 0x1c */
- u32 derateen; /* 0x20 */
- u32 deratenint; /* 0x24 */
- u8 res2[0x08]; /* 0x28 */
- u32 pwrctl; /* 0x30 */
- u32 pwrtmg; /* 0x34 */
- u8 res3[0x18]; /* 0x38 */
- u32 rfshctl0; /* 0x50 */
- u32 rfshctl1; /* 0x54 */
- u8 res4[0x8]; /* 0x58 */
- u32 rfshctl3; /* 0x60 */
- u32 rfshtmg; /* 0x64 */
- u8 res6[0x68]; /* 0x68 */
- u32 init0; /* 0xd0 */
- u32 init1; /* 0xd4 */
- u32 init2; /* 0xd8 */
- u32 init3; /* 0xdc */
- u32 init4; /* 0xe0 */
- u32 init5; /* 0xe4 */
- u8 res7[0x0c]; /* 0xe8 */
- u32 rankctl; /* 0xf4 */
- u8 res8[0x08]; /* 0xf8 */
- u32 dramtmg0; /* 0x100 */
- u32 dramtmg1; /* 0x104 */
- u32 dramtmg2; /* 0x108 */
- u32 dramtmg3; /* 0x10c */
- u32 dramtmg4; /* 0x110 */
- u32 dramtmg5; /* 0x114 */
- u32 dramtmg6; /* 0x118 */
- u32 dramtmg7; /* 0x11c */
- u32 dramtmg8; /* 0x120 */
- u8 res9[0x5c]; /* 0x124 */
- u32 zqctl0; /* 0x180 */
- u32 zqctl1; /* 0x184 */
- u32 zqctl2; /* 0x188 */
- u32 zqstat; /* 0x18c */
- u32 pitmg0; /* 0x190 */
- u32 pitmg1; /* 0x194 */
- u32 plpcfg0; /* 0x198 */
- u8 res10[0x04]; /* 0x19c */
- u32 upd0; /* 0x1a0 */
- u32 upd1; /* 0x1a4 */
- u32 upd2; /* 0x1a8 */
- u32 upd3; /* 0x1ac */
- u32 pimisc; /* 0x1b0 */
- u8 res11[0x1c]; /* 0x1b4 */
- u32 trainctl0; /* 0x1d0 */
- u32 trainctl1; /* 0x1d4 */
- u32 trainctl2; /* 0x1d8 */
- u32 trainstat; /* 0x1dc */
- u8 res12[0x60]; /* 0x1e0 */
- u32 odtcfg; /* 0x240 */
- u32 odtmap; /* 0x244 */
- u8 res13[0x08]; /* 0x248 */
- u32 sched; /* 0x250 */
- u8 res14[0x04]; /* 0x254 */
- u32 perfshpr0; /* 0x258 */
- u32 perfshpr1; /* 0x25c */
- u32 perflpr0; /* 0x260 */
- u32 perflpr1; /* 0x264 */
- u32 perfwr0; /* 0x268 */
- u32 perfwr1; /* 0x26c */
-};
-
-struct sunxi_mctl_phy_reg {
- u8 res0[0x04]; /* 0x00 */
- u32 pir; /* 0x04 */
- u32 pgcr0; /* 0x08 phy general configuration register */
- u32 pgcr1; /* 0x0c phy general configuration register */
- u32 pgsr0; /* 0x10 */
- u32 pgsr1; /* 0x14 */
- u32 dllgcr; /* 0x18 */
- u32 ptr0; /* 0x1c */
- u32 ptr1; /* 0x20 */
- u32 ptr2; /* 0x24 */
- u32 ptr3; /* 0x28 */
- u32 ptr4; /* 0x2c */
- u32 acmdlr; /* 0x30 */
- u32 acbdlr; /* 0x34 */
- u32 aciocr; /* 0x38 */
- u32 dxccr; /* 0x3c DATX8 common configuration register */
- u32 dsgcr; /* 0x40 dram system general config register */
- u32 dcr; /* 0x44 */
- u32 dtpr0; /* 0x48 dram timing parameters register 0 */
- u32 dtpr1; /* 0x4c dram timing parameters register 1 */
- u32 dtpr2; /* 0x50 dram timing parameters register 2 */
- u32 mr0; /* 0x54 mode register 0 */
- u32 mr1; /* 0x58 mode register 1 */
- u32 mr2; /* 0x5c mode register 2 */
- u32 mr3; /* 0x60 mode register 3 */
- u32 odtcr; /* 0x64 */
- u32 dtcr; /* 0x68 */
- u32 dtar0; /* 0x6c data training address register 0 */
- u32 dtar1; /* 0x70 data training address register 1 */
- u32 dtar2; /* 0x74 data training address register 2 */
- u32 dtar3; /* 0x78 data training address register 3 */
- u32 dtdr0; /* 0x7c */
- u32 dtdr1; /* 0x80 */
- u32 dtedr0; /* 0x84 */
- u32 dtedr1; /* 0x88 */
- u32 pgcr2; /* 0x8c */
- u8 res1[0x70]; /* 0x90 */
- u32 bistrr; /* 0x100 */
- u32 bistwcr; /* 0x104 */
- u32 bistmskr0; /* 0x108 */
- u32 bistmskr1; /* 0x10c */
- u32 bistmskr2; /* 0x110 */
- u32 bistlsr; /* 0x114 */
- u32 bistar0; /* 0x118 */
- u32 bistar1; /* 0x11c */
- u32 bistar2; /* 0x120 */
- u32 bistupdr; /* 0x124 */
- u32 bistgsr; /* 0x128 */
- u32 bistwer; /* 0x12c */
- u32 bistber0; /* 0x130 */
- u32 bistber1; /* 0x134 */
- u32 bistber2; /* 0x138 */
- u32 bistber3; /* 0x13c */
- u32 bistwcsr; /* 0x140 */
- u32 bistfwr0; /* 0x144 */
- u32 bistfwr1; /* 0x148 */
- u32 bistfwr2; /* 0x14c */
- u8 res2[0x30]; /* 0x150 */
- u32 zqcr0; /* 0x180 zq control register 0 */
- u32 zqcr1; /* 0x184 zq control register 1 */
- u32 zqsr0; /* 0x188 zq status register 0 */
- u32 zqsr1; /* 0x18c zq status register 1 */
- u32 zqcr2; /* 0x190 zq control register 2 */
- u8 res3[0x2c]; /* 0x194 */
- u32 dx0gcr; /* 0x1c0 */
- u32 dx0gsr0; /* 0x1c4 */
- u32 dx0gsr1; /* 0x1c8 */
- u32 dx0bdlr0; /* 0x1cc */
- u32 dx0bdlr1; /* 0x1d0 */
- u32 dx0bdlr2; /* 0x1d4 */
- u32 dx0bdlr3; /* 0x1d8 */
- u32 dx0bdlr4; /* 0x1dc */
- u32 dx0lcdlr0; /* 0x1e0 */
- u32 dx0lcdlr1; /* 0x1e4 */
- u32 dx0lcdlr2; /* 0x1e8 */
- u32 dx0mdlr; /* 0x1ec */
- u32 dx0gtr; /* 0x1f0 */
- u32 dx0gsr2; /* 0x1f4 */
- u8 res4[0x08]; /* 0x1f8 */
- u32 dx1gcr; /* 0x200 */
- u32 dx1gsr0; /* 0x204 */
- u32 dx1gsr1; /* 0x208 */
- u32 dx1bdlr0; /* 0x20c */
- u32 dx1bdlr1; /* 0x210 */
- u32 dx1bdlr2; /* 0x214 */
- u32 dx1bdlr3; /* 0x218 */
- u32 dx1bdlr4; /* 0x21c */
- u32 dx1lcdlr0; /* 0x220 */
- u32 dx1lcdlr1; /* 0x224 */
- u32 dx1lcdlr2; /* 0x228 */
- u32 dx1mdlr; /* 0x22c */
- u32 dx1gtr; /* 0x230 */
- u32 dx1gsr2; /* 0x234 */
-};
-
-/*
- * DRAM common (sunxi_mctl_com_reg) register constants.
- */
-#define MCTL_CR_ROW_MASK (0xf << 4)
-#define MCTL_CR_ROW(x) (((x) - 1) << 4)
-#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
-#define MCTL_CR_PAGE_SIZE(x) ((x) << 8)
-
-#endif /* _SUNXI_DRAM_SUN8I_H */
--- /dev/null
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * CPL <cplanxy@allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H
+#define _SUNXI_DRAM_SUN8I_H
+
+struct dram_para {
+ u32 clock;
+ u32 type;
+ u32 zq;
+ u32 odt_en;
+ u32 para1;
+ u32 para2;
+ u32 mr0;
+ u32 mr1;
+ u32 mr2;
+ u32 mr3;
+ u32 tpr0;
+ u32 tpr1;
+ u32 tpr2;
+ u32 tpr3;
+ u32 tpr4;
+ u32 tpr5;
+ u32 tpr6;
+ u32 tpr7;
+ u32 tpr8;
+ u32 tpr9;
+ u32 tpr10;
+ u32 tpr11;
+ u32 tpr12;
+ u32 tpr13;
+};
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 */
+ u32 ccr; /* 0x04 controller configuration register */
+ u32 dbgcr; /* 0x08 */
+ u8 res0[0x4]; /* 0x0c */
+ u32 mcr0_0; /* 0x10 */
+ u32 mcr1_0; /* 0x14 */
+ u32 mcr0_1; /* 0x18 */
+ u32 mcr1_1; /* 0x1c */
+ u32 mcr0_2; /* 0x20 */
+ u32 mcr1_2; /* 0x24 */
+ u32 mcr0_3; /* 0x28 */
+ u32 mcr1_3; /* 0x2c */
+ u32 mcr0_4; /* 0x30 */
+ u32 mcr1_4; /* 0x34 */
+ u32 mcr0_5; /* 0x38 */
+ u32 mcr1_5; /* 0x3c */
+ u32 mcr0_6; /* 0x40 */
+ u32 mcr1_6; /* 0x44 */
+ u32 mcr0_7; /* 0x48 */
+ u32 mcr1_7; /* 0x4c */
+ u32 mcr0_8; /* 0x50 */
+ u32 mcr1_8; /* 0x54 */
+ u32 mcr0_9; /* 0x58 */
+ u32 mcr1_9; /* 0x5c */
+ u32 mcr0_10; /* 0x60 */
+ u32 mcr1_10; /* 0x64 */
+ u32 mcr0_11; /* 0x68 */
+ u32 mcr1_11; /* 0x6c */
+ u32 mcr0_12; /* 0x70 */
+ u32 mcr1_12; /* 0x74 */
+ u32 mcr0_13; /* 0x78 */
+ u32 mcr1_13; /* 0x7c */
+ u32 mcr0_14; /* 0x80 */
+ u32 mcr1_14; /* 0x84 */
+ u32 mcr0_15; /* 0x88 */
+ u32 mcr1_15; /* 0x8c */
+ u32 bwcr; /* 0x90 */
+ u32 maer; /* 0x94 */
+ u8 res1[0x4]; /* 0x98 */
+ u32 mcgcr; /* 0x9c */
+ u32 bwctr; /* 0xa0 */
+ u8 res2[0x4]; /* 0xa4 */
+ u32 swonr; /* 0xa8 */
+ u32 swoffr; /* 0xac */
+};
+
+struct sunxi_mctl_ctl_reg {
+ u32 mstr; /* 0x00 */
+ u32 statr; /* 0x04 */
+ u8 res0[0x08]; /* 0x08 */
+ u32 mrctrl0; /* 0x10 */
+ u32 mrctrl1; /* 0x14 */
+ u32 mrstatr; /* 0x18 */
+ u8 res1[0x04]; /* 0x1c */
+ u32 derateen; /* 0x20 */
+ u32 deratenint; /* 0x24 */
+ u8 res2[0x08]; /* 0x28 */
+ u32 pwrctl; /* 0x30 */
+ u32 pwrtmg; /* 0x34 */
+ u8 res3[0x18]; /* 0x38 */
+ u32 rfshctl0; /* 0x50 */
+ u32 rfshctl1; /* 0x54 */
+ u8 res4[0x8]; /* 0x58 */
+ u32 rfshctl3; /* 0x60 */
+ u32 rfshtmg; /* 0x64 */
+ u8 res6[0x68]; /* 0x68 */
+ u32 init0; /* 0xd0 */
+ u32 init1; /* 0xd4 */
+ u32 init2; /* 0xd8 */
+ u32 init3; /* 0xdc */
+ u32 init4; /* 0xe0 */
+ u32 init5; /* 0xe4 */
+ u8 res7[0x0c]; /* 0xe8 */
+ u32 rankctl; /* 0xf4 */
+ u8 res8[0x08]; /* 0xf8 */
+ u32 dramtmg0; /* 0x100 */
+ u32 dramtmg1; /* 0x104 */
+ u32 dramtmg2; /* 0x108 */
+ u32 dramtmg3; /* 0x10c */
+ u32 dramtmg4; /* 0x110 */
+ u32 dramtmg5; /* 0x114 */
+ u32 dramtmg6; /* 0x118 */
+ u32 dramtmg7; /* 0x11c */
+ u32 dramtmg8; /* 0x120 */
+ u8 res9[0x5c]; /* 0x124 */
+ u32 zqctl0; /* 0x180 */
+ u32 zqctl1; /* 0x184 */
+ u32 zqctl2; /* 0x188 */
+ u32 zqstat; /* 0x18c */
+ u32 pitmg0; /* 0x190 */
+ u32 pitmg1; /* 0x194 */
+ u32 plpcfg0; /* 0x198 */
+ u8 res10[0x04]; /* 0x19c */
+ u32 upd0; /* 0x1a0 */
+ u32 upd1; /* 0x1a4 */
+ u32 upd2; /* 0x1a8 */
+ u32 upd3; /* 0x1ac */
+ u32 pimisc; /* 0x1b0 */
+ u8 res11[0x1c]; /* 0x1b4 */
+ u32 trainctl0; /* 0x1d0 */
+ u32 trainctl1; /* 0x1d4 */
+ u32 trainctl2; /* 0x1d8 */
+ u32 trainstat; /* 0x1dc */
+ u8 res12[0x60]; /* 0x1e0 */
+ u32 odtcfg; /* 0x240 */
+ u32 odtmap; /* 0x244 */
+ u8 res13[0x08]; /* 0x248 */
+ u32 sched; /* 0x250 */
+ u8 res14[0x04]; /* 0x254 */
+ u32 perfshpr0; /* 0x258 */
+ u32 perfshpr1; /* 0x25c */
+ u32 perflpr0; /* 0x260 */
+ u32 perflpr1; /* 0x264 */
+ u32 perfwr0; /* 0x268 */
+ u32 perfwr1; /* 0x26c */
+};
+
+struct sunxi_mctl_phy_reg {
+ u8 res0[0x04]; /* 0x00 */
+ u32 pir; /* 0x04 */
+ u32 pgcr0; /* 0x08 phy general configuration register */
+ u32 pgcr1; /* 0x0c phy general configuration register */
+ u32 pgsr0; /* 0x10 */
+ u32 pgsr1; /* 0x14 */
+ u32 dllgcr; /* 0x18 */
+ u32 ptr0; /* 0x1c */
+ u32 ptr1; /* 0x20 */
+ u32 ptr2; /* 0x24 */
+ u32 ptr3; /* 0x28 */
+ u32 ptr4; /* 0x2c */
+ u32 acmdlr; /* 0x30 */
+ u32 acbdlr; /* 0x34 */
+ u32 aciocr; /* 0x38 */
+ u32 dxccr; /* 0x3c DATX8 common configuration register */
+ u32 dsgcr; /* 0x40 dram system general config register */
+ u32 dcr; /* 0x44 */
+ u32 dtpr0; /* 0x48 dram timing parameters register 0 */
+ u32 dtpr1; /* 0x4c dram timing parameters register 1 */
+ u32 dtpr2; /* 0x50 dram timing parameters register 2 */
+ u32 mr0; /* 0x54 mode register 0 */
+ u32 mr1; /* 0x58 mode register 1 */
+ u32 mr2; /* 0x5c mode register 2 */
+ u32 mr3; /* 0x60 mode register 3 */
+ u32 odtcr; /* 0x64 */
+ u32 dtcr; /* 0x68 */
+ u32 dtar0; /* 0x6c data training address register 0 */
+ u32 dtar1; /* 0x70 data training address register 1 */
+ u32 dtar2; /* 0x74 data training address register 2 */
+ u32 dtar3; /* 0x78 data training address register 3 */
+ u32 dtdr0; /* 0x7c */
+ u32 dtdr1; /* 0x80 */
+ u32 dtedr0; /* 0x84 */
+ u32 dtedr1; /* 0x88 */
+ u32 pgcr2; /* 0x8c */
+ u8 res1[0x70]; /* 0x90 */
+ u32 bistrr; /* 0x100 */
+ u32 bistwcr; /* 0x104 */
+ u32 bistmskr0; /* 0x108 */
+ u32 bistmskr1; /* 0x10c */
+ u32 bistmskr2; /* 0x110 */
+ u32 bistlsr; /* 0x114 */
+ u32 bistar0; /* 0x118 */
+ u32 bistar1; /* 0x11c */
+ u32 bistar2; /* 0x120 */
+ u32 bistupdr; /* 0x124 */
+ u32 bistgsr; /* 0x128 */
+ u32 bistwer; /* 0x12c */
+ u32 bistber0; /* 0x130 */
+ u32 bistber1; /* 0x134 */
+ u32 bistber2; /* 0x138 */
+ u32 bistber3; /* 0x13c */
+ u32 bistwcsr; /* 0x140 */
+ u32 bistfwr0; /* 0x144 */
+ u32 bistfwr1; /* 0x148 */
+ u32 bistfwr2; /* 0x14c */
+ u8 res2[0x30]; /* 0x150 */
+ u32 zqcr0; /* 0x180 zq control register 0 */
+ u32 zqcr1; /* 0x184 zq control register 1 */
+ u32 zqsr0; /* 0x188 zq status register 0 */
+ u32 zqsr1; /* 0x18c zq status register 1 */
+ u32 zqcr2; /* 0x190 zq control register 2 */
+ u8 res3[0x2c]; /* 0x194 */
+ u32 dx0gcr; /* 0x1c0 */
+ u32 dx0gsr0; /* 0x1c4 */
+ u32 dx0gsr1; /* 0x1c8 */
+ u32 dx0bdlr0; /* 0x1cc */
+ u32 dx0bdlr1; /* 0x1d0 */
+ u32 dx0bdlr2; /* 0x1d4 */
+ u32 dx0bdlr3; /* 0x1d8 */
+ u32 dx0bdlr4; /* 0x1dc */
+ u32 dx0lcdlr0; /* 0x1e0 */
+ u32 dx0lcdlr1; /* 0x1e4 */
+ u32 dx0lcdlr2; /* 0x1e8 */
+ u32 dx0mdlr; /* 0x1ec */
+ u32 dx0gtr; /* 0x1f0 */
+ u32 dx0gsr2; /* 0x1f4 */
+ u8 res4[0x08]; /* 0x1f8 */
+ u32 dx1gcr; /* 0x200 */
+ u32 dx1gsr0; /* 0x204 */
+ u32 dx1gsr1; /* 0x208 */
+ u32 dx1bdlr0; /* 0x20c */
+ u32 dx1bdlr1; /* 0x210 */
+ u32 dx1bdlr2; /* 0x214 */
+ u32 dx1bdlr3; /* 0x218 */
+ u32 dx1bdlr4; /* 0x21c */
+ u32 dx1lcdlr0; /* 0x220 */
+ u32 dx1lcdlr1; /* 0x224 */
+ u32 dx1lcdlr2; /* 0x228 */
+ u32 dx1mdlr; /* 0x22c */
+ u32 dx1gtr; /* 0x230 */
+ u32 dx1gsr2; /* 0x234 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_ROW_MASK (0xf << 4)
+#define MCTL_CR_ROW(x) (((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x) ((x) << 8)
+
+#endif /* _SUNXI_DRAM_SUN8I_H */
--- /dev/null
+/*
+ * Sun8i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang <wangflord@allwinnertech.com>
+ * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_A33_H
+#define _SUNXI_DRAM_SUN8I_A33_H
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 */
+ u32 ccr; /* 0x04 controller configuration register */
+ u32 dbgcr; /* 0x08 */
+ u8 res0[0x4]; /* 0x0c */
+ u32 mcr0_0; /* 0x10 */
+ u32 mcr1_0; /* 0x14 */
+ u32 mcr0_1; /* 0x18 */
+ u32 mcr1_1; /* 0x1c */
+ u32 mcr0_2; /* 0x20 */
+ u32 mcr1_2; /* 0x24 */
+ u32 mcr0_3; /* 0x28 */
+ u32 mcr1_3; /* 0x2c */
+ u32 mcr0_4; /* 0x30 */
+ u32 mcr1_4; /* 0x34 */
+ u32 mcr0_5; /* 0x38 */
+ u32 mcr1_5; /* 0x3c */
+ u32 mcr0_6; /* 0x40 */
+ u32 mcr1_6; /* 0x44 */
+ u32 mcr0_7; /* 0x48 */
+ u32 mcr1_7; /* 0x4c */
+ u32 mcr0_8; /* 0x50 */
+ u32 mcr1_8; /* 0x54 */
+ u32 mcr0_9; /* 0x58 */
+ u32 mcr1_9; /* 0x5c */
+ u32 mcr0_10; /* 0x60 */
+ u32 mcr1_10; /* 0x64 */
+ u32 mcr0_11; /* 0x68 */
+ u32 mcr1_11; /* 0x6c */
+ u32 mcr0_12; /* 0x70 */
+ u32 mcr1_12; /* 0x74 */
+ u32 mcr0_13; /* 0x78 */
+ u32 mcr1_13; /* 0x7c */
+ u32 mcr0_14; /* 0x80 */
+ u32 mcr1_14; /* 0x84 */
+ u32 mcr0_15; /* 0x88 */
+ u32 mcr1_15; /* 0x8c */
+ u32 bwcr; /* 0x90 */
+ u32 maer; /* 0x94 */
+ u32 mapr; /* 0x98 */
+ u32 mcgcr; /* 0x9c */
+ u32 bwctr; /* 0xa0 */
+ u8 res2[0x8]; /* 0xa4 */
+ u32 swoffr; /* 0xac */
+ u8 res3[0x10]; /* 0xb0 */
+ u32 swonr; /* 0xc0 */
+ u8 res4[0x3c]; /* 0xc4 */
+ u32 mdfscr; /* 0x100 */
+ u32 mdfsmer; /* 0x104 */
+};
+
+struct sunxi_mctl_ctl_reg {
+ u32 pir; /* 0x00 */
+ u32 pwrctl; /* 0x04 */
+ u32 mrctrl0; /* 0x08 */
+ u32 clken; /* 0x0c */
+ u32 pgsr0; /* 0x10 */
+ u32 pgsr1; /* 0x14 */
+ u32 statr; /* 0x18 */
+ u8 res1[0x14]; /* 0x1c */
+ u32 mr0; /* 0x30 */
+ u32 mr1; /* 0x34 */
+ u32 mr2; /* 0x38 */
+ u32 mr3; /* 0x3c */
+ u32 pllgcr; /* 0x40 */
+ u32 ptr0; /* 0x44 */
+ u32 ptr1; /* 0x48 */
+ u32 ptr2; /* 0x4c */
+ u32 ptr3; /* 0x50 */
+ u32 ptr4; /* 0x54 */
+ u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
+ u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
+ u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
+ u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
+ u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
+ u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
+ u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
+ u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
+ u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
+ u32 odtcfg; /* 0x7c */
+ u32 pitmg0; /* 0x80 */
+ u32 pitmg1; /* 0x84 */
+ u8 res2[0x4]; /* 0x88 */
+ u32 rfshctl0; /* 0x8c */
+ u32 rfshtmg; /* 0x90 */
+ u32 rfshctl1; /* 0x94 */
+ u32 pwrtmg; /* 0x98 */
+ u8 res3[0x20]; /* 0x9c */
+ u32 dqsgmr; /* 0xbc */
+ u32 dtcr; /* 0xc0 */
+ u32 dtar0; /* 0xc4 */
+ u32 dtar1; /* 0xc8 */
+ u32 dtar2; /* 0xcc */
+ u32 dtar3; /* 0xd0 */
+ u32 dtdr0; /* 0xd4 */
+ u32 dtdr1; /* 0xd8 */
+ u32 dtmr0; /* 0xdc */
+ u32 dtmr1; /* 0xe0 */
+ u32 dtbmr; /* 0xe4 */
+ u32 catr0; /* 0xe8 */
+ u32 catr1; /* 0xec */
+ u32 dtedr0; /* 0xf0 */
+ u32 dtedr1; /* 0xf4 */
+ u8 res4[0x8]; /* 0xf8 */
+ u32 pgcr0; /* 0x100 */
+ u32 pgcr1; /* 0x104 */
+ u32 pgcr2; /* 0x108 */
+ u8 res5[0x4]; /* 0x10c */
+ u32 iovcr0; /* 0x110 */
+ u32 iovcr1; /* 0x114 */
+ u32 dqsdr; /* 0x118 */
+ u32 dxccr; /* 0x11c */
+ u32 odtmap; /* 0x120 */
+ u32 zqctl0; /* 0x124 */
+ u32 zqctl1; /* 0x128 */
+ u8 res6[0x14]; /* 0x12c */
+ u32 zqcr0; /* 0x140 zq control register 0 */
+ u32 zqcr1; /* 0x144 zq control register 1 */
+ u32 zqcr2; /* 0x148 zq control register 2 */
+ u32 zqsr0; /* 0x14c zq status register 0 */
+ u32 zqsr1; /* 0x150 zq status register 1 */
+ u8 res7[0x6c]; /* 0x154 */
+ u32 sched; /* 0x1c0 */
+ u32 perfhpr0; /* 0x1c4 */
+ u32 perfhpr1; /* 0x1c8 */
+ u32 perflpr0; /* 0x1cc */
+ u32 perflpr1; /* 0x1d0 */
+ u32 perfwr0; /* 0x1d4 */
+ u32 perfwr1; /* 0x1d8 */
+};
+
+#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
+#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
+#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
+#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
+#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK (3 << 0)
+#define MCTL_CR_RANK(x) (((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK (3 << 2)
+#define MCTL_CR_BANK(x) ((x) << 2)
+#define MCTL_CR_ROW_MASK (0xf << 4)
+#define MCTL_CR_ROW(x) (((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK (7 << 12)
+#define MCTL_CR_BUSW8 (0 << 12)
+#define MCTL_CR_BUSW16 (1 << 12)
+#define MCTL_CR_SEQUENCE (1 << 15)
+#define MCTL_CR_DDR3 (3 << 16)
+#define MCTL_CR_CHANNEL_MASK (1 << 19)
+#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN (0x4 << 20)
+#define MCTL_CR_CS1_CONTROL(x) ((x) << 24)
+
+/* DRAM control (sunxi_mctl_ctl_reg) register constants */
+#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */
+#define MCTL_MR1 0x40
+#define MCTL_MR2 0x18 /* CWL=8 */
+#define MCTL_MR3 0x0
+
+#endif /* _SUNXI_DRAM_SUN8I_A33_H */
#define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */
-#define SUNXI_GPIO_AXP0_VBUS_DETECT 8
-#define SUNXI_GPIO_AXP0_VBUS_ENABLE 9
+#define SUNXI_GPIO_AXP0_PREFIX "AXP0-"
+#define SUNXI_GPIO_AXP0_VBUS_DETECT 4
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5
+#define SUNXI_GPIO_AXP0_GPIO_COUNT 6
void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
int sunxi_name_to_gpio(const char *name);
#define name_to_gpio(name) sunxi_name_to_gpio(name)
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+int axp_gpio_init(void);
+#else
+static inline int axp_gpio_init(void) { return 0; }
+#endif
+
#endif /* _SUNXI_GPIO_H */
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
- defined(CONFIG_MACH_SUN9I)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
u32 res2[64];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
--- /dev/null
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Sunxi PMIC bus access helpers header
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_PMIC_BUS_H
+#define _SUNXI_PMIS_BUS_H
+
+int pmic_bus_init(void);
+int pmic_bus_read(u8 reg, u8 *data);
+int pmic_bus_write(u8 reg, u8 data);
+int pmic_bus_setbits(u8 reg, u8 bits);
+int pmic_bus_clrbits(u8 reg, u8 bits);
+
+#endif
*/
void return_to_fel(uint32_t lr, uint32_t sp);
+/* Board / SoC level designware gmac init */
+int sunxi_gmac_initialize(bd_t *bis);
+
#endif
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_SUNXI_GEN_SUN4I
struct sunxi_wdog wdog; /* 0x90 */
/* XXX the following is not accurate for sun5i/sun7i */
struct sunxi_64cnt cnt64; /* 0xa0 */
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
--- /dev/null
+/*
+ * Sunxi usb-phy code
+ *
+ * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+int sunxi_usb_phy_probe(void);
+int sunxi_usb_phy_remove(void);
+void sunxi_usb_phy_init(int index);
+void sunxi_usb_phy_exit(int index);
+void sunxi_usb_phy_power_on(int index);
+void sunxi_usb_phy_power_off(int index);
+int sunxi_usb_phy_vbus_detect(int index);
+void sunxi_usb_phy_enable_squelch_detect(int index, int enable);
+++ /dev/null
-/*
- * Sunxi usb-controller code shared between the ehci and musb controllers
- *
- * Copyright (C) 2014 Roman Byshko
- *
- * Roman Byshko <rbyshko@gmail.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-extern const struct musb_platform_ops sunxi_musb_ops;
-
-void *sunxi_usbc_get_io_base(int index);
-int sunxi_usbc_request_resources(int index);
-int sunxi_usbc_free_resources(int index);
-void sunxi_usbc_enable(int index);
-void sunxi_usbc_disable(int index);
-void sunxi_usbc_vbus_enable(int index);
-void sunxi_usbc_vbus_disable(int index);
-int sunxi_usbc_vbus_detect(int index);
-void sunxi_usbc_enable_squelch_detect(int index, int enable);
#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
+#ifdef __ARM_ARCH_7A__
+#define ISB asm volatile ("isb" : : : "memory")
+#define DSB asm volatile ("dsb" : : : "memory")
+#define DMB asm volatile ("dmb" : : : "memory")
+#else
+#define ISB CP15ISB
+#define DSB CP15DSB
+#define DMB CP15DMB
+#endif
+
/*
* Workaround for ARM errata # 798870
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
return (old & mask) != 0;
}
-extern int find_first_zero_bit(void * addr, unsigned size);
-extern int find_next_zero_bit(void * addr, int size, int offset);
-
/*
* This routine doesn't need to be atomic.
*/
return k;
}
+static inline int find_next_zero_bit(void *addr, int size, int offset)
+{
+ unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
+ unsigned long result = offset & ~31UL;
+ unsigned long tmp;
+
+ if (offset >= size)
+ return size;
+ size -= result;
+ offset &= 31UL;
+ if (offset) {
+ tmp = *(p++);
+ tmp |= ~0UL >> (32-offset);
+ if (size < 32)
+ goto found_first;
+ if (~tmp)
+ goto found_middle;
+ size -= 32;
+ result += 32;
+ }
+ while (size & ~31UL) {
+ tmp = *(p++);
+ if (~tmp)
+ goto found_middle;
+ result += 32;
+ size -= 32;
+ }
+ if (!size)
+ return result;
+ tmp = *p;
+
+found_first:
+ tmp |= ~0UL >> size;
+found_middle:
+ return result + ffz(tmp);
+}
+
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
+#define find_first_zero_bit(addr, size) \
+ find_next_zero_bit((addr), (size), 0)
+
#define ext2_set_bit test_and_set_bit
#define ext2_clear_bit test_and_clear_bit
#define ext2_test_bit test_bit
mov \xreg1, #0x33ff
msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
+ /* Initialize Generic Timers */
+ msr cntvoff_el2, xzr
+
/* Initialize SCTLR_EL2
*
* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
isb();
}
+#ifdef CONFIG_ARMV7
+/* Short-Descriptor Translation Table Level 1 Bits */
+#define TTB_SECT_NS_MASK (1 << 19)
+#define TTB_SECT_NG_MASK (1 << 17)
+#define TTB_SECT_S_MASK (1 << 16)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
+#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
+#define TTB_SECT_XN_MASK (1 << 4)
+#define TTB_SECT_C_MASK (1 << 3)
+#define TTB_SECT_B_MASK (1 << 2)
+#define TTB_SECT (2 << 0)
+
+/* options available for data cache on each page */
+enum dcache_option {
+ DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
+ TTB_SECT_XN_MASK | TTB_SECT,
+ DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
+ DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
+ DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
+};
+#else
/* options available for data cache on each page */
enum dcache_option {
DCACHE_OFF = 0x12,
DCACHE_WRITEBACK = 0x1e,
DCACHE_WRITEALLOC = 0x16,
};
+#endif
/* Size of an MMU section */
enum {
MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
};
+#ifdef CONFIG_ARMV7
+/* TTBR0 bits */
+#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
+#define TTBR0_RGN_NC (0 << 3)
+#define TTBR0_RGN_WBWA (1 << 3)
+#define TTBR0_RGN_WT (2 << 3)
+#define TTBR0_RGN_WB (3 << 3)
+/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
+#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
+#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
+#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
+#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
+#endif
+
/**
* Change the cache settings for a region.
*
dram_bank_mmu_setup(i);
}
+#ifdef CONFIG_ARMV7
+ /* Set TTBR0 */
+ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
+#else
+ reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
+#endif
+ asm volatile("mcr p15, 0, %0, c2, c0, 0"
+ : : "r" (reg) : "memory");
+#else
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (gd->arch.tlb_addr) : "memory");
+#endif
/* Set the access control to all-supervisor */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));
--- /dev/null
+#
+# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_KIRKWOOD
+
+obj-y = dram.o
+obj-y += gpio.o
+obj-y += timer.o
+
+else
+
+obj-y = cpu.o
+obj-y += dram.o
+obj-y += gpio.o
+obj-y += mbus.o
+obj-y += timer.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+
+obj-y += serdes/
+endif
--- /dev/null
+/*
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
+
+static struct mbus_win windows[] = {
+ /* PCIE MEM address space */
+ { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
+
+ /* PCIE IO address space */
+ { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
+
+ /* SPI */
+ { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+ CPU_ATTR_SPIFLASH },
+
+ /* NOR */
+ { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
+ CPU_ATTR_BOOTROM },
+};
+
+void reset_cpu(unsigned long ignored)
+{
+ struct mvebu_system_registers *reg =
+ (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
+
+ writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
+ writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
+ while (1)
+ ;
+}
+
+int mvebu_soc_family(void)
+{
+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+
+ if (devid == SOC_MV78460_ID)
+ return MVEBU_SOC_AXP;
+
+ if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
+ devid == SOC_88F6828_ID)
+ return MVEBU_SOC_A38X;
+
+ return MVEBU_SOC_UNKNOWN;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+ u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
+
+ puts("SoC: ");
+
+ switch (devid) {
+ case SOC_MV78460_ID:
+ puts("MV78460-");
+ break;
+ case SOC_88F6810_ID:
+ puts("MV88F6810-");
+ break;
+ case SOC_88F6820_ID:
+ puts("MV88F6820-");
+ break;
+ case SOC_88F6828_ID:
+ puts("MV88F6828-");
+ break;
+ default:
+ puts("Unknown-");
+ break;
+ }
+
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ switch (revid) {
+ case 1:
+ puts("A0\n");
+ break;
+ case 2:
+ puts("B0\n");
+ break;
+ default:
+ printf("?? (%x)\n", revid);
+ break;
+ }
+ }
+
+ if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+ switch (revid) {
+ case MV_88F68XX_Z1_ID:
+ puts("Z1\n");
+ break;
+ case MV_88F68XX_A0_ID:
+ puts("A0\n");
+ break;
+ default:
+ printf("?? (%x)\n", revid);
+ break;
+ }
+ }
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+/*
+ * This function initialize Controller DRAM Fastpath windows.
+ * It takes the CS size information from the 0x1500 scratch registers
+ * and sets the correct windows sizes and base addresses accordingly.
+ *
+ * These values are set in the scratch registers by the Marvell
+ * DDR3 training code, which is executed by the BootROM before the
+ * main payload (U-Boot) is executed. This training code is currently
+ * only available in the Marvell U-Boot version. It needs to be
+ * ported to mainline U-Boot SPL at some point.
+ */
+static void update_sdram_window_sizes(void)
+{
+ u64 base = 0;
+ u32 size, temp;
+ int i;
+
+ for (i = 0; i < SDRAM_MAX_CS; i++) {
+ size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
+ if (size != 0) {
+ size |= ~(SDRAM_ADDR_MASK);
+
+ /* Set Base Address */
+ temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
+ writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
+
+ /*
+ * Check if out of max window size and resize
+ * the window
+ */
+ temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
+ ~(SDRAM_ADDR_MASK)) | 1;
+ temp |= (size & SDRAM_ADDR_MASK);
+ writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
+
+ base += ((u64)size + 1);
+ } else {
+ /*
+ * Disable window if not used, otherwise this
+ * leads to overlapping enabled windows with
+ * pretty strange results
+ */
+ clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
+ }
+ }
+}
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+
+ /*
+ * We need to call mvebu_mbus_probe() before calling
+ * update_sdram_window_sizes() as it disables all previously
+ * configured mbus windows and then configures them as
+ * required for U-Boot. Calling update_sdram_window_sizes()
+ * without this configuration will not work, as the internal
+ * registers can't be accessed reliably because of potenial
+ * double mapping.
+ * After updating the SDRAM access windows we need to call
+ * mvebu_mbus_probe() again, as this now correctly configures
+ * the SDRAM areas that are later used by the MVEBU drivers
+ * (e.g. USB, NETA).
+ */
+
+ /*
+ * First disable all windows
+ */
+ mvebu_mbus_probe(NULL, 0);
+
+ if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+ /*
+ * Now the SDRAM access windows can be reconfigured using
+ * the information in the SDRAM scratch pad registers
+ */
+ update_sdram_window_sizes();
+ }
+
+ /*
+ * Finally the mbus windows can be configured with the
+ * updated SDRAM sizes
+ */
+ mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
+
+ return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ /* Nothing yet, perhaps we need something here later */
+ return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MVNETA
+int cpu_eth_init(bd_t *bis)
+{
+ u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
+ MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
+ u8 phy_addr[] = CONFIG_PHY_ADDR;
+ int i;
+
+ /*
+ * Only Armada XP supports all 4 ethernet interfaces. A38x has
+ * slightly different base addresses for its 2-3 interfaces.
+ */
+ if (mvebu_soc_family() != MVEBU_SOC_AXP) {
+ enet_base[1] = MVEBU_EGIGA2_BASE;
+ enet_base[2] = MVEBU_EGIGA3_BASE;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
+ mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
+
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Avoid problem with e.g. neta ethernet driver */
+ invalidate_dcache_all();
+
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sdram_bank {
+ u32 win_bar;
+ u32 win_sz;
+};
+
+struct sdram_addr_dec {
+ struct sdram_bank sdram_bank[4];
+};
+
+#define REG_CPUCS_WIN_ENABLE (1 << 0)
+#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
+#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
+#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
+
+/*
+ * mvebu_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 mvebu_sdram_bar(enum memory_bank bank)
+{
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
+ u32 result = 0;
+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+
+ result = readl(&base->sdram_bank[bank].win_bar);
+ return result;
+}
+
+/*
+ * mvebu_sdram_bs_set - writes SDRAM Bank size
+ */
+static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
+ /* Read current register value */
+ u32 reg = readl(&base->sdram_bank[bank].win_sz);
+
+ /* Clear window size */
+ reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
+
+ /* Set new window size */
+ reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
+
+ writel(reg, &base->sdram_bank[bank].win_sz);
+}
+
+/*
+ * mvebu_sdram_bs - reads SDRAM Bank size
+ */
+u32 mvebu_sdram_bs(enum memory_bank bank)
+{
+ struct sdram_addr_dec *base =
+ (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
+ u32 result = 0;
+ u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
+
+ if ((!enable) || (bank > BANK3))
+ return 0;
+ result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
+ result += 0x01000000;
+ return result;
+}
+
+void mvebu_sdram_size_adjust(enum memory_bank bank)
+{
+ u32 size;
+
+ /* probe currently equipped RAM size */
+ size = get_ram_size((void *)mvebu_sdram_bar(bank),
+ mvebu_sdram_bs(bank));
+
+ /* adjust SDRAM window size accordingly */
+ mvebu_sdram_bs_set(bank, size);
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+ int i;
+
+ gd->ram_size = 0;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
+ gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
+ /*
+ * It is assumed that all memory banks are consecutive
+ * and without gaps.
+ * If the gap is found, ram_size will be reported for
+ * consecutive memory only
+ */
+ if (gd->bd->bi_dram[i].start != gd->ram_size)
+ break;
+
+ /*
+ * Don't report more than 3GiB of SDRAM, otherwise there is no
+ * address space left for the internal registers etc.
+ */
+ if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
+ (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
+ gd->ram_size += gd->bd->bi_dram[i].size;
+
+ }
+
+ for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* If above loop terminated prematurely, we need to set
+ * remaining banks' start address & size as 0. Otherwise other
+ * u-boot functions and Linux kernel gets wrong values which
+ * could result in crash */
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+ dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+/*
+ * mvebu_config_gpio - GPIO configuration
+ */
+void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
+ u32 gpp0_oe, u32 gpp1_oe)
+{
+ struct kwgpio_registers *gpio0reg =
+ (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
+ struct kwgpio_registers *gpio1reg =
+ (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
+
+ /* Init GPIOS to default values as per board requirement */
+ writel(gpp0_oe_val, &gpio0reg->dout);
+ writel(gpp1_oe_val, &gpio1reg->dout);
+ writel(gpp0_oe, &gpio0reg->oe);
+ writel(gpp1_oe, &gpio1reg->oe);
+}
--- /dev/null
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * This file should be included in board config header file.
+ *
+ * It supports common definitions for MVEBU platforms
+ */
+
+#ifndef _MVEBU_CONFIG_H
+#define _MVEBU_CONFIG_H
+
+#include <asm/arch/soc.h>
+
+#if defined(CONFIG_ARMADA_XP)
+#define MV88F78X60 /* for the DDR training bin_hdr code */
+#endif
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/*
+ * By default kwbimage.cfg from board specific folder is used
+ * If for some board, different configuration file need to be used,
+ * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
+ */
+#ifndef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#endif /* CONFIG_SYS_KWD_CONFIG */
+
+/* Add target to build it automatically upon "make" */
+#ifdef CONFIG_SPL
+#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
+#endif
+
+/* end of 16M scrubbed by training in bootrom */
+#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
+#define CONFIG_NR_DRAM_BANKS_MAX 2
+
+#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
+
+/*
+ * SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_HARD_SPI 1
+#define CONFIG_KIRKWOOD_SPI 1
+#ifndef CONFIG_ENV_SPI_BUS
+# define CONFIG_ENV_SPI_BUS 0
+#endif
+#ifndef CONFIG_ENV_SPI_CS
+# define CONFIG_ENV_SPI_CS 0
+#endif
+#ifndef CONFIG_ENV_SPI_MAX_HZ
+# define CONFIG_ENV_SPI_MAX_HZ 50000000
+#endif
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_PHYLIB
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#ifndef CONFIG_SYS_I2C_SOFT
+#define CONFIG_I2C_MVTWSI
+#endif
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+#endif
+
+/* Common SPL configuration */
+#ifndef CONFIG_SPL_LDSCRIPT
+#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-mvebu/u-boot-spl.lds"
+#endif
+
+#endif /* __MVEBU_CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MVEBU_CPU_H
+#define _MVEBU_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
+#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
+
+enum memory_bank {
+ BANK0,
+ BANK1,
+ BANK2,
+ BANK3
+};
+
+enum cpu_winen {
+ CPU_WIN_DISABLE,
+ CPU_WIN_ENABLE
+};
+
+enum cpu_target {
+ CPU_TARGET_DRAM = 0x0,
+ CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
+ CPU_TARGET_ETH23 = 0x3,
+ CPU_TARGET_PCIE02 = 0x4,
+ CPU_TARGET_ETH01 = 0x7,
+ CPU_TARGET_PCIE13 = 0x8,
+ CPU_TARGET_SASRAM = 0x9,
+ CPU_TARGET_NAND = 0xd,
+};
+
+enum cpu_attrib {
+ CPU_ATTR_SASRAM = 0x01,
+ CPU_ATTR_DRAM_CS0 = 0x0e,
+ CPU_ATTR_DRAM_CS1 = 0x0d,
+ CPU_ATTR_DRAM_CS2 = 0x0b,
+ CPU_ATTR_DRAM_CS3 = 0x07,
+ CPU_ATTR_NANDFLASH = 0x2f,
+ CPU_ATTR_SPIFLASH = 0x1e,
+ CPU_ATTR_BOOTROM = 0x1d,
+ CPU_ATTR_PCIE_IO = 0xe0,
+ CPU_ATTR_PCIE_MEM = 0xe8,
+ CPU_ATTR_DEV_CS0 = 0x3e,
+ CPU_ATTR_DEV_CS1 = 0x3d,
+ CPU_ATTR_DEV_CS2 = 0x3b,
+ CPU_ATTR_DEV_CS3 = 0x37,
+};
+
+enum {
+ MVEBU_SOC_AXP,
+ MVEBU_SOC_A38X,
+ MVEBU_SOC_UNKNOWN,
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define DEFADR_PCI_MEM 0x90000000
+#define DEFADR_PCI_IO 0xC0000000
+#define DEFADR_SPIF 0xF4000000
+#define DEFADR_BOOTROM 0xF8000000
+
+struct mbus_win {
+ u32 base;
+ u32 size;
+ u8 target;
+ u8 attr;
+};
+
+/*
+ * System registers
+ * Ref: Datasheet sec:A.28
+ */
+struct mvebu_system_registers {
+ u8 pad1[0x60];
+ u32 rstoutn_mask; /* 0x60 */
+ u32 sys_soft_rst; /* 0x64 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct kwgpio_registers {
+ u32 dout;
+ u32 oe;
+ u32 blink_en;
+ u32 din_pol;
+ u32 din;
+ u32 irq_cause;
+ u32 irq_mask;
+ u32 irq_level;
+};
+
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
+/*
+ * functions
+ */
+unsigned int mvebu_sdram_bar(enum memory_bank bank);
+unsigned int mvebu_sdram_bs(enum memory_bank bank);
+void mvebu_sdram_size_adjust(enum memory_bank bank);
+int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
+
+/*
+ * Highspeed SERDES PHY config init, ported from bin_hdr
+ * to mainline U-Boot
+ */
+int serdes_phy_config(void);
+
+/*
+ * DDR3 init / training code ported from Marvell bin_hdr. Now
+ * available in mainline U-Boot in:
+ * drivers/ddr/mvebu/
+ */
+int ddr3_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _MVEBU_CPU_H */
--- /dev/null
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for the Marvell's Feroceon CPU core.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MVEBU_SOC_H
+#define _MVEBU_SOC_H
+
+#define SOC_MV78460_ID 0x7846
+#define SOC_88F6810_ID 0x6810
+#define SOC_88F6820_ID 0x6820
+#define SOC_88F6828_ID 0x6828
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID 0x0
+#define MV_88F68XX_A0_ID 0x4
+
+/* TCLK Core Clock definition */
+#ifndef CONFIG_SYS_TCLK
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+#endif
+
+/* SOC specific definations */
+#define INTREG_BASE 0xd0000000
+#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
+#define SOC_REGS_PHY_BASE 0xf1000000
+#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
+
+#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
+#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
+#define CONFIG_SYS_PL310_BASE MVEBU_L2_CACHE_BASE
+#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
+#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
+#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
+#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
+#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
+#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
+#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
+#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
+#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
+#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
+#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
+#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
+#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
+#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
+#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
+#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
+#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
+
+#define SDRAM_MAX_CS 4
+#define SDRAM_ADDR_MASK 0xFF000000
+
+/* MVEBU CPU memory windows */
+#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
+#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
+#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
+
+#endif /* _MVEBU_SOC_H */
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+/*
+ * cache_inv - invalidate Cache line
+ * r0 - dest
+ */
+ .global cache_inv
+ .type cache_inv, %function
+ cache_inv:
+
+ stmfd sp!, {r1-r12}
+
+ mcr p15, 0, r0, c7, c6, 1
+
+ ldmfd sp!, {r1-r12}
+ bx lr
+
+
+/*
+ * flush_l1_v6 - l1 cache clean invalidate
+ * r0 - dest
+ */
+ .global flush_l1_v6
+ .type flush_l1_v6, %function
+ flush_l1_v6:
+
+ stmfd sp!, {r1-r12}
+
+ mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
+ mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
+ mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
+
+ ldmfd sp!, {r1-r12}
+ bx lr
+
+
+/*
+ * flush_l1_v7 - l1 cache clean invalidate
+ * r0 - dest
+ */
+ .global flush_l1_v7
+ .type flush_l1_v7, %function
+ flush_l1_v7:
+
+ stmfd sp!, {r1-r12}
+
+ dmb /* @data memory barrier */
+ mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
+ dsb /* @data sync barrier */
+
+ ldmfd sp!, {r1-r12}
+ bx lr
--- /dev/null
+/*
+ * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
+ * 370/XP, Dove, Orion5x and MV78xx0)
+ *
+ * Ported from the Barebox version to U-Boot by:
+ * Stefan Roese <sr@denx.de>
+ *
+ * The Barebox version is:
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * based on mbus driver from Linux
+ * (C) Copyright 2008 Marvell Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * The Marvell EBU SoCs have a configurable physical address space:
+ * the physical address at which certain devices (PCIe, NOR, NAND,
+ * etc.) sit can be configured. The configuration takes place through
+ * two sets of registers:
+ *
+ * - One to configure the access of the CPU to the devices. Depending
+ * on the families, there are between 8 and 20 configurable windows,
+ * each can be use to create a physical memory window that maps to a
+ * specific device. Devices are identified by a tuple (target,
+ * attribute).
+ *
+ * - One to configure the access to the CPU to the SDRAM. There are
+ * either 2 (for Dove) or 4 (for other families) windows to map the
+ * SDRAM into the physical address space.
+ *
+ * This driver:
+ *
+ * - Reads out the SDRAM address decoding windows at initialization
+ * time, and fills the mbus_dram_info structure with these
+ * informations. The exported function mv_mbus_dram_info() allow
+ * device drivers to get those informations related to the SDRAM
+ * address decoding windows. This is because devices also have their
+ * own windows (configured through registers that are part of each
+ * device register space), and therefore the drivers for Marvell
+ * devices have to configure those device -> SDRAM windows to ensure
+ * that DMA works properly.
+ *
+ * - Provides an API for platform code or device drivers to
+ * dynamically add or remove address decoding windows for the CPU ->
+ * device accesses. This API is mvebu_mbus_add_window_by_id(),
+ * mvebu_mbus_add_window_remap_by_id() and
+ * mvebu_mbus_del_window().
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#define BIT(nr) (1UL << (nr))
+
+/* DDR target is the same on all platforms */
+#define TARGET_DDR 0
+
+/* CPU Address Decode Windows registers */
+#define WIN_CTRL_OFF 0x0000
+#define WIN_CTRL_ENABLE BIT(0)
+#define WIN_CTRL_TGT_MASK 0xf0
+#define WIN_CTRL_TGT_SHIFT 4
+#define WIN_CTRL_ATTR_MASK 0xff00
+#define WIN_CTRL_ATTR_SHIFT 8
+#define WIN_CTRL_SIZE_MASK 0xffff0000
+#define WIN_CTRL_SIZE_SHIFT 16
+#define WIN_BASE_OFF 0x0004
+#define WIN_BASE_LOW 0xffff0000
+#define WIN_BASE_HIGH 0xf
+#define WIN_REMAP_LO_OFF 0x0008
+#define WIN_REMAP_LOW 0xffff0000
+#define WIN_REMAP_HI_OFF 0x000c
+
+#define ATTR_HW_COHERENCY (0x1 << 4)
+
+#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
+#define DDR_BASE_CS_HIGH_MASK 0xf
+#define DDR_BASE_CS_LOW_MASK 0xff000000
+#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
+#define DDR_SIZE_ENABLED BIT(0)
+#define DDR_SIZE_CS_MASK 0x1c
+#define DDR_SIZE_CS_SHIFT 2
+#define DDR_SIZE_MASK 0xff000000
+
+#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
+
+struct mvebu_mbus_state;
+
+struct mvebu_mbus_soc_data {
+ unsigned int num_wins;
+ unsigned int num_remappable_wins;
+ unsigned int (*win_cfg_offset)(const int win);
+ void (*setup_cpu_target)(struct mvebu_mbus_state *s);
+};
+
+struct mvebu_mbus_state mbus_state
+ __attribute__ ((section(".data")));
+static struct mbus_dram_target_info mbus_dram_info
+ __attribute__ ((section(".data")));
+
+/*
+ * Functions to manipulate the address decoding windows
+ */
+
+static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
+ int win, int *enabled, u64 *base,
+ u32 *size, u8 *target, u8 *attr,
+ u64 *remap)
+{
+ void __iomem *addr = mbus->mbuswins_base +
+ mbus->soc->win_cfg_offset(win);
+ u32 basereg = readl(addr + WIN_BASE_OFF);
+ u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
+
+ if (!(ctrlreg & WIN_CTRL_ENABLE)) {
+ *enabled = 0;
+ return;
+ }
+
+ *enabled = 1;
+ *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
+ *base |= (basereg & WIN_BASE_LOW);
+ *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
+
+ if (target)
+ *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
+
+ if (attr)
+ *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
+
+ if (remap) {
+ if (win < mbus->soc->num_remappable_wins) {
+ u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
+ u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
+ *remap = ((u64)remap_hi << 32) | remap_low;
+ } else {
+ *remap = 0;
+ }
+ }
+}
+
+static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
+ int win)
+{
+ void __iomem *addr;
+
+ addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
+
+ writel(0, addr + WIN_BASE_OFF);
+ writel(0, addr + WIN_CTRL_OFF);
+ if (win < mbus->soc->num_remappable_wins) {
+ writel(0, addr + WIN_REMAP_LO_OFF);
+ writel(0, addr + WIN_REMAP_HI_OFF);
+ }
+}
+
+/* Checks whether the given window number is available */
+static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
+ const int win)
+{
+ void __iomem *addr = mbus->mbuswins_base +
+ mbus->soc->win_cfg_offset(win);
+ u32 ctrl = readl(addr + WIN_CTRL_OFF);
+ return !(ctrl & WIN_CTRL_ENABLE);
+}
+
+/*
+ * Checks whether the given (base, base+size) area doesn't overlap an
+ * existing region
+ */
+static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
+ phys_addr_t base, size_t size,
+ u8 target, u8 attr)
+{
+ u64 end = (u64)base + size;
+ int win;
+
+ for (win = 0; win < mbus->soc->num_wins; win++) {
+ u64 wbase, wend;
+ u32 wsize;
+ u8 wtarget, wattr;
+ int enabled;
+
+ mvebu_mbus_read_window(mbus, win,
+ &enabled, &wbase, &wsize,
+ &wtarget, &wattr, NULL);
+
+ if (!enabled)
+ continue;
+
+ wend = wbase + wsize;
+
+ /*
+ * Check if the current window overlaps with the
+ * proposed physical range
+ */
+ if ((u64)base < wend && end > wbase)
+ return 0;
+
+ /*
+ * Check if target/attribute conflicts
+ */
+ if (target == wtarget && attr == wattr)
+ return 0;
+ }
+
+ return 1;
+}
+
+static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
+ phys_addr_t base, size_t size)
+{
+ int win;
+
+ for (win = 0; win < mbus->soc->num_wins; win++) {
+ u64 wbase;
+ u32 wsize;
+ int enabled;
+
+ mvebu_mbus_read_window(mbus, win,
+ &enabled, &wbase, &wsize,
+ NULL, NULL, NULL);
+
+ if (!enabled)
+ continue;
+
+ if (base == wbase && size == wsize)
+ return win;
+ }
+
+ return -ENODEV;
+}
+
+static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
+ int win, phys_addr_t base, size_t size,
+ phys_addr_t remap, u8 target,
+ u8 attr)
+{
+ void __iomem *addr = mbus->mbuswins_base +
+ mbus->soc->win_cfg_offset(win);
+ u32 ctrl, remap_addr;
+
+ ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
+ (attr << WIN_CTRL_ATTR_SHIFT) |
+ (target << WIN_CTRL_TGT_SHIFT) |
+ WIN_CTRL_ENABLE;
+
+ writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
+ writel(ctrl, addr + WIN_CTRL_OFF);
+ if (win < mbus->soc->num_remappable_wins) {
+ if (remap == MVEBU_MBUS_NO_REMAP)
+ remap_addr = base;
+ else
+ remap_addr = remap;
+ writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
+ writel(0, addr + WIN_REMAP_HI_OFF);
+ }
+
+ return 0;
+}
+
+static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap, u8 target,
+ u8 attr)
+{
+ int win;
+
+ if (remap == MVEBU_MBUS_NO_REMAP) {
+ for (win = mbus->soc->num_remappable_wins;
+ win < mbus->soc->num_wins; win++)
+ if (mvebu_mbus_window_is_free(mbus, win))
+ return mvebu_mbus_setup_window(mbus, win, base,
+ size, remap,
+ target, attr);
+ }
+
+
+ for (win = 0; win < mbus->soc->num_wins; win++)
+ if (mvebu_mbus_window_is_free(mbus, win))
+ return mvebu_mbus_setup_window(mbus, win, base, size,
+ remap, target, attr);
+
+ return -ENOMEM;
+}
+
+/*
+ * SoC-specific functions and definitions
+ */
+
+static unsigned int armada_370_xp_mbus_win_offset(int win)
+{
+ /* The register layout is a bit annoying and the below code
+ * tries to cope with it.
+ * - At offset 0x0, there are the registers for the first 8
+ * windows, with 4 registers of 32 bits per window (ctrl,
+ * base, remap low, remap high)
+ * - Then at offset 0x80, there is a hole of 0x10 bytes for
+ * the internal registers base address and internal units
+ * sync barrier register.
+ * - Then at offset 0x90, there the registers for 12
+ * windows, with only 2 registers of 32 bits per window
+ * (ctrl, base).
+ */
+ if (win < 8)
+ return win << 4;
+ else
+ return 0x90 + ((win - 8) << 3);
+}
+
+static unsigned int orion5x_mbus_win_offset(int win)
+{
+ return win << 4;
+}
+
+static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
+{
+ int i;
+ int cs;
+
+ mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+ for (i = 0, cs = 0; i < 4; i++) {
+ u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
+ u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
+
+ /*
+ * We only take care of entries for which the chip
+ * select is enabled, and that don't have high base
+ * address bits set (devices can only access the first
+ * 32 bits of the memory).
+ */
+ if ((size & DDR_SIZE_ENABLED) &&
+ !(base & DDR_BASE_CS_HIGH_MASK)) {
+ struct mbus_dram_window *w;
+
+ w = &mbus_dram_info.cs[cs++];
+ w->cs_index = i;
+ w->mbus_attr = 0xf & ~(1 << i);
+ w->base = base & DDR_BASE_CS_LOW_MASK;
+ w->size = (size | ~DDR_SIZE_MASK) + 1;
+ }
+ }
+ mbus_dram_info.num_cs = cs;
+}
+
+static const struct mvebu_mbus_soc_data
+armada_370_xp_mbus_data __maybe_unused = {
+ .num_wins = 20,
+ .num_remappable_wins = 8,
+ .win_cfg_offset = armada_370_xp_mbus_win_offset,
+ .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
+};
+
+static const struct mvebu_mbus_soc_data
+kirkwood_mbus_data __maybe_unused = {
+ .num_wins = 8,
+ .num_remappable_wins = 4,
+ .win_cfg_offset = orion5x_mbus_win_offset,
+ .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
+};
+
+/*
+ * Public API of the driver
+ */
+const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
+{
+ return &mbus_dram_info;
+}
+
+int mvebu_mbus_add_window_remap_by_id(unsigned int target,
+ unsigned int attribute,
+ phys_addr_t base, size_t size,
+ phys_addr_t remap)
+{
+ struct mvebu_mbus_state *s = &mbus_state;
+
+ if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
+ printf("Cannot add window '%x:%x', conflicts with another window\n",
+ target, attribute);
+ return -EINVAL;
+ }
+
+ return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
+}
+
+int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
+ phys_addr_t base, size_t size)
+{
+ return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
+ size, MVEBU_MBUS_NO_REMAP);
+}
+
+int mvebu_mbus_del_window(phys_addr_t base, size_t size)
+{
+ int win;
+
+ win = mvebu_mbus_find_window(&mbus_state, base, size);
+ if (win < 0)
+ return win;
+
+ mvebu_mbus_disable_window(&mbus_state, win);
+ return 0;
+}
+
+int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
+ u32 base, u32 size, u8 target, u8 attr)
+{
+ if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
+ printf("Cannot add window '%04x:%04x', conflicts with another window\n",
+ target, attr);
+ return -EBUSY;
+ }
+
+ /*
+ * In U-Boot we first try to add the mbus window to the remap windows.
+ * If this fails, lets try to add the windows to the non-remap windows.
+ */
+ if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
+ if (mvebu_mbus_alloc_window(mbus, base, size,
+ MVEBU_MBUS_NO_REMAP, target, attr))
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+int mvebu_mbus_probe(struct mbus_win windows[], int count)
+{
+ int win;
+ int ret;
+ int i;
+
+#if defined(CONFIG_KIRKWOOD)
+ mbus_state.soc = &kirkwood_mbus_data;
+#endif
+#if defined(CONFIG_ARMADA_XP)
+ mbus_state.soc = &armada_370_xp_mbus_data;
+#endif
+
+ mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
+ mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
+
+ for (win = 0; win < mbus_state.soc->num_wins; win++)
+ mvebu_mbus_disable_window(&mbus_state, win);
+
+ mbus_state.soc->setup_cpu_target(&mbus_state);
+
+ /* Setup statically declared windows in the DT */
+ for (i = 0; i < count; i++) {
+ u32 base, size;
+ u8 target, attr;
+
+ target = windows[i].target;
+ attr = windows[i].attr;
+ base = windows[i].base;
+ size = windows[i].size;
+ ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
--- /dev/null
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o
+obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
--- /dev/null
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BOARD_ENV_SPEC
+#define __BOARD_ENV_SPEC
+
+/* Board specific configuration */
+
+/* KW40 */
+#define MV_6710_DEV_ID 0x6710
+
+#define MV_6710_Z1_REV 0x0
+#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV)
+#define MV_6710_Z1_NAME "MV6710 Z1"
+
+/* Armada XP Family */
+#define MV_78130_DEV_ID 0x7813
+#define MV_78160_DEV_ID 0x7816
+#define MV_78230_DEV_ID 0x7823
+#define MV_78260_DEV_ID 0x7826
+#define MV_78460_DEV_ID 0x7846
+#define MV_78000_DEV_ID 0x7888
+
+#define MV_FPGA_DEV_ID 0x2107
+
+#define MV_78XX0_Z1_REV 0x0
+
+/* boards ID numbers */
+#define BOARD_ID_BASE 0x0
+
+/* New board ID numbers */
+#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
+#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
+#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
+#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
+#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1)
+#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1)
+#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1)
+#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1)
+#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1)
+#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
+#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
+#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
+#define INVALID_BAORD_ID 0xFFFFFFFF
+
+/* Sample at Reset */
+#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
+
+/* BIOS Modes related defines */
+
+#define SAR0_BOOTWIDTH_OFFSET 3
+#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET)
+#define SAR0_BOOTSRC_OFFSET 5
+#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET)
+
+#define SAR0_L2_SIZE_OFFSET 19
+#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET)
+#define SAR0_CPU_FREQ_OFFSET 21
+#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET)
+#define SAR0_FABRIC_FREQ_OFFSET 24
+#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET)
+#define SAR0_CPU0CORE_OFFSET 31
+#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET)
+#define SAR1_CPU0CORE_OFFSET 0
+#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET)
+
+#define PEX_CLK_100MHZ_OFFSET 2
+#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET)
+
+#define SAR1_FABRIC_MODE_OFFSET 19
+#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET)
+#define SAR1_CPU_MODE_OFFSET 20
+#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET)
+
+#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
+
+
+#define CORE_AVS_CONTROL_0REG 0x18300
+#define CORE_AVS_CONTROL_2REG 0x18308
+#define CPU_AVS_CONTROL2_REG 0x20868
+#define CPU_AVS_CONTROL0_REG 0x20860
+#define GENERAL_PURPOSE_RESERVED0_REG 0x182E0
+
+#define MSAR_TCLK_OFFS 28
+#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
+
+
+/* Controler environment registers offsets */
+#define GEN_PURP_RES_1_REG 0x182F4
+#define GEN_PURP_RES_2_REG 0x182F8
+
+/* registers offsets */
+#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40))
+#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
+#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit))
+#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0)
+
+#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
+#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */
+#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
+#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08)
+#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C)
+#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
+#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14)
+#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18)
+#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C)
+#define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40))
+#define GPP_64_66_DATA_OUT_SET_REG 0x181A4
+#define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40))
+#define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0
+#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40)
+
+#define MV_GPP66 (1 << 2)
+
+/* Relevant for MV78XX0 */
+#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20)
+#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24)
+
+/* This define describes the maximum number of supported PEX Interfaces */
+#define MV_PEX_MAX_IF 10
+#define MV_PEX_MAX_UNIT 4
+
+#define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12)))
+
+#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \
+ ((unit)/2 * 0x2000) + 0x1B00)
+
+#define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000)
+
+#define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804)
+#define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C)
+#define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918)
+#define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920)
+#define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058)
+#define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C)
+#define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810)
+#define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834)
+#define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838)
+#define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C)
+#define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840)
+
+#define MV_ETH_BASE_ADDR (0x72000)
+#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \
+ 0x40000 + ((port) % 2) * 0x4000)
+#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
+
+
+#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
+#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
+#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
+#define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0)
+#define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4)
+#define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20)
+#define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38)
+#define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0)
+
+#define SERDES_LINE_MUX_REG_0_7 0x18270
+#define SERDES_LINE_MUX_REG_8_15 0x18274
+#define QSGMII_CONTROL_1_REG 0x18404
+
+/* SOC_CTRL_REG fields */
+#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3)
+#define SCR_PEX_ENA_MASK(pex) (1 << pex)
+
+#define PCIE0_QUADX1_EN (1<<7)
+#define PCIE1_QUADX1_EN (1<<8)
+
+#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7)
+#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex))
+
+#define PCIE1_CLK_OUT_EN_OFF 5
+#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF)
+
+#define PCIE0_CLK_OUT_EN_OFF 4
+#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF)
+
+#define SCR_PEX0_4BY1_OFFS 7
+#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS)
+
+#define SCR_PEX1_4BY1_OFFS 8
+#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
+
+
+#define MV_MISC_REGS_OFFSET (0x18200)
+#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
+#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
+
+/*
+ * PCI Express Control and Status Registers
+ */
+#define MAX_PEX_DEVICES 32
+#define MAX_PEX_FUNCS 8
+#define MAX_PEX_BUSSES 256
+
+#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
+#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
+
+#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
+#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
+
+#define PXSR_DL_DOWN 0x1 /* DL_Down indication. */
+#define PXCAR_CONFIG_EN (1 << 31)
+#define PEX_STATUS_AND_COMMAND 0x004
+#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */
+
+/* PCI Express Configuration Address Register */
+
+/* PEX_CFG_ADDR_REG (PXCAR) */
+#define PXCAR_REG_NUM_OFFS 2
+#define PXCAR_REG_NUM_MAX 0x3F
+#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
+#define PXCAR_FUNC_NUM_OFFS 8
+#define PXCAR_FUNC_NUM_MAX 0x7
+#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
+#define PXCAR_DEVICE_NUM_OFFS 11
+#define PXCAR_DEVICE_NUM_MAX 0x1F
+#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
+#define PXCAR_BUS_NUM_OFFS 16
+#define PXCAR_BUS_NUM_MAX 0xFF
+#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
+#define PXCAR_EXT_REG_NUM_OFFS 24
+#define PXCAR_EXT_REG_NUM_MAX 0xF
+
+#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
+#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
+
+
+#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
+#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
+#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
+#define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90)
+#define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00)
+#define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04)
+#define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10)
+#define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18)
+#define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20)
+#define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30)
+#define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C)
+#define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50)
+#define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60)
+#define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64)
+
+#define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */
+#define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS)
+#define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS)
+#define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS)
+
+#define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8)
+#define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC)
+#define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900)
+
+#define PEX_CAPABILITY_REG 0x60
+#define PEX_DEV_CAPABILITY_REG 0x64
+#define PEX_DEV_CTRL_STAT_REG 0x68
+#define PEX_LINK_CAPABILITY_REG 0x6C
+#define PEX_LINK_CTRL_STAT_REG 0x70
+#define PEX_LINK_CTRL_STAT_2_REG 0x90
+
+#endif /* __BOARD_ENV_SPEC */
--- /dev/null
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "high_speed_env_spec.h"
+#include "board_env_spec.h"
+
+#define SERDES_VERION "2.1.5"
+#define ENDED_OK "High speed PHY - Ended Successfully\n"
+
+static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
+
+extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
+
+extern u8 rd78460gp_twsi_dev[];
+extern u8 db88f78xx0rev2_twsi_dev[];
+
+u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
+int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
+int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
+
+#define MV_BOARD_PEX_MODULE_ADDR 0x23
+#define MV_BOARD_PEX_MODULE_ID 1
+#define MV_BOARD_ETM_MODULE_ID 2
+
+#define PEX_MODULE_DETECT 1
+#define ETM_MODULE_DETECT 2
+
+#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
+#define PEX_CAPABILITY_GET(satr) (satr & 1)
+#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
+
+/* Static parametes */
+static int config_module;
+static int switch_module;
+
+/* Local function */
+static u32 board_id_get(void)
+{
+#if defined(CONFIG_DB_88F78X60)
+ return DB_88F78XX0_BP_ID;
+#elif defined(CONFIG_RD_88F78460_SERVER)
+ return RD_78460_SERVER_ID;
+#elif defined(CONFIG_RD_78460_SERVER_REV2)
+ return RD_78460_SERVER_REV2_ID;
+#elif defined(CONFIG_DB_78X60_PCAC)
+ return DB_78X60_PCAC_ID;
+#elif defined(CONFIG_DB_88F78X60_REV2)
+ return DB_88F78XX0_BP_REV2_ID;
+#elif defined(CONFIG_RD_78460_NAS)
+ return RD_78460_NAS_ID;
+#elif defined(CONFIG_DB_78X60_AMC)
+ return DB_78X60_AMC_ID;
+#elif defined(CONFIG_DB_78X60_PCAC_REV2)
+ return DB_78X60_PCAC_REV2_ID;
+#elif defined(CONFIG_DB_784MP_GP)
+ return DB_784MP_GP_ID;
+#elif defined(CONFIG_RD_78460_CUSTOMER)
+ return RD_78460_CUSTOMER_ID;
+#else
+ /*
+ * Return 0 here for custom board as this should not be used
+ * for custom boards.
+ */
+ return 0;
+#endif
+}
+
+static u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+ u8 data;
+ u8 *dev;
+ u32 board_id = board_id_get();
+ int ret;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ switch (board_id) {
+ case DB_784MP_GP_ID:
+ dev = rd78460gp_twsi_dev;
+
+ break;
+ case DB_88F78XX0_BP_ID:
+ case DB_88F78XX0_BP_REV2_ID:
+ dev = db88f78xx0rev2_twsi_dev;
+ break;
+
+ case DB_78X60_PCAC_ID:
+ case FPGA_88F78XX0_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_SERVER_REV2_ID:
+ default:
+ return 0;
+ }
+
+ /* Read MPP module ID */
+ ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
+ if (ret)
+ return MV_ERROR;
+
+ return data;
+}
+
+static int board_modules_scan(void)
+{
+ u8 val;
+ u32 board_id = board_id_get();
+ int ret;
+
+ /* Perform scan only for DB board */
+ if ((board_id == DB_88F78XX0_BP_ID) ||
+ (board_id == DB_88F78XX0_BP_REV2_ID)) {
+ /* reset modules flags */
+ config_module = 0;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* SERDES module (only PEX model is supported now) */
+ ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
+ if (ret)
+ return MV_ERROR;
+
+ if (val == MV_BOARD_PEX_MODULE_ID)
+ config_module = PEX_MODULE_DETECT;
+ if (val == MV_BOARD_ETM_MODULE_ID)
+ config_module = ETM_MODULE_DETECT;
+ } else if (board_id == RD_78460_NAS_ID) {
+ switch_module = 0;
+ if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
+ switch_module = 1;
+ }
+
+ return MV_OK;
+}
+
+u32 pex_max_unit_get(void)
+{
+ /*
+ * TODO:
+ * Right now only MV78460 is supported. Other SoC's might need
+ * a different value here.
+ */
+ return MV_PEX_MAX_UNIT;
+}
+
+u32 pex_max_if_get(void)
+{
+ /*
+ * TODO:
+ * Right now only MV78460 is supported. Other SoC's might need
+ * a different value here.
+ */
+ return MV_PEX_MAX_IF;
+}
+
+u8 board_cpu_freq_get(void)
+{
+ u32 sar;
+ u32 sar_msb;
+
+ sar = reg_read(MPP_SAMPLE_AT_RESET(0));
+ sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
+ return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
+}
+
+__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ u32 board_id;
+ u32 serdes_cfg_val = 0; /* default */
+
+ board_id = board_id_get();
+
+ switch (board_id) {
+ case DB_784MP_GP_ID:
+ serdes_cfg_val = 0;
+ break;
+ }
+
+ return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
+}
+
+u16 ctrl_model_get(void)
+{
+ /* Right now only MV78460 supported */
+ return MV_78460_DEV_ID;
+}
+
+u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
+{
+ if (line_num < 8)
+ return (info->line0_7 >> (line_num << 2)) & 0xF;
+ else
+ return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
+}
+
+int serdes_phy_config(void)
+{
+ int status = MV_OK;
+ u32 line_cfg;
+ u8 line_num;
+ /* addr/value for each line @ every setup step */
+ u32 addr[16][11], val[16][11];
+ u8 pex_unit, pex_line_num;
+ u8 sgmii_port = 0;
+ u32 tmp;
+ u32 in_direct;
+ u8 max_serdes_lines;
+ MV_BIN_SERDES_CFG *info;
+ u8 satr11;
+ u8 sata_port;
+ u8 freq;
+ u8 device_rev;
+ u32 rx_high_imp_mode;
+ u16 ctrl_mode;
+ u32 board_id = board_id_get();
+ u32 pex_if;
+ u32 pex_if_num;
+
+ /*
+ * TODO:
+ * Right now we only support the MV78460 with 16 serdes lines
+ */
+ max_serdes_lines = 16;
+ if (max_serdes_lines == 0)
+ return MV_OK;
+
+ switch (board_id) {
+ case DB_78X60_AMC_ID:
+ case DB_78X60_PCAC_REV2_ID:
+ case RD_78460_CUSTOMER_ID:
+ case RD_78460_SERVER_ID:
+ case RD_78460_SERVER_REV2_ID:
+ case DB_78X60_PCAC_ID:
+ satr11 = (0x1 << 1) | 1;
+ break;
+ case FPGA_88F78XX0_ID:
+ case RD_78460_NAS_ID:
+ satr11 = (0x0 << 1) | 1;
+ break;
+ case DB_88F78XX0_BP_REV2_ID:
+ case DB_784MP_GP_ID:
+ case DB_88F78XX0_BP_ID:
+ satr11 = board_sat_r_get(1, 1);
+ if ((u8) MV_ERROR == (u8) satr11)
+ return MV_ERROR;
+ break;
+ }
+
+ board_modules_scan();
+ memset(addr, 0, sizeof(addr));
+ memset(val, 0, sizeof(val));
+
+ /* Check if DRAM is already initialized */
+ if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
+ (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
+ DEBUG_INIT_S("High speed PHY - Version: ");
+ DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(" - 2nd boot - Skip\n");
+ return MV_OK;
+ }
+ DEBUG_INIT_S("High speed PHY - Version: ");
+ DEBUG_INIT_S(SERDES_VERION);
+ DEBUG_INIT_S(" (COM-PHY-V20)\n");
+
+ /*
+ * AVS : disable AVS for frequency less than 1333
+ */
+ freq = board_cpu_freq_get();
+ device_rev = mv_ctrl_rev_get();
+
+ if (device_rev == 2) { /* for B0 only */
+ u32 cpu_avs;
+ u8 fabric_freq;
+ cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
+ DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
+ cpu_avs &= ~(1 << 9);
+
+ if ((0x4 == freq) || (0xB == freq)) {
+ u32 tmp2;
+
+ tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
+ DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
+ /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
+ tmp2 |= 0x0FF;
+ reg_write(CPU_AVS_CONTROL0_REG, tmp2);
+ DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
+ cpu_avs |= (1 << 9); /* cpu avs enable */
+ cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
+ fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
+ SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
+ if ((0xB == freq) && (5 == fabric_freq)) {
+ u32 core_avs;
+
+ core_avs = reg_read(CORE_AVS_CONTROL_0REG);
+ DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
+
+ /*
+ * Set core lower limit = 0.9V &
+ * core upper limit = 0.9125V
+ */
+ core_avs &= ~(0xff);
+ core_avs |= 0x0E;
+ reg_write(CORE_AVS_CONTROL_0REG, core_avs);
+ DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
+
+ core_avs = reg_read(CORE_AVS_CONTROL_2REG);
+ DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
+ core_avs |= (1 << 9); /* core AVS enable */
+ reg_write(CORE_AVS_CONTROL_2REG, core_avs);
+ DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
+
+ tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
+ DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
+ tmp2);
+ tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
+ reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
+ DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
+ tmp2);
+ }
+ }
+ reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
+ DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
+ }
+
+ info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
+ DEBUG_INIT_FULL_S("info->line0_7= 0x");
+ DEBUG_INIT_FULL_D(info->line0_7, 8);
+ DEBUG_INIT_FULL_S(" info->line8_15= 0x");
+ DEBUG_INIT_FULL_D(info->line8_15, 8);
+ DEBUG_INIT_FULL_S("\n");
+
+ if (info == NULL) {
+ DEBUG_INIT_S("Hight speed PHY Error #1\n");
+ return MV_ERROR;
+ }
+
+ if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
+ DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
+ reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
+ info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
+ mdelay(100);
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
+ reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
+ }
+
+ /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
+ DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /* 1. GLOB_CLK_CTRL Reset and Clock Control */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
+
+ /* 2. GLOB_TEST_CTRL Test Mode Control */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC2 << 16) | 0x200);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC2 << 16) | 0x200);
+ }
+
+ /* 3. GLOB_CLK_SRC_LO Clock Source Low */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC3 << 16) | 0x0F);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC3 << 16) | 0x0F);
+ }
+
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC5 << 16) | 0x11F);
+ }
+
+ /*
+ * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
+ * PU_RX,PU_TX. (bits[12:5])
+ */
+ DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ switch (line_num) {
+ case 4:
+ case 6:
+ sata_port = 0;
+ break;
+ case 5:
+ sata_port = 1;
+ break;
+ default:
+ DEBUG_INIT_C
+ ("SATA port error for serdes line: ",
+ line_num, 2);
+ return MV_ERROR;
+ }
+ tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
+ (0x11 << 5) : 0x0;
+
+ reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /*
+ * 4) Configure the desire PIN_PHY_GEN and do power
+ * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
+ */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= 0x660;
+ reg_write(SGMII_SERDES_CFG_REG(0), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ tmp &= ~((0x1ff << 5) | 0x7);
+ tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
+ (0x88 << 5) : (0x66 << 5));
+ reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ }
+
+ /* Step 3 - QSGMII enable */
+ DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /* QSGMII Active bit set to true */
+ tmp = reg_read(QSGMII_CONTROL_1_REG);
+ DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
+ tmp |= (1 << 30);
+#ifdef ERRATA_GL_6572255
+ tmp |= (1 << 27);
+#endif
+ reg_write(QSGMII_CONTROL_1_REG, tmp);
+ DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
+ }
+ }
+
+ /* Step 4 - configure SERDES MUXes */
+ DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
+ if (config_module & ETM_MODULE_DETECT) {
+ reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
+ } else {
+ reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
+ }
+ reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
+ DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
+
+ /* Step 5: Activate the RX High Impedance Mode */
+ DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
+ rx_high_imp_mode = 0x8080;
+ if (device_rev == 2) /* for B0 only */
+ rx_high_imp_mode |= 4;
+
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+ DEBUG_INIT_FULL_S("SERDES ");
+ DEBUG_INIT_FULL_D_10(line_num, 2);
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
+ DEBUG_INIT_FULL_S(" unconnected ***\n");
+ continue;
+ }
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ DEBUG_INIT_FULL_S(" - PEX unit ");
+ DEBUG_INIT_FULL_D_10(pex_unit, 1);
+ DEBUG_INIT_FULL_S(" line= ");
+ DEBUG_INIT_FULL_D_10(pex_line_num, 1);
+ DEBUG_INIT_FULL_S("\n");
+
+ /* Needed for PEX_PHY_ACCESS_REG macro */
+ if ((line_num > 7) &&
+ (info->pex_mode[3] == PEX_BUS_MODE_X8))
+ /* lines 8 - 15 are belong to PEX3 in x8 mode */
+ pex_unit = 3;
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /*
+ * 8) Activate the RX High Impedance Mode field
+ * (bit [2]) in register /PCIe_USB Control (Each MAC
+ * contain different Access to reach its
+ * Serdes-Regfile).
+ * [PEX-Only] Set bit[12]: The analog part latches idle
+ * if PU_TX = 1 and PU_PLL =1.
+ */
+
+ /* Termination enable */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
+ in_direct = (0x48 << 16) | (pex_line_num << 24) |
+ 0x1000 | rx_high_imp_mode; /* x1 */
+ } else if ((info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4) && (pex_line_num == 0))
+ in_direct = (0x48 << 16) | (pex_line_num << 24) |
+ 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
+ else
+ in_direct = 0;
+
+ if (in_direct) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ in_direct);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ in_direct);
+ }
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * port 0 for serdes lines 4,6, and port 1 for
+ * serdes lines 5
+ */
+ sata_port = line_num & 1;
+ DEBUG_INIT_FULL_S(" - SATA port ");
+ DEBUG_INIT_FULL_D_10(sata_port, 2);
+ DEBUG_INIT_FULL_S("\n");
+ reg_write(SATA_COMPHY_CTRL_REG(sata_port),
+ rx_high_imp_mode);
+ DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
+ rx_high_imp_mode);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ DEBUG_INIT_FULL_S(" - QSGMII\n");
+ reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
+ DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
+ rx_high_imp_mode);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+ DEBUG_INIT_FULL_S(" - SGMII port ");
+ DEBUG_INIT_FULL_D_10(sgmii_port, 2);
+ DEBUG_INIT_FULL_S("\n");
+ reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
+ DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
+ rx_high_imp_mode);
+ } /* for each serdes lane */
+
+ /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
+ DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
+ tmp = reg_read(SOC_CTRL_REG);
+ DEBUG_RD_REG(SOC_CTRL_REG, tmp);
+ tmp &= 0x200;
+ if (info->pex_mode[0] == PEX_BUS_MODE_X1)
+ tmp |= PCIE0_QUADX1_EN;
+ if (info->pex_mode[1] == PEX_BUS_MODE_X1)
+ tmp |= PCIE1_QUADX1_EN;
+ if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
+ PEX_CLK_100MHZ_OFFSET) == 0x1)
+ tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
+
+ reg_write(SOC_CTRL_REG, tmp);
+ DEBUG_WR_REG(SOC_CTRL_REG, tmp);
+
+ /* 6.2 PCI Express Link Capabilities */
+ DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
+
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ /*
+ * PCI Express Control
+ * 0xX1A00 [0]:
+ * 0x0 X4-Link.
+ * 0x1 X1-Link
+ */
+ pex_unit = line_num >> 2;
+ pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+
+ /* set Common Clock Configuration */
+ tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
+ DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+ tmp |= (1 << 6);
+ reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+ DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
+
+ tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
+ DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+ tmp &= ~(0x3FF);
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
+ tmp |= (0x1 << 4);
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
+ tmp |= (0x4 << 4);
+ if (0 == PEX_CAPABILITY_GET(satr11))
+ tmp |= 0x1;
+ else
+ tmp |= 0x2;
+ DEBUG_INIT_FULL_S("Step 6.2: PEX ");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
+ reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+ DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
+
+ /*
+ * If pex is X4, no need to pass thru the other
+ * 3X1 serdes lines
+ */
+ if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
+ line_num += 3;
+ }
+ }
+
+ /*
+ * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
+ * need to config the register SOC_Misc/General Purpose2
+ * (Address= 182F8)
+ */
+ DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
+ tmp = reg_read(GEN_PURP_RES_2_REG);
+ DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
+
+ tmp &= 0xFFFF0000;
+ if (info->pex_mode[0] == PEX_BUS_MODE_X4)
+ tmp |= 0x0000000F;
+
+ if (info->pex_mode[1] == PEX_BUS_MODE_X4)
+ tmp |= 0x000000F0;
+
+ if (info->pex_mode[2] == PEX_BUS_MODE_X4)
+ tmp |= 0x00000F00;
+
+ if (info->pex_mode[3] == PEX_BUS_MODE_X4)
+ tmp |= 0x0000F000;
+
+ reg_write(GEN_PURP_RES_2_REG, tmp);
+ DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
+
+ /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
+ DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
+
+ /* Prepare PHY parameters for each step according to MUX selection */
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5])
+ * and REF_FREF_SEL (bits[4:0]) in the register Power
+ * and PLL Control (Each MAC contain different Access
+ * to reach its Serdes-Regfile).
+ */
+ if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
+ (0 == pex_line_num))
+ || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x01 << 16) | (pex_line_num << 24) |
+ 0xFC60);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x01 << 16) | (pex_line_num << 24)
+ | 0xFC60);
+ /*
+ * Step 8.1: [PEX-Only] Configure Max PLL Rate
+ * (bit 8 in KVCO Calibration Control and
+ * bits[10:9] in
+ */
+ /* Use Maximum PLL Rate(Bit 8) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x02 << 16) | (1 << 31) |
+ (pex_line_num << 24)); /* read command */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x02 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ tmp &= ~(1 << 31);
+ tmp |= (1 << 8);
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+
+ /* Use Maximum PLL Rate(Bits [10:9]) */
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x81 << 16) | (1 << 31) |
+ (pex_line_num << 24)); /* read command */
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0x81 << 16) | (1 << 31) |
+ (pex_line_num << 24));
+ tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
+ DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ tmp &= ~(1 << 31);
+ tmp |= (3 << 9);
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
+ }
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * Port 0 for serdes lines 4,6, and port 1 for serdes
+ * lines 5
+ */
+ sata_port = line_num & 1;
+
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5]) and
+ * REF_FREF_SEL (bits[4:0]) in the register Power
+ * and PLL Control (Each MAC contain different Access
+ * to reach its Serdes-Regfile).
+ */
+ reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
+ DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
+
+ /* 9) Configure the desire SEL_BITS */
+ reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
+ DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
+
+ /* 10) Configure the desire REFCLK_SEL */
+
+ reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
+ DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ tmp |= 7;
+ reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+ DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
+
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5])
+ * and REF_FREF_SEL (bits[4:0]) in the register
+ */
+ reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
+ DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
+
+ /*
+ * 9) Configure the desire SEL_BITS (bits [11:0]
+ * in register
+ */
+ reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
+ DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
+
+ /*
+ * 10) Configure the desire REFCLK_SEL (bit [10])
+ * in register
+ */
+ reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
+ DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ tmp |= 7;
+ reg_write(SGMII_SERDES_CFG_REG(0), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
+ continue;
+ }
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ /*
+ * 8) Configure the desire PHY_MODE (bits [7:5]) and
+ * REF_FREF_SEL (bits[4:0]) in the register
+ */
+ reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
+ DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
+
+ /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
+ reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
+ DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
+
+ /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
+ reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
+ DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
+
+ /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
+ tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ tmp |= 7;
+ reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+ DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
+
+ } /* for each serdes lane */
+
+ /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
+ DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ /* for each serdes lane */
+
+ line_cfg = get_line_cfg(line_num, info);
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ if (0 == pex_line_num) {
+ reg_write(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC1 << 16) | 0x24);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
+ (0xC1 << 16) | 0x24);
+ }
+ }
+ }
+
+ /*--------------------------------------------------------------*/
+ /* Step 13: Wait 15ms before checking results */
+ DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
+ mdelay(15);
+ tmp = 20;
+ while (tmp) {
+ status = MV_OK;
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ u32 tmp;
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+
+ if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
+ /*
+ * Port 0 for serdes lines 4,6, and port 1
+ * for serdes lines 5
+ */
+ sata_port = line_num & 1;
+
+ tmp =
+ reg_read(SATA_LP_PHY_EXT_STAT_REG
+ (sata_port));
+ DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
+ (sata_port), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ continue;
+ }
+
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
+ tmp = reg_read(SGMII_SERDES_STAT_REG(0));
+ DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ continue;
+ }
+
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ continue;
+
+ tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
+ DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
+ if ((tmp & 0x7) != 0x7)
+ status = MV_ERROR;
+ }
+
+ if (status == MV_OK)
+ break;
+ mdelay(5);
+ tmp--;
+ }
+
+ /*
+ * Step14 [PEX-Only] In order to configure RC/EP mode please write
+ * to register 0x0060 bits
+ */
+ DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ tmp =
+ reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
+ DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ tmp &= ~(0xf << 20);
+ if (info->pex_type == MV_PEX_ROOT_COMPLEX)
+ tmp |= (0x4 << 20);
+ else
+ tmp |= (0x1 << 20);
+ reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ }
+
+ /*
+ * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
+ * register 0x1a60
+ */
+ DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
+ continue;
+ if (info->pex_type == MV_PEX_END_POINT) {
+ tmp =
+ reg_read(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)));
+ DEBUG_RD_REG(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
+ tmp &= 0xfff6ffff;
+ reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
+ tmp);
+ DEBUG_WR_REG(PEX_DBG_CTRL_REG
+ (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
+ }
+ }
+
+ if (info->serdes_m_phy_change) {
+ MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
+ u32 bus_speed;
+ for (line_num = 0; line_num < max_serdes_lines; line_num++) {
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg ==
+ serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
+ continue;
+ serdes_m_phy_change = info->serdes_m_phy_change;
+ bus_speed = info->bus_speed & (1 << line_num);
+ while (serdes_m_phy_change->type !=
+ SERDES_UNIT_UNCONNECTED) {
+ switch (serdes_m_phy_change->type) {
+ case SERDES_UNIT_PEX:
+ if (line_cfg != SERDES_UNIT_PEX)
+ break;
+ pex_unit = line_num >> 2;
+ pex_line_num = line_num % 4;
+ if (info->pex_mode[pex_unit] ==
+ PEX_BUS_DISABLED)
+ break;
+ if ((info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4) && pex_line_num)
+ break;
+
+ if (bus_speed) {
+ reg_write(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num << 24) |
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num <<
+ 24) |
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num << 24) |
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(PEX_PHY_ACCESS_REG
+ (pex_unit),
+ (pex_line_num <<
+ 24) |
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_SATA:
+ if (line_cfg != SERDES_UNIT_SATA)
+ break;
+ /*
+ * Port 0 for serdes lines 4,6, and
+ * port 1 for serdes lines 5
+ */
+ sata_port = line_num & 1;
+ if (bus_speed) {
+ reg_write(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(SATA_BASE_REG
+ (sata_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_SGMII0:
+ case SERDES_UNIT_SGMII1:
+ case SERDES_UNIT_SGMII2:
+ case SERDES_UNIT_SGMII3:
+ if (line_cfg == serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII0])
+ sgmii_port = 0;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII1])
+ sgmii_port = 1;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII2])
+ sgmii_port = 2;
+ else if (line_cfg ==
+ serdes_cfg[line_num]
+ [SERDES_UNIT_SGMII3])
+ sgmii_port = 3;
+ else
+ break;
+ if (bus_speed) {
+ reg_write(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG(MV_ETH_REGS_BASE
+ (sgmii_port) |
+ serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ case SERDES_UNIT_QSGMII:
+ if (line_cfg != SERDES_UNIT_QSGMII)
+ break;
+ if (bus_speed) {
+ reg_write
+ (serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ DEBUG_WR_REG
+ (serdes_m_phy_change->reg_hi_speed,
+ serdes_m_phy_change->val_hi_speed);
+ } else {
+ reg_write
+ (serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ DEBUG_WR_REG
+ (serdes_m_phy_change->reg_low_speed,
+ serdes_m_phy_change->val_low_speed);
+ }
+ break;
+ default:
+ break;
+ }
+ serdes_m_phy_change++;
+ }
+ }
+ }
+
+ /* Step 16 [PEX-Only] Training Enable */
+ DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
+ tmp = reg_read(SOC_CTRL_REG);
+ DEBUG_RD_REG(SOC_CTRL_REG, tmp);
+ tmp &= ~(0x0F);
+ for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
+ reg_write(PEX_CAUSE_REG(pex_unit), 0);
+ DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
+ if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
+ tmp |= (0x1 << pex_unit);
+ }
+ reg_write(SOC_CTRL_REG, tmp);
+ DEBUG_WR_REG(SOC_CTRL_REG, tmp);
+
+ /* Step 17: Speed change to target speed and width */
+ {
+ u32 tmp_reg, tmp_pex_reg;
+ u32 addr;
+ u32 first_busno, next_busno;
+ u32 max_link_width = 0;
+ u32 neg_link_width = 0;
+ pex_if_num = pex_max_if_get();
+ mdelay(150);
+ DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
+ next_busno = 0;
+ for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
+ line_num = (pex_if <= 8) ? pex_if : 12;
+ line_cfg = get_line_cfg(line_num, info);
+ if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
+ continue;
+ pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
+ DEBUG_INIT_FULL_S("step 17: PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
+
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
+ DEBUG_INIT_FULL_C("PEX disabled interface ",
+ pex_if, 1);
+ if (pex_if < 8)
+ pex_if += 3;
+ continue;
+ }
+ first_busno = next_busno;
+ if ((info->pex_type == MV_PEX_END_POINT) &&
+ (0 == pex_if)) {
+ if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
+ PEX_BUS_MODE_X4))
+ pex_if += 3;
+ continue;
+ }
+
+ tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
+ DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
+ if ((tmp & 0x7f) == 0x7e) {
+ next_busno++;
+ tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
+ max_link_width = tmp;
+ DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
+ (pex_if)), tmp);
+ max_link_width = ((max_link_width >> 4) & 0x3F);
+ neg_link_width =
+ reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
+ DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
+ neg_link_width);
+ neg_link_width = ((neg_link_width >> 20) & 0x3F);
+ if (max_link_width > neg_link_width) {
+ tmp &= ~(0x3F << 4);
+ tmp |= (neg_link_width << 4);
+ reg_write(PEX_LINK_CAPABILITIES_REG
+ (pex_if), tmp);
+ DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
+ (pex_if)), tmp);
+ mdelay(1); /* wait 1ms before reading capability for speed */
+ DEBUG_INIT_S("PEX");
+ DEBUG_INIT_D(pex_if, 1);
+ DEBUG_INIT_C(": change width to X",
+ neg_link_width, 1);
+ }
+ tmp_pex_reg =
+ reg_read((PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CAPABILITY_REG)));
+ DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CAPABILITY_REG)),
+ tmp_pex_reg);
+ tmp_pex_reg &= (0xF);
+ if (tmp_pex_reg == 0x2) {
+ tmp_reg =
+ (reg_read
+ (PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CTRL_STAT_REG)) &
+ 0xF0000) >> 16;
+ DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
+ (pex_if,
+ PEX_LINK_CTRL_STAT_REG),
+ tmp_pex_reg);
+ /* check if the link established is GEN1 */
+ if (tmp_reg == 0x1) {
+ pex_local_bus_num_set(pex_if,
+ first_busno);
+ pex_local_dev_num_set(pex_if,
+ 1);
+
+ DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
+ /* link is Gen1, check the EP capability */
+ addr =
+ pex_cfg_read(pex_if,
+ first_busno, 0,
+ 0,
+ 0x34) & 0xFF;
+ DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
+ addr, 4);
+ if (addr == 0xff) {
+ DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
+ pex_if, 1);
+ continue;
+ }
+ while ((pex_cfg_read
+ (pex_if, first_busno, 0,
+ 0,
+ addr) & 0xFF) !=
+ 0x10) {
+ addr =
+ (pex_cfg_read
+ (pex_if,
+ first_busno, 0, 0,
+ addr) & 0xFF00) >>
+ 8;
+ }
+ if ((pex_cfg_read
+ (pex_if, first_busno, 0, 0,
+ addr + 0xC) & 0xF) >=
+ 0x2) {
+ tmp =
+ reg_read
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if));
+ DEBUG_RD_REG
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+ tmp &= ~(0x1 | 1 << 1);
+ tmp |= (1 << 1);
+ reg_write
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+ DEBUG_WR_REG
+ (PEX_LINK_CTRL_STATUS2_REG
+ (pex_if), tmp);
+
+ tmp =
+ reg_read
+ (PEX_CTRL_REG
+ (pex_if));
+ DEBUG_RD_REG
+ (PEX_CTRL_REG
+ (pex_if), tmp);
+ tmp |= (1 << 10);
+ reg_write(PEX_CTRL_REG
+ (pex_if),
+ tmp);
+ DEBUG_WR_REG
+ (PEX_CTRL_REG
+ (pex_if), tmp);
+ mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
+ DEBUG_INIT_FULL_S
+ ("Gen2 client!\n");
+ } else {
+ DEBUG_INIT_FULL_S
+ ("GEN1 client!\n");
+ }
+ }
+ }
+ } else {
+ DEBUG_INIT_FULL_S("PEX");
+ DEBUG_INIT_FULL_D(pex_if, 1);
+ DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
+ DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
+ 8);
+ DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
+ }
+
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ }
+ }
+
+ /* Step 18: update pex DEVICE ID */
+ {
+ u32 devId;
+ pex_if_num = pex_max_if_get();
+ ctrl_mode = ctrl_model_get();
+ for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
+ pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
+ if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ continue;
+ }
+
+ devId = reg_read(PEX_CFG_DIRECT_ACCESS(
+ pex_if, PEX_DEVICE_AND_VENDOR_ID));
+ devId &= 0xFFFF;
+ devId |= ((ctrl_mode << 16) & 0xffff0000);
+ DEBUG_INIT_S("Update Device ID PEX");
+ DEBUG_INIT_D(pex_if, 1);
+ DEBUG_INIT_D(devId, 8);
+ DEBUG_INIT_S("\n");
+ reg_write(PEX_CFG_DIRECT_ACCESS
+ (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
+ if ((pex_if < 8) &&
+ (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
+ pex_if += 3;
+ }
+ DEBUG_INIT_S("Update PEX Device ID 0x");
+ DEBUG_INIT_D(ctrl_mode, 4);
+ DEBUG_INIT_S("0\n");
+ }
+ tmp = reg_read(PEX_DBG_STATUS_REG(0));
+ DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
+
+ DEBUG_INIT_S(ENDED_OK);
+ return MV_OK;
+}
+
+/* PEX configuration space read write */
+
+/*
+ * pex_cfg_read - Read from configuration space
+ *
+ * DESCRIPTION:
+ * This function performs a 32 bit read from PEX configuration space.
+ * It supports both type 0 and type 1 of Configuration Transactions
+ * (local and over bridge). In order to read from local bus segment, use
+ * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
+ * will result configuration transaction of type 1 (over bridge).
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * bus - PEX segment bus number.
+ * dev - PEX device number.
+ * func - Function number.
+ * offss - Register offset.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * 32bit register data, 0xffffffff on error
+ *
+ */
+u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
+{
+ u32 pex_data = 0;
+ u32 local_dev, local_bus;
+ u32 val;
+
+ if (pex_if >= MV_PEX_MAX_IF)
+ return 0xFFFFFFFF;
+
+ if (dev >= MAX_PEX_DEVICES) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
+ 1);
+ return 0xFFFFFFFF;
+ }
+
+ if (func >= MAX_PEX_FUNCS) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
+ 1);
+ return 0xFFFFFFFF;
+ }
+
+ if (bus >= MAX_PEX_BUSSES) {
+ DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
+ return MV_ERROR;
+ }
+ val = reg_read(PEX_STATUS_REG(pex_if));
+
+ local_dev =
+ ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
+ local_bus =
+ ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
+
+ /* Speed up the process. In case on no link, return MV_ERROR */
+ if ((dev != local_dev) || (bus != local_bus)) {
+ pex_data = reg_read(PEX_STATUS_REG(pex_if));
+
+ if ((pex_data & PXSR_DL_DOWN))
+ return MV_ERROR;
+ }
+
+ /*
+ * In PCI Express we have only one device number
+ * and this number is the first number we encounter else that the
+ * local_dev spec pex define return on config read/write on any device
+ */
+ if (bus == local_bus) {
+ if (local_dev == 0) {
+ /*
+ * If local dev is 0 then the first number we encounter
+ * after 0 is 1
+ */
+ if ((dev != 1) && (dev != local_dev))
+ return MV_ERROR;
+ } else {
+ /*
+ * If local dev is not 0 then the first number we
+ * encounter is 0
+ */
+ if ((dev != 0) && (dev != local_dev))
+ return MV_ERROR;
+ }
+ }
+
+ /* Creating PEX address to be passed */
+ pex_data = (bus << PXCAR_BUS_NUM_OFFS);
+ pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
+ pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
+ pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
+ /* extended register space */
+ pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
+ PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
+
+ pex_data |= PXCAR_CONFIG_EN;
+
+ /* Write the address to the PEX configuration address register */
+ reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
+
+ /*
+ * In order to let the PEX controller absorbed the address of the read
+ * transaction we perform a validity check that the address was written
+ */
+ if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
+ return MV_ERROR;
+
+ /* cleaning Master Abort */
+ reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
+ PXSAC_MABORT);
+ /* Read the Data returned in the PEX Data register */
+ pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
+
+ DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
+
+ return pex_data;
+}
+
+/*
+ * pex_local_bus_num_set - Set PEX interface local bus number.
+ *
+ * DESCRIPTION:
+ * This function sets given PEX interface its local bus number.
+ * Note: In case the PEX interface is PEX-X, the information is read-only.
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * bus_num - Bus number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * MV_NOT_ALLOWED in case PEX interface is PEX-X.
+ * MV_BAD_PARAM on bad parameters ,
+ * otherwise MV_OK
+ *
+ */
+int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
+{
+ u32 val;
+
+ if (bus_num >= MAX_PEX_BUSSES) {
+ DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
+ bus_num, 4);
+ return MV_ERROR;
+ }
+
+ val = reg_read(PEX_STATUS_REG(pex_if));
+ val &= ~PXSR_PEX_BUS_NUM_MASK;
+ val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
+ reg_write(PEX_STATUS_REG(pex_if), val);
+
+ return MV_OK;
+}
+
+/*
+ * pex_local_dev_num_set - Set PEX interface local device number.
+ *
+ * DESCRIPTION:
+ * This function sets given PEX interface its local device number.
+ * Note: In case the PEX interface is PEX-X, the information is read-only.
+ *
+ * INPUT:
+ * pex_if - PEX interface number.
+ * dev_num - Device number.
+ *
+ * OUTPUT:
+ * None.
+ *
+ * RETURN:
+ * MV_NOT_ALLOWED in case PEX interface is PEX-X.
+ * MV_BAD_PARAM on bad parameters ,
+ * otherwise MV_OK
+ *
+ */
+int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
+{
+ u32 val;
+
+ if (pex_if >= MV_PEX_MAX_IF)
+ return MV_BAD_PARAM;
+
+ val = reg_read(PEX_STATUS_REG(pex_if));
+ val &= ~PXSR_PEX_DEV_NUM_MASK;
+ val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
+ reg_write(PEX_STATUS_REG(pex_if), val);
+
+ return MV_OK;
+}
--- /dev/null
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#include "high_speed_env_spec.h"
+
+MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
+ /* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
+ {
+ /* PEX: Change of Slew Rate port0 */
+ SERDES_UNIT_PEX, 0x0,
+ (0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
+ }, {
+ /* PEX: Change PLL BW port0 */
+ SERDES_UNIT_PEX, 0x0,
+ (0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
+ }, {
+ /* SATA: Slew rate change port 0 */
+ SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
+ }, {
+ /* SGMII: FFE setting Port0 */
+ SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
+ }, {
+ /* SGMII: SELMUP and SELMUF Port0 */
+ SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
+ }, {
+ /* SGMII: Amplitude new setting gen2 Port3 */
+ SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
+ }, {
+ /* QSGMII: Amplitude and slew rate change */
+ SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
+ }, {
+ /* QSGMII: SELMUP and SELMUF */
+ SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
+ }, {
+ /* QSGMII: 0x72e18 */
+ SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
+ }, {
+ /* Null terminated */
+ SERDES_UNIT_UNCONNECTED, 0, 0
+ }
+};
+
+MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
+ /* Z1B */
+ {MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* PEX module */
+ /* Z1A */
+ {MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
+ PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
+ {MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0030, serdes_change_m_phy} /* PEX module - Z1A */
+};
+
+MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
+ /* A0 */
+ {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
+ {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
+ {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
+ {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
+ {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
+ {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
+};
+
+MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00f4, serdes_change_m_phy}, /* Switch module */
+};
+
+MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy}, /* CPU0 */
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* CPU1-3 */
+};
+
+MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy}, /* CPU0 */
+ {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* CPU1-3 */
+};
+
+MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
+ {MV_PEX_END_POINT, 0x22321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
+ {MV_PEX_END_POINT, 0x23321111, 0x00000000,
+ {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0010, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
+ {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
+ 0x0000, serdes_change_m_phy} /* No PEX in FPGA */
+};
+
+MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
+ {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
+ 0x0030, serdes_change_m_phy} /* Default */
+};
+
+/*
+ * ARMADA-XP CUSTOMER BOARD
+ */
+MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00000030, serdes_change_m_phy}, /* Default */
+ {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x00000030, serdes_change_m_phy}, /* Switch module */
+};
+
+MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
+ {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
+ {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
+ 0x0030, serdes_change_m_phy} /* Default */
+};
+
+MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
+ db88f78xx0_serdes_cfg,
+ rd78460_serdes_cfg,
+ db78X60pcac_serdes_cfg,
+ fpga88f78xx0_serdes_cfg,
+ db88f78xx0rev2_serdes_cfg,
+ rd78460nas_serdes_cfg,
+ db78X60amc_serdes_cfg,
+ db78X60pcacrev2_serdes_cfg,
+ rd78460server_rev2_serdes_cfg,
+ rd78460AXP_GP_serdes_cfg,
+ rd78460customer_serdes_cfg
+};
+
+u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
+u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
--- /dev/null
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __HIGHSPEED_ENV_SPEC_H
+#define __HIGHSPEED_ENV_SPEC_H
+
+#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
+
+typedef enum {
+ SERDES_UNIT_UNCONNECTED = 0x0,
+ SERDES_UNIT_PEX = 0x1,
+ SERDES_UNIT_SATA = 0x2,
+ SERDES_UNIT_SGMII0 = 0x3,
+ SERDES_UNIT_SGMII1 = 0x4,
+ SERDES_UNIT_SGMII2 = 0x5,
+ SERDES_UNIT_SGMII3 = 0x6,
+ SERDES_UNIT_QSGMII = 0x7,
+ SERDES_UNIT_SETM = 0x8,
+ SERDES_LAST_UNIT
+} MV_BIN_SERDES_UNIT_INDX;
+
+
+typedef enum {
+ PEX_BUS_DISABLED = 0,
+ PEX_BUS_MODE_X1 = 1,
+ PEX_BUS_MODE_X4 = 2,
+ PEX_BUS_MODE_X8 = 3
+} MV_PEX_UNIT_CFG;
+
+typedef enum pex_type {
+ MV_PEX_ROOT_COMPLEX, /* root complex device */
+ MV_PEX_END_POINT /* end point device */
+} MV_PEX_TYPE;
+
+typedef struct serdes_change_m_phy {
+ MV_BIN_SERDES_UNIT_INDX type;
+ u32 reg_low_speed;
+ u32 val_low_speed;
+ u32 reg_hi_speed;
+ u32 val_hi_speed;
+} MV_SERDES_CHANGE_M_PHY;
+
+/*
+ * Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
+ */
+typedef struct board_serdes_conf {
+ MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
+ u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
+ u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
+ MV_PEX_UNIT_CFG pex_mode[4];
+
+ /*
+ * Bus speed - one bit per SERDES line:
+ * Low speed (0) High speed (1)
+ * PEX 2.5 G (10 bit) 5 G (20 bit)
+ * SATA 1.5 G 3 G
+ * SGMII 1.25 Gbps 3.125 Gbps
+ */
+ u32 bus_speed;
+
+ MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
+} MV_BIN_SERDES_CFG;
+
+
+#define BIN_SERDES_CFG { \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
+ {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
+ {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
+ {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
+ {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
+ {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
+ {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */ \
+ {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */ \
+}
+
+#endif /* __HIGHSPEED_ENV_SPEC_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ /* Right now only booting via SPI NOR flash is supported */
+ return BOOT_DEVICE_SPI;
+}
+
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ arch_cpu_init();
+
+ preloader_console_init();
+
+ /* First init the serdes PHY's */
+ serdes_phy_config();
+
+ /* Setup DDR */
+ ddr3_init();
+
+ board_init_r(NULL, 0);
+}
--- /dev/null
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/soc.h>
+
+#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG &tmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
+#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
+#if defined(CONFIG_ARMADA_XP)
+#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
+#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
+#else
+#define CTCR_ARM_TIMER_25MHZ(cntr) 0
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
+
+/* Timer reload and current value registers */
+struct kwtmr_val {
+ u32 reload; /* Timer reload reg */
+ u32 val; /* Timer value reg */
+};
+
+/* Timer registers */
+struct kwtmr_registers {
+ u32 ctrl; /* Timer control reg */
+ u32 pad[3];
+ struct kwtmr_val tmr[4];
+ u32 wdt_reload;
+ u32 wdt_val;
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct kwtmr_registers *tmr_regs =
+ (struct kwtmr_registers *)MVEBU_TIMER_BASE;
+
+static inline ulong read_timer(void)
+{
+ return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
+}
+
+ulong get_timer_masked(void)
+{
+ ulong now = read_timer();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec +
+ (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ uint current;
+ ulong delayticks;
+
+ current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+ delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+ if (current < delayticks) {
+ delayticks -= current;
+ while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
+ while ((TIMER_LOAD_VAL - delayticks) <
+ readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
+ } else {
+ while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+ (current - delayticks)) ;
+ }
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+ /* load value into timer */
+ writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+ writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+ /* enable timer in auto reload mode */
+ clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
+ CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
+ CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
+
+ /* init the timestamp and lastdec value */
+ lastdec = read_timer();
+ timestamp = 0;
+
+ return 0;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+ return (ulong)CONFIG_SYS_HZ;
+}
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text*)
+ *(.text*)
+ *(.vectors)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*_i2c_*)));
+ } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .end :
+ {
+ *(.__end)
+ }
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end = .;
+ } >.sdram
+}
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct sdram_bank {
- u32 win_bar;
- u32 win_sz;
-};
-
-struct sdram_addr_dec {
- struct sdram_bank sdram_bank[4];
-};
-
-#define REG_CPUCS_WIN_ENABLE (1 << 0)
-#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
-#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
-#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
-
-/*
- * mvebu_sdram_bar - reads SDRAM Base Address Register
- */
-u32 mvebu_sdram_bar(enum memory_bank bank)
-{
- struct sdram_addr_dec *base =
- (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
- u32 result = 0;
- u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
-
- if ((!enable) || (bank > BANK3))
- return 0;
-
- result = readl(&base->sdram_bank[bank].win_bar);
- return result;
-}
-
-/*
- * mvebu_sdram_bs_set - writes SDRAM Bank size
- */
-static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
-{
- struct sdram_addr_dec *base =
- (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
- /* Read current register value */
- u32 reg = readl(&base->sdram_bank[bank].win_sz);
-
- /* Clear window size */
- reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
-
- /* Set new window size */
- reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
-
- writel(reg, &base->sdram_bank[bank].win_sz);
-}
-
-/*
- * mvebu_sdram_bs - reads SDRAM Bank size
- */
-u32 mvebu_sdram_bs(enum memory_bank bank)
-{
- struct sdram_addr_dec *base =
- (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
- u32 result = 0;
- u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
-
- if ((!enable) || (bank > BANK3))
- return 0;
- result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
- result += 0x01000000;
- return result;
-}
-
-void mvebu_sdram_size_adjust(enum memory_bank bank)
-{
- u32 size;
-
- /* probe currently equipped RAM size */
- size = get_ram_size((void *)mvebu_sdram_bar(bank),
- mvebu_sdram_bs(bank));
-
- /* adjust SDRAM window size accordingly */
- mvebu_sdram_bs_set(bank, size);
-}
-
-#ifndef CONFIG_SYS_BOARD_DRAM_INIT
-int dram_init(void)
-{
- int i;
-
- gd->ram_size = 0;
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
- gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
- /*
- * It is assumed that all memory banks are consecutive
- * and without gaps.
- * If the gap is found, ram_size will be reported for
- * consecutive memory only
- */
- if (gd->bd->bi_dram[i].start != gd->ram_size)
- break;
-
- /*
- * Don't report more than 3GiB of SDRAM, otherwise there is no
- * address space left for the internal registers etc.
- */
- if ((gd->ram_size + gd->bd->bi_dram[i].size != 0) &&
- (gd->ram_size + gd->bd->bi_dram[i].size <= (3 << 30)))
- gd->ram_size += gd->bd->bi_dram[i].size;
-
- }
-
- for (; i < CONFIG_NR_DRAM_BANKS; i++) {
- /* If above loop terminated prematurely, we need to set
- * remaining banks' start address & size as 0. Otherwise other
- * u-boot functions and Linux kernel gets wrong values which
- * could result in crash */
- gd->bd->bi_dram[i].start = 0;
- gd->bd->bi_dram[i].size = 0;
- }
-
- return 0;
-}
-
-/*
- * If this function is not defined here,
- * board.c alters dram bank zero configuration defined above.
- */
-void dram_init_banksize(void)
-{
- dram_init();
-}
-#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-/*
- * mvebu_config_gpio - GPIO configuration
- */
-void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
- u32 gpp0_oe, u32 gpp1_oe)
-{
- struct kwgpio_registers *gpio0reg =
- (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
- struct kwgpio_registers *gpio1reg =
- (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
-
- /* Init GPIOS to default values as per board requirement */
- writel(gpp0_oe_val, &gpio0reg->dout);
- writel(gpp1_oe_val, &gpio1reg->dout);
- writel(gpp0_oe, &gpio0reg->oe);
- writel(gpp1_oe, &gpio1reg->oe);
-}
+++ /dev/null
-/*
- * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
- * 370/XP, Dove, Orion5x and MV78xx0)
- *
- * Ported from the Barebox version to U-Boot by:
- * Stefan Roese <sr@denx.de>
- *
- * The Barebox version is:
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * based on mbus driver from Linux
- * (C) Copyright 2008 Marvell Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0
- *
- * The Marvell EBU SoCs have a configurable physical address space:
- * the physical address at which certain devices (PCIe, NOR, NAND,
- * etc.) sit can be configured. The configuration takes place through
- * two sets of registers:
- *
- * - One to configure the access of the CPU to the devices. Depending
- * on the families, there are between 8 and 20 configurable windows,
- * each can be use to create a physical memory window that maps to a
- * specific device. Devices are identified by a tuple (target,
- * attribute).
- *
- * - One to configure the access to the CPU to the SDRAM. There are
- * either 2 (for Dove) or 4 (for other families) windows to map the
- * SDRAM into the physical address space.
- *
- * This driver:
- *
- * - Reads out the SDRAM address decoding windows at initialization
- * time, and fills the mbus_dram_info structure with these
- * informations. The exported function mv_mbus_dram_info() allow
- * device drivers to get those informations related to the SDRAM
- * address decoding windows. This is because devices also have their
- * own windows (configured through registers that are part of each
- * device register space), and therefore the drivers for Marvell
- * devices have to configure those device -> SDRAM windows to ensure
- * that DMA works properly.
- *
- * - Provides an API for platform code or device drivers to
- * dynamically add or remove address decoding windows for the CPU ->
- * device accesses. This API is mvebu_mbus_add_window_by_id(),
- * mvebu_mbus_add_window_remap_by_id() and
- * mvebu_mbus_del_window().
- */
-
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-#include <linux/mbus.h>
-
-#define BIT(nr) (1UL << (nr))
-
-/* DDR target is the same on all platforms */
-#define TARGET_DDR 0
-
-/* CPU Address Decode Windows registers */
-#define WIN_CTRL_OFF 0x0000
-#define WIN_CTRL_ENABLE BIT(0)
-#define WIN_CTRL_TGT_MASK 0xf0
-#define WIN_CTRL_TGT_SHIFT 4
-#define WIN_CTRL_ATTR_MASK 0xff00
-#define WIN_CTRL_ATTR_SHIFT 8
-#define WIN_CTRL_SIZE_MASK 0xffff0000
-#define WIN_CTRL_SIZE_SHIFT 16
-#define WIN_BASE_OFF 0x0004
-#define WIN_BASE_LOW 0xffff0000
-#define WIN_BASE_HIGH 0xf
-#define WIN_REMAP_LO_OFF 0x0008
-#define WIN_REMAP_LOW 0xffff0000
-#define WIN_REMAP_HI_OFF 0x000c
-
-#define ATTR_HW_COHERENCY (0x1 << 4)
-
-#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
-#define DDR_BASE_CS_HIGH_MASK 0xf
-#define DDR_BASE_CS_LOW_MASK 0xff000000
-#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
-#define DDR_SIZE_ENABLED BIT(0)
-#define DDR_SIZE_CS_MASK 0x1c
-#define DDR_SIZE_CS_SHIFT 2
-#define DDR_SIZE_MASK 0xff000000
-
-#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
-
-struct mvebu_mbus_state;
-
-struct mvebu_mbus_soc_data {
- unsigned int num_wins;
- unsigned int num_remappable_wins;
- unsigned int (*win_cfg_offset)(const int win);
- void (*setup_cpu_target)(struct mvebu_mbus_state *s);
-};
-
-struct mvebu_mbus_state mbus_state
- __attribute__ ((section(".data")));
-static struct mbus_dram_target_info mbus_dram_info
- __attribute__ ((section(".data")));
-
-/*
- * Functions to manipulate the address decoding windows
- */
-
-static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
- int win, int *enabled, u64 *base,
- u32 *size, u8 *target, u8 *attr,
- u64 *remap)
-{
- void __iomem *addr = mbus->mbuswins_base +
- mbus->soc->win_cfg_offset(win);
- u32 basereg = readl(addr + WIN_BASE_OFF);
- u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
-
- if (!(ctrlreg & WIN_CTRL_ENABLE)) {
- *enabled = 0;
- return;
- }
-
- *enabled = 1;
- *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
- *base |= (basereg & WIN_BASE_LOW);
- *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
-
- if (target)
- *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
-
- if (attr)
- *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
-
- if (remap) {
- if (win < mbus->soc->num_remappable_wins) {
- u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
- u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
- *remap = ((u64)remap_hi << 32) | remap_low;
- } else {
- *remap = 0;
- }
- }
-}
-
-static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
- int win)
-{
- void __iomem *addr;
-
- addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
-
- writel(0, addr + WIN_BASE_OFF);
- writel(0, addr + WIN_CTRL_OFF);
- if (win < mbus->soc->num_remappable_wins) {
- writel(0, addr + WIN_REMAP_LO_OFF);
- writel(0, addr + WIN_REMAP_HI_OFF);
- }
-}
-
-/* Checks whether the given window number is available */
-static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
- const int win)
-{
- void __iomem *addr = mbus->mbuswins_base +
- mbus->soc->win_cfg_offset(win);
- u32 ctrl = readl(addr + WIN_CTRL_OFF);
- return !(ctrl & WIN_CTRL_ENABLE);
-}
-
-/*
- * Checks whether the given (base, base+size) area doesn't overlap an
- * existing region
- */
-static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
- phys_addr_t base, size_t size,
- u8 target, u8 attr)
-{
- u64 end = (u64)base + size;
- int win;
-
- for (win = 0; win < mbus->soc->num_wins; win++) {
- u64 wbase, wend;
- u32 wsize;
- u8 wtarget, wattr;
- int enabled;
-
- mvebu_mbus_read_window(mbus, win,
- &enabled, &wbase, &wsize,
- &wtarget, &wattr, NULL);
-
- if (!enabled)
- continue;
-
- wend = wbase + wsize;
-
- /*
- * Check if the current window overlaps with the
- * proposed physical range
- */
- if ((u64)base < wend && end > wbase)
- return 0;
-
- /*
- * Check if target/attribute conflicts
- */
- if (target == wtarget && attr == wattr)
- return 0;
- }
-
- return 1;
-}
-
-static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
- phys_addr_t base, size_t size)
-{
- int win;
-
- for (win = 0; win < mbus->soc->num_wins; win++) {
- u64 wbase;
- u32 wsize;
- int enabled;
-
- mvebu_mbus_read_window(mbus, win,
- &enabled, &wbase, &wsize,
- NULL, NULL, NULL);
-
- if (!enabled)
- continue;
-
- if (base == wbase && size == wsize)
- return win;
- }
-
- return -ENODEV;
-}
-
-static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
- int win, phys_addr_t base, size_t size,
- phys_addr_t remap, u8 target,
- u8 attr)
-{
- void __iomem *addr = mbus->mbuswins_base +
- mbus->soc->win_cfg_offset(win);
- u32 ctrl, remap_addr;
-
- ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
- (attr << WIN_CTRL_ATTR_SHIFT) |
- (target << WIN_CTRL_TGT_SHIFT) |
- WIN_CTRL_ENABLE;
-
- writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
- writel(ctrl, addr + WIN_CTRL_OFF);
- if (win < mbus->soc->num_remappable_wins) {
- if (remap == MVEBU_MBUS_NO_REMAP)
- remap_addr = base;
- else
- remap_addr = remap;
- writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
- writel(0, addr + WIN_REMAP_HI_OFF);
- }
-
- return 0;
-}
-
-static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
- phys_addr_t base, size_t size,
- phys_addr_t remap, u8 target,
- u8 attr)
-{
- int win;
-
- if (remap == MVEBU_MBUS_NO_REMAP) {
- for (win = mbus->soc->num_remappable_wins;
- win < mbus->soc->num_wins; win++)
- if (mvebu_mbus_window_is_free(mbus, win))
- return mvebu_mbus_setup_window(mbus, win, base,
- size, remap,
- target, attr);
- }
-
-
- for (win = 0; win < mbus->soc->num_wins; win++)
- if (mvebu_mbus_window_is_free(mbus, win))
- return mvebu_mbus_setup_window(mbus, win, base, size,
- remap, target, attr);
-
- return -ENOMEM;
-}
-
-/*
- * SoC-specific functions and definitions
- */
-
-static unsigned int armada_370_xp_mbus_win_offset(int win)
-{
- /* The register layout is a bit annoying and the below code
- * tries to cope with it.
- * - At offset 0x0, there are the registers for the first 8
- * windows, with 4 registers of 32 bits per window (ctrl,
- * base, remap low, remap high)
- * - Then at offset 0x80, there is a hole of 0x10 bytes for
- * the internal registers base address and internal units
- * sync barrier register.
- * - Then at offset 0x90, there the registers for 12
- * windows, with only 2 registers of 32 bits per window
- * (ctrl, base).
- */
- if (win < 8)
- return win << 4;
- else
- return 0x90 + ((win - 8) << 3);
-}
-
-static unsigned int orion5x_mbus_win_offset(int win)
-{
- return win << 4;
-}
-
-static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
-{
- int i;
- int cs;
-
- mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
- for (i = 0, cs = 0; i < 4; i++) {
- u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
- u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
-
- /*
- * We only take care of entries for which the chip
- * select is enabled, and that don't have high base
- * address bits set (devices can only access the first
- * 32 bits of the memory).
- */
- if ((size & DDR_SIZE_ENABLED) &&
- !(base & DDR_BASE_CS_HIGH_MASK)) {
- struct mbus_dram_window *w;
-
- w = &mbus_dram_info.cs[cs++];
- w->cs_index = i;
- w->mbus_attr = 0xf & ~(1 << i);
-#if defined(CONFIG_ARMADA_XP)
- w->mbus_attr |= ATTR_HW_COHERENCY;
-#endif
- w->base = base & DDR_BASE_CS_LOW_MASK;
- w->size = (size | ~DDR_SIZE_MASK) + 1;
- }
- }
- mbus_dram_info.num_cs = cs;
-}
-
-static const struct mvebu_mbus_soc_data
-armada_370_xp_mbus_data __maybe_unused = {
- .num_wins = 20,
- .num_remappable_wins = 8,
- .win_cfg_offset = armada_370_xp_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
-};
-
-static const struct mvebu_mbus_soc_data
-kirkwood_mbus_data __maybe_unused = {
- .num_wins = 8,
- .num_remappable_wins = 4,
- .win_cfg_offset = orion5x_mbus_win_offset,
- .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
-};
-
-/*
- * Public API of the driver
- */
-const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
-{
- return &mbus_dram_info;
-}
-
-int mvebu_mbus_add_window_remap_by_id(unsigned int target,
- unsigned int attribute,
- phys_addr_t base, size_t size,
- phys_addr_t remap)
-{
- struct mvebu_mbus_state *s = &mbus_state;
-
- if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
- printf("Cannot add window '%x:%x', conflicts with another window\n",
- target, attribute);
- return -EINVAL;
- }
-
- return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
-}
-
-int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
- phys_addr_t base, size_t size)
-{
- return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
- size, MVEBU_MBUS_NO_REMAP);
-}
-
-int mvebu_mbus_del_window(phys_addr_t base, size_t size)
-{
- int win;
-
- win = mvebu_mbus_find_window(&mbus_state, base, size);
- if (win < 0)
- return win;
-
- mvebu_mbus_disable_window(&mbus_state, win);
- return 0;
-}
-
-int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
- u32 base, u32 size, u8 target, u8 attr)
-{
- if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
- printf("Cannot add window '%04x:%04x', conflicts with another window\n",
- target, attr);
- return -EBUSY;
- }
-
- /*
- * In U-Boot we first try to add the mbus window to the remap windows.
- * If this fails, lets try to add the windows to the non-remap windows.
- */
- if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
- if (mvebu_mbus_alloc_window(mbus, base, size,
- MVEBU_MBUS_NO_REMAP, target, attr))
- return -ENOMEM;
- }
-
- return 0;
-}
-
-int mvebu_mbus_probe(struct mbus_win windows[], int count)
-{
- int win;
- int ret;
- int i;
-
-#if defined(CONFIG_KIRKWOOD)
- mbus_state.soc = &kirkwood_mbus_data;
-#endif
-#if defined(CONFIG_ARMADA_XP)
- mbus_state.soc = &armada_370_xp_mbus_data;
-#endif
-
- mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
- mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
-
- for (win = 0; win < mbus_state.soc->num_wins; win++)
- mvebu_mbus_disable_window(&mbus_state, win);
-
- mbus_state.soc->setup_cpu_target(&mbus_state);
-
- /* Setup statically declared windows in the DT */
- for (i = 0; i < count; i++) {
- u32 base, size;
- u8 target, attr;
-
- target = windows[i].target;
- attr = windows[i].attr;
- base = windows[i].base;
- size = windows[i].size;
- ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);
- if (ret < 0)
- return ret;
- }
-
- return 0;
-}
+++ /dev/null
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o
-obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
+++ /dev/null
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __BOARD_ENV_SPEC
-#define __BOARD_ENV_SPEC
-
-/* Board specific configuration */
-
-/* KW40 */
-#define MV_6710_DEV_ID 0x6710
-
-#define MV_6710_Z1_REV 0x0
-#define MV_6710_Z1_ID ((MV_6710_DEV_ID << 16) | MV_6710_Z1_REV)
-#define MV_6710_Z1_NAME "MV6710 Z1"
-
-/* Armada XP Family */
-#define MV_78130_DEV_ID 0x7813
-#define MV_78160_DEV_ID 0x7816
-#define MV_78230_DEV_ID 0x7823
-#define MV_78260_DEV_ID 0x7826
-#define MV_78460_DEV_ID 0x7846
-#define MV_78000_DEV_ID 0x7888
-
-#define MV_FPGA_DEV_ID 0x2107
-
-#define MV_78XX0_Z1_REV 0x0
-
-/* boards ID numbers */
-#define BOARD_ID_BASE 0x0
-
-/* New board ID numbers */
-#define DB_88F78XX0_BP_ID (BOARD_ID_BASE)
-#define RD_78460_SERVER_ID (DB_88F78XX0_BP_ID + 1)
-#define DB_78X60_PCAC_ID (RD_78460_SERVER_ID + 1)
-#define FPGA_88F78XX0_ID (DB_78X60_PCAC_ID + 1)
-#define DB_88F78XX0_BP_REV2_ID (FPGA_88F78XX0_ID + 1)
-#define RD_78460_NAS_ID (DB_88F78XX0_BP_REV2_ID + 1)
-#define DB_78X60_AMC_ID (RD_78460_NAS_ID + 1)
-#define DB_78X60_PCAC_REV2_ID (DB_78X60_AMC_ID + 1)
-#define RD_78460_SERVER_REV2_ID (DB_78X60_PCAC_REV2_ID + 1)
-#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
-#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
-#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
-#define INVALID_BAORD_ID 0xFFFFFFFF
-
-/* Sample at Reset */
-#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
-
-/* BIOS Modes related defines */
-
-#define SAR0_BOOTWIDTH_OFFSET 3
-#define SAR0_BOOTWIDTH_MASK (0x3 << SAR0_BOOTWIDTH_OFFSET)
-#define SAR0_BOOTSRC_OFFSET 5
-#define SAR0_BOOTSRC_MASK (0xF << SAR0_BOOTSRC_OFFSET)
-
-#define SAR0_L2_SIZE_OFFSET 19
-#define SAR0_L2_SIZE_MASK (0x3 << SAR0_L2_SIZE_OFFSET)
-#define SAR0_CPU_FREQ_OFFSET 21
-#define SAR0_CPU_FREQ_MASK (0x7 << SAR0_CPU_FREQ_OFFSET)
-#define SAR0_FABRIC_FREQ_OFFSET 24
-#define SAR0_FABRIC_FREQ_MASK (0xF << SAR0_FABRIC_FREQ_OFFSET)
-#define SAR0_CPU0CORE_OFFSET 31
-#define SAR0_CPU0CORE_MASK (0x1 << SAR0_CPU0CORE_OFFSET)
-#define SAR1_CPU0CORE_OFFSET 0
-#define SAR1_CPU0CORE_MASK (0x1 << SAR1_CPU0CORE_OFFSET)
-
-#define PEX_CLK_100MHZ_OFFSET 2
-#define PEX_CLK_100MHZ_MASK (0x1 << PEX_CLK_100MHZ_OFFSET)
-
-#define SAR1_FABRIC_MODE_OFFSET 19
-#define SAR1_FABRIC_MODE_MASK (0x1 << SAR1_FABRIC_MODE_OFFSET)
-#define SAR1_CPU_MODE_OFFSET 20
-#define SAR1_CPU_MODE_MASK (0x1 << SAR1_CPU_MODE_OFFSET)
-
-#define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
-
-
-#define CORE_AVS_CONTROL_0REG 0x18300
-#define CORE_AVS_CONTROL_2REG 0x18308
-#define CPU_AVS_CONTROL2_REG 0x20868
-#define CPU_AVS_CONTROL0_REG 0x20860
-#define GENERAL_PURPOSE_RESERVED0_REG 0x182E0
-
-#define MSAR_TCLK_OFFS 28
-#define MSAR_TCLK_MASK (0x1 << MSAR_TCLK_OFFS)
-
-
-/* Controler environment registers offsets */
-#define GEN_PURP_RES_1_REG 0x182F4
-#define GEN_PURP_RES_2_REG 0x182F8
-
-/* registers offsets */
-#define MV_GPP_REGS_OFFSET(unit) (0x18100 + ((unit) * 0x40))
-#define MPP_CONTROL_REG(id) (0x18000 + (id * 4))
-#define MV_GPP_REGS_BASE(unit) (MV_GPP_REGS_OFFSET(unit))
-#define MV_GPP_REGS_BASE_0 (MV_GPP_REGS_OFFSET_0)
-
-#define GPP_DATA_OUT_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x00)
-#define GPP_DATA_OUT_REG_0 (MV_GPP_REGS_BASE_0 + 0x00) /* Used in .S files */
-#define GPP_DATA_OUT_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x04)
-#define GPP_BLINK_EN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x08)
-#define GPP_DATA_IN_POL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x0C)
-#define GPP_DATA_IN_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x10)
-#define GPP_INT_CAUSE_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x14)
-#define GPP_INT_MASK_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x18)
-#define GPP_INT_LVL_REG(grp) (MV_GPP_REGS_BASE(grp) + 0x1C)
-#define GPP_OUT_SET_REG(grp) (0x18130 + ((grp) * 0x40))
-#define GPP_64_66_DATA_OUT_SET_REG 0x181A4
-#define GPP_OUT_CLEAR_REG(grp) (0x18134 + ((grp) * 0x40))
-#define GPP_64_66_DATA_OUT_CLEAR_REG 0x181B0
-#define GPP_FUNC_SELECT_REG (MV_GPP_REGS_BASE(0) + 0x40)
-
-#define MV_GPP66 (1 << 2)
-
-/* Relevant for MV78XX0 */
-#define GPP_DATA_OUT_SET_REG (MV_GPP_REGS_BASE(0) + 0x20)
-#define GPP_DATA_OUT_CLEAR_REG (MV_GPP_REGS_BASE(0) + 0x24)
-
-/* This define describes the maximum number of supported PEX Interfaces */
-#define MV_PEX_MAX_IF 10
-#define MV_PEX_MAX_UNIT 4
-
-#define MV_SERDES_NUM_TO_PEX_NUM(num) ((num < 8) ? (num) : (8 + (num / 12)))
-
-#define PEX_PHY_ACCESS_REG(unit) (0x40000 + ((unit) % 2 * 0x40000) + \
- ((unit)/2 * 0x2000) + 0x1B00)
-
-#define SATA_BASE_REG(port) (0xA2000 + (port)*0x2000)
-
-#define SATA_PWR_PLL_CTRL_REG(port) (SATA_BASE_REG(port) + 0x804)
-#define SATA_DIG_LP_ENA_REG(port) (SATA_BASE_REG(port) + 0x88C)
-#define SATA_REF_CLK_SEL_REG(port) (SATA_BASE_REG(port) + 0x918)
-#define SATA_COMPHY_CTRL_REG(port) (SATA_BASE_REG(port) + 0x920)
-#define SATA_LP_PHY_EXT_CTRL_REG(port) (SATA_BASE_REG(port) + 0x058)
-#define SATA_LP_PHY_EXT_STAT_REG(port) (SATA_BASE_REG(port) + 0x05C)
-#define SATA_IMP_TX_SSC_CTRL_REG(port) (SATA_BASE_REG(port) + 0x810)
-#define SATA_GEN_1_SET_0_REG(port) (SATA_BASE_REG(port) + 0x834)
-#define SATA_GEN_1_SET_1_REG(port) (SATA_BASE_REG(port) + 0x838)
-#define SATA_GEN_2_SET_0_REG(port) (SATA_BASE_REG(port) + 0x83C)
-#define SATA_GEN_2_SET_1_REG(port) (SATA_BASE_REG(port) + 0x840)
-
-#define MV_ETH_BASE_ADDR (0x72000)
-#define MV_ETH_REGS_OFFSET(port) (MV_ETH_BASE_ADDR - ((port) / 2) * \
- 0x40000 + ((port) % 2) * 0x4000)
-#define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port)
-
-
-#define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)
-#define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)
-#define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)
-#define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0)
-#define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4)
-#define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20)
-#define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38)
-#define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0)
-
-#define SERDES_LINE_MUX_REG_0_7 0x18270
-#define SERDES_LINE_MUX_REG_8_15 0x18274
-#define QSGMII_CONTROL_1_REG 0x18404
-
-/* SOC_CTRL_REG fields */
-#define SCR_PEX_ENA_OFFS(pex) ((pex) & 0x3)
-#define SCR_PEX_ENA_MASK(pex) (1 << pex)
-
-#define PCIE0_QUADX1_EN (1<<7)
-#define PCIE1_QUADX1_EN (1<<8)
-
-#define SCR_PEX_4BY1_OFFS(pex) ((pex) + 7)
-#define SCR_PEX_4BY1_MASK(pex) (1 << SCR_PEX_4BY1_OFFS(pex))
-
-#define PCIE1_CLK_OUT_EN_OFF 5
-#define PCIE1_CLK_OUT_EN_MASK (1 << PCIE1_CLK_OUT_EN_OFF)
-
-#define PCIE0_CLK_OUT_EN_OFF 4
-#define PCIE0_CLK_OUT_EN_MASK (1 << PCIE0_CLK_OUT_EN_OFF)
-
-#define SCR_PEX0_4BY1_OFFS 7
-#define SCR_PEX0_4BY1_MASK (1 << SCR_PEX0_4BY1_OFFS)
-
-#define SCR_PEX1_4BY1_OFFS 8
-#define SCR_PEX1_4BY1_MASK (1 << SCR_PEX1_4BY1_OFFS)
-
-
-#define MV_MISC_REGS_OFFSET (0x18200)
-#define MV_MISC_REGS_BASE (MV_MISC_REGS_OFFSET)
-#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
-
-/*
- * PCI Express Control and Status Registers
- */
-#define MAX_PEX_DEVICES 32
-#define MAX_PEX_FUNCS 8
-#define MAX_PEX_BUSSES 256
-
-#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
-#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
-
-#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
-#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
-
-#define PXSR_DL_DOWN 0x1 /* DL_Down indication. */
-#define PXCAR_CONFIG_EN (1 << 31)
-#define PEX_STATUS_AND_COMMAND 0x004
-#define PXSAC_MABORT (1 << 29) /* Recieved Master Abort */
-
-/* PCI Express Configuration Address Register */
-
-/* PEX_CFG_ADDR_REG (PXCAR) */
-#define PXCAR_REG_NUM_OFFS 2
-#define PXCAR_REG_NUM_MAX 0x3F
-#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS)
-#define PXCAR_FUNC_NUM_OFFS 8
-#define PXCAR_FUNC_NUM_MAX 0x7
-#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS)
-#define PXCAR_DEVICE_NUM_OFFS 11
-#define PXCAR_DEVICE_NUM_MAX 0x1F
-#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS)
-#define PXCAR_BUS_NUM_OFFS 16
-#define PXCAR_BUS_NUM_MAX 0xFF
-#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS)
-#define PXCAR_EXT_REG_NUM_OFFS 24
-#define PXCAR_EXT_REG_NUM_MAX 0xF
-
-#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
-#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS)
-
-
-#define PEX_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x60)
-#define PEX_LINK_CAPABILITIES_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x6C)
-#define PEX_LINK_CTRL_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x70)
-#define PEX_LINK_CTRL_STATUS2_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x90)
-#define PEX_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A00)
-#define PEX_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A04)
-#define PEX_COMPLT_TMEOUT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A10)
-#define PEX_PWR_MNG_EXT_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A18)
-#define PEX_FLOW_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A20)
-#define PEX_DYNMC_WIDTH_MNG_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A30)
-#define PEX_ROOT_CMPLX_SSPL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A0C)
-#define PEX_RAM_PARITY_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A50)
-#define PEX_DBG_CTRL_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A60)
-#define PEX_DBG_STATUS_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1A64)
-
-#define PXLCSR_NEG_LNK_GEN_OFFS 16 /* Negotiated Link GEN */
-#define PXLCSR_NEG_LNK_GEN_MASK (0xf << PXLCSR_NEG_LNK_GEN_OFFS)
-#define PXLCSR_NEG_LNK_GEN_1_1 (0x1 << PXLCSR_NEG_LNK_GEN_OFFS)
-#define PXLCSR_NEG_LNK_GEN_2_0 (0x2 << PXLCSR_NEG_LNK_GEN_OFFS)
-
-#define PEX_CFG_ADDR_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18F8)
-#define PEX_CFG_DATA_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x18FC)
-#define PEX_CAUSE_REG(if) ((MV_PEX_IF_REGS_BASE(if)) + 0x1900)
-
-#define PEX_CAPABILITY_REG 0x60
-#define PEX_DEV_CAPABILITY_REG 0x64
-#define PEX_DEV_CTRL_STAT_REG 0x68
-#define PEX_LINK_CAPABILITY_REG 0x6C
-#define PEX_LINK_CTRL_STAT_REG 0x70
-#define PEX_LINK_CTRL_STAT_2_REG 0x90
-
-#endif /* __BOARD_ENV_SPEC */
+++ /dev/null
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-#include "high_speed_env_spec.h"
-#include "board_env_spec.h"
-
-#define SERDES_VERION "2.1.5"
-#define ENDED_OK "High speed PHY - Ended Successfully\n"
-
-static const u8 serdes_cfg[][SERDES_LAST_UNIT] = BIN_SERDES_CFG;
-
-extern MV_BIN_SERDES_CFG *serdes_info_tbl[];
-
-extern u8 rd78460gp_twsi_dev[];
-extern u8 db88f78xx0rev2_twsi_dev[];
-
-u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs);
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
-
-#define MV_BOARD_PEX_MODULE_ADDR 0x23
-#define MV_BOARD_PEX_MODULE_ID 1
-#define MV_BOARD_ETM_MODULE_ID 2
-
-#define PEX_MODULE_DETECT 1
-#define ETM_MODULE_DETECT 2
-
-#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
-#define PEX_CAPABILITY_GET(satr) (satr & 1)
-#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
-
-/* Static parametes */
-static int config_module;
-static int switch_module;
-
-/* Local function */
-static u32 board_id_get(void)
-{
-#if defined(CONFIG_DB_88F78X60)
- return DB_88F78XX0_BP_ID;
-#elif defined(CONFIG_RD_88F78460_SERVER)
- return RD_78460_SERVER_ID;
-#elif defined(CONFIG_RD_78460_SERVER_REV2)
- return RD_78460_SERVER_REV2_ID;
-#elif defined(CONFIG_DB_78X60_PCAC)
- return DB_78X60_PCAC_ID;
-#elif defined(CONFIG_DB_88F78X60_REV2)
- return DB_88F78XX0_BP_REV2_ID;
-#elif defined(CONFIG_RD_78460_NAS)
- return RD_78460_NAS_ID;
-#elif defined(CONFIG_DB_78X60_AMC)
- return DB_78X60_AMC_ID;
-#elif defined(CONFIG_DB_78X60_PCAC_REV2)
- return DB_78X60_PCAC_REV2_ID;
-#elif defined(CONFIG_DB_784MP_GP)
- return DB_784MP_GP_ID;
-#elif defined(CONFIG_RD_78460_CUSTOMER)
- return RD_78460_CUSTOMER_ID;
-#else
- /*
- * Return 0 here for custom board as this should not be used
- * for custom boards.
- */
- return 0;
-#endif
-}
-
-static u8 board_sat_r_get(u8 dev_num, u8 reg)
-{
- u8 data;
- u8 *dev;
- u32 board_id = board_id_get();
- int ret;
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- switch (board_id) {
- case DB_784MP_GP_ID:
- dev = rd78460gp_twsi_dev;
-
- break;
- case DB_88F78XX0_BP_ID:
- case DB_88F78XX0_BP_REV2_ID:
- dev = db88f78xx0rev2_twsi_dev;
- break;
-
- case DB_78X60_PCAC_ID:
- case FPGA_88F78XX0_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_SERVER_REV2_ID:
- default:
- return 0;
- }
-
- /* Read MPP module ID */
- ret = i2c_read(dev[dev_num], 0, 1, (u8 *)&data, 1);
- if (ret)
- return MV_ERROR;
-
- return data;
-}
-
-static int board_modules_scan(void)
-{
- u8 val;
- u32 board_id = board_id_get();
- int ret;
-
- /* Perform scan only for DB board */
- if ((board_id == DB_88F78XX0_BP_ID) ||
- (board_id == DB_88F78XX0_BP_REV2_ID)) {
- /* reset modules flags */
- config_module = 0;
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- /* SERDES module (only PEX model is supported now) */
- ret = i2c_read(MV_BOARD_PEX_MODULE_ADDR, 0, 1, (u8 *)&val, 1);
- if (ret)
- return MV_ERROR;
-
- if (val == MV_BOARD_PEX_MODULE_ID)
- config_module = PEX_MODULE_DETECT;
- if (val == MV_BOARD_ETM_MODULE_ID)
- config_module = ETM_MODULE_DETECT;
- } else if (board_id == RD_78460_NAS_ID) {
- switch_module = 0;
- if ((reg_read(GPP_DATA_IN_REG(2)) & MV_GPP66) == 0x0)
- switch_module = 1;
- }
-
- return MV_OK;
-}
-
-u32 pex_max_unit_get(void)
-{
- /*
- * TODO:
- * Right now only MV78460 is supported. Other SoC's might need
- * a different value here.
- */
- return MV_PEX_MAX_UNIT;
-}
-
-u32 pex_max_if_get(void)
-{
- /*
- * TODO:
- * Right now only MV78460 is supported. Other SoC's might need
- * a different value here.
- */
- return MV_PEX_MAX_IF;
-}
-
-u8 board_cpu_freq_get(void)
-{
- u32 sar;
- u32 sar_msb;
-
- sar = reg_read(MPP_SAMPLE_AT_RESET(0));
- sar_msb = reg_read(MPP_SAMPLE_AT_RESET(1));
- return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
-}
-
-__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
-{
- u32 board_id;
- u32 serdes_cfg_val = 0; /* default */
-
- board_id = board_id_get();
-
- switch (board_id) {
- case DB_784MP_GP_ID:
- serdes_cfg_val = 0;
- break;
- }
-
- return &serdes_info_tbl[board_id - BOARD_ID_BASE][serdes_cfg_val];
-}
-
-u16 ctrl_model_get(void)
-{
- /* Right now only MV78460 supported */
- return MV_78460_DEV_ID;
-}
-
-u32 get_line_cfg(u32 line_num, MV_BIN_SERDES_CFG *info)
-{
- if (line_num < 8)
- return (info->line0_7 >> (line_num << 2)) & 0xF;
- else
- return (info->line8_15 >> ((line_num - 8) << 2)) & 0xF;
-}
-
-int serdes_phy_config(void)
-{
- int status = MV_OK;
- u32 line_cfg;
- u8 line_num;
- /* addr/value for each line @ every setup step */
- u32 addr[16][11], val[16][11];
- u8 pex_unit, pex_line_num;
- u8 sgmii_port = 0;
- u32 tmp;
- u32 in_direct;
- u8 max_serdes_lines;
- MV_BIN_SERDES_CFG *info;
- u8 satr11;
- u8 sata_port;
- u8 freq;
- u8 device_rev;
- u32 rx_high_imp_mode;
- u16 ctrl_mode;
- u32 board_id = board_id_get();
- u32 pex_if;
- u32 pex_if_num;
-
- /*
- * TODO:
- * Right now we only support the MV78460 with 16 serdes lines
- */
- max_serdes_lines = 16;
- if (max_serdes_lines == 0)
- return MV_OK;
-
- switch (board_id) {
- case DB_78X60_AMC_ID:
- case DB_78X60_PCAC_REV2_ID:
- case RD_78460_CUSTOMER_ID:
- case RD_78460_SERVER_ID:
- case RD_78460_SERVER_REV2_ID:
- case DB_78X60_PCAC_ID:
- satr11 = (0x1 << 1) | 1;
- break;
- case FPGA_88F78XX0_ID:
- case RD_78460_NAS_ID:
- satr11 = (0x0 << 1) | 1;
- break;
- case DB_88F78XX0_BP_REV2_ID:
- case DB_784MP_GP_ID:
- case DB_88F78XX0_BP_ID:
- satr11 = board_sat_r_get(1, 1);
- if ((u8) MV_ERROR == (u8) satr11)
- return MV_ERROR;
- break;
- }
-
- board_modules_scan();
- memset(addr, 0, sizeof(addr));
- memset(val, 0, sizeof(val));
-
- /* Check if DRAM is already initialized */
- if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
- (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
- DEBUG_INIT_S("High speed PHY - Version: ");
- DEBUG_INIT_S(SERDES_VERION);
- DEBUG_INIT_S(" - 2nd boot - Skip\n");
- return MV_OK;
- }
- DEBUG_INIT_S("High speed PHY - Version: ");
- DEBUG_INIT_S(SERDES_VERION);
- DEBUG_INIT_S(" (COM-PHY-V20)\n");
-
- /*
- * AVS : disable AVS for frequency less than 1333
- */
- freq = board_cpu_freq_get();
- device_rev = mv_ctrl_rev_get();
-
- if (device_rev == 2) { /* for B0 only */
- u32 cpu_avs;
- u8 fabric_freq;
- cpu_avs = reg_read(CPU_AVS_CONTROL2_REG);
- DEBUG_RD_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
- cpu_avs &= ~(1 << 9);
-
- if ((0x4 == freq) || (0xB == freq)) {
- u32 tmp2;
-
- tmp2 = reg_read(CPU_AVS_CONTROL0_REG);
- DEBUG_RD_REG(CPU_AVS_CONTROL0_REG, tmp2);
- /* cpu upper limit = 1.1V cpu lower limit = 0.9125V */
- tmp2 |= 0x0FF;
- reg_write(CPU_AVS_CONTROL0_REG, tmp2);
- DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2);
- cpu_avs |= (1 << 9); /* cpu avs enable */
- cpu_avs |= (1 << 18); /* AvsAvddDetEn enable */
- fabric_freq = (reg_read(MPP_SAMPLE_AT_RESET(0)) &
- SAR0_FABRIC_FREQ_MASK) >> SAR0_FABRIC_FREQ_OFFSET;
- if ((0xB == freq) && (5 == fabric_freq)) {
- u32 core_avs;
-
- core_avs = reg_read(CORE_AVS_CONTROL_0REG);
- DEBUG_RD_REG(CORE_AVS_CONTROL_0REG, core_avs);
-
- /*
- * Set core lower limit = 0.9V &
- * core upper limit = 0.9125V
- */
- core_avs &= ~(0xff);
- core_avs |= 0x0E;
- reg_write(CORE_AVS_CONTROL_0REG, core_avs);
- DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs);
-
- core_avs = reg_read(CORE_AVS_CONTROL_2REG);
- DEBUG_RD_REG(CORE_AVS_CONTROL_2REG, core_avs);
- core_avs |= (1 << 9); /* core AVS enable */
- reg_write(CORE_AVS_CONTROL_2REG, core_avs);
- DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs);
-
- tmp2 = reg_read(GENERAL_PURPOSE_RESERVED0_REG);
- DEBUG_RD_REG(GENERAL_PURPOSE_RESERVED0_REG,
- tmp2);
- tmp2 |= 0x1; /* AvsCoreAvddDetEn enable */
- reg_write(GENERAL_PURPOSE_RESERVED0_REG, tmp2);
- DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG,
- tmp2);
- }
- }
- reg_write(CPU_AVS_CONTROL2_REG, cpu_avs);
- DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
- }
-
- info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
- DEBUG_INIT_FULL_S("info->line0_7= 0x");
- DEBUG_INIT_FULL_D(info->line0_7, 8);
- DEBUG_INIT_FULL_S(" info->line8_15= 0x");
- DEBUG_INIT_FULL_D(info->line8_15, 8);
- DEBUG_INIT_FULL_S("\n");
-
- if (info == NULL) {
- DEBUG_INIT_S("Hight speed PHY Error #1\n");
- return MV_ERROR;
- }
-
- if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */
- DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n");
- reg_write(SERDES_LINE_MUX_REG_0_7, 0x11111111);
- DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111);
- info->pex_mode[1] = PEX_BUS_DISABLED; /* pex unit 1 is configure for ETM */
- mdelay(100);
- reg_write(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x011 << 16) | 0x0BFF); /* SETM0 - G3 full swing AMP */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x311 << 16) | 0x0BFF); /* SETM1 - G3 full swing AMP */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x023 << 16) | 0x0800); /* SETM0 - 40 data bit width */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x323 << 16) | 0x0800); /* SETM1 - 40 data bit width */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x046 << 16) | 0x0400); /* lane0(serdes4) */
- reg_write(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x346 << 16) | 0x0400); /* lane3(serdes7) */
- }
-
- /* STEP -1 [PEX-Only] First phase of PEX-PIPE Configuration: */
- DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n");
- for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
- continue;
-
- /* 1. GLOB_CLK_CTRL Reset and Clock Control */
- reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), (0xC1 << 16) | 0x25);
-
- /* 2. GLOB_TEST_CTRL Test Mode Control */
- if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) {
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC2 << 16) | 0x200);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC2 << 16) | 0x200);
- }
-
- /* 3. GLOB_CLK_SRC_LO Clock Source Low */
- if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC3 << 16) | 0x0F);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC3 << 16) | 0x0F);
- }
-
- reg_write(PEX_PHY_ACCESS_REG(pex_unit), (0xC5 << 16) | 0x11F);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC5 << 16) | 0x11F);
- }
-
- /*
- * 2 Configure the desire PIN_PHY_GEN and do power down to the PU_PLL,
- * PU_RX,PU_TX. (bits[12:5])
- */
- DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n");
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- line_cfg = get_line_cfg(line_num, info);
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
- continue;
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
- continue;
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
- switch (line_num) {
- case 4:
- case 6:
- sata_port = 0;
- break;
- case 5:
- sata_port = 1;
- break;
- default:
- DEBUG_INIT_C
- ("SATA port error for serdes line: ",
- line_num, 2);
- return MV_ERROR;
- }
- tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
- DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
- tmp &= ~((0x1ff << 5) | 0x7);
- tmp |= ((info->bus_speed & (1 << line_num)) != 0) ?
- (0x11 << 5) : 0x0;
-
- reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
- DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
- /*
- * 4) Configure the desire PIN_PHY_GEN and do power
- * down to the PU_PLL,PU_RX,PU_TX. (bits[12:5])
- */
- tmp = reg_read(SGMII_SERDES_CFG_REG(0));
- DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
- tmp &= ~((0x1ff << 5) | 0x7);
- tmp |= 0x660;
- reg_write(SGMII_SERDES_CFG_REG(0), tmp);
- DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
- sgmii_port = 0;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
- sgmii_port = 1;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
- sgmii_port = 2;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
- sgmii_port = 3;
- else
- continue;
-
- tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
- DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
- tmp &= ~((0x1ff << 5) | 0x7);
- tmp |= (((info->bus_speed & (1 << line_num)) != 0) ?
- (0x88 << 5) : (0x66 << 5));
- reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
- DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
- }
-
- /* Step 3 - QSGMII enable */
- DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n");
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- line_cfg = get_line_cfg(line_num, info);
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
- /* QSGMII Active bit set to true */
- tmp = reg_read(QSGMII_CONTROL_1_REG);
- DEBUG_RD_REG(QSGMII_CONTROL_1_REG, tmp);
- tmp |= (1 << 30);
-#ifdef ERRATA_GL_6572255
- tmp |= (1 << 27);
-#endif
- reg_write(QSGMII_CONTROL_1_REG, tmp);
- DEBUG_WR_REG(QSGMII_CONTROL_1_REG, tmp);
- }
- }
-
- /* Step 4 - configure SERDES MUXes */
- DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n");
- if (config_module & ETM_MODULE_DETECT) {
- reg_write(SERDES_LINE_MUX_REG_0_7, 0x40041111);
- DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x40041111);
- } else {
- reg_write(SERDES_LINE_MUX_REG_0_7, info->line0_7);
- DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, info->line0_7);
- }
- reg_write(SERDES_LINE_MUX_REG_8_15, info->line8_15);
- DEBUG_WR_REG(SERDES_LINE_MUX_REG_8_15, info->line8_15);
-
- /* Step 5: Activate the RX High Impedance Mode */
- DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n");
- rx_high_imp_mode = 0x8080;
- if (device_rev == 2) /* for B0 only */
- rx_high_imp_mode |= 4;
-
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- /* for each serdes lane */
- DEBUG_INIT_FULL_S("SERDES ");
- DEBUG_INIT_FULL_D_10(line_num, 2);
- line_cfg = get_line_cfg(line_num, info);
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED]) {
- DEBUG_INIT_FULL_S(" unconnected ***\n");
- continue;
- }
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
- pex_unit = line_num >> 2;
- pex_line_num = line_num % 4;
- DEBUG_INIT_FULL_S(" - PEX unit ");
- DEBUG_INIT_FULL_D_10(pex_unit, 1);
- DEBUG_INIT_FULL_S(" line= ");
- DEBUG_INIT_FULL_D_10(pex_line_num, 1);
- DEBUG_INIT_FULL_S("\n");
-
- /* Needed for PEX_PHY_ACCESS_REG macro */
- if ((line_num > 7) &&
- (info->pex_mode[3] == PEX_BUS_MODE_X8))
- /* lines 8 - 15 are belong to PEX3 in x8 mode */
- pex_unit = 3;
-
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
- continue;
-
- /*
- * 8) Activate the RX High Impedance Mode field
- * (bit [2]) in register /PCIe_USB Control (Each MAC
- * contain different Access to reach its
- * Serdes-Regfile).
- * [PEX-Only] Set bit[12]: The analog part latches idle
- * if PU_TX = 1 and PU_PLL =1.
- */
-
- /* Termination enable */
- if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1) {
- in_direct = (0x48 << 16) | (pex_line_num << 24) |
- 0x1000 | rx_high_imp_mode; /* x1 */
- } else if ((info->pex_mode[pex_unit] ==
- PEX_BUS_MODE_X4) && (pex_line_num == 0))
- in_direct = (0x48 << 16) | (pex_line_num << 24) |
- 0x1000 | (rx_high_imp_mode & 0xff); /* x4 */
- else
- in_direct = 0;
-
- if (in_direct) {
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- in_direct);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- in_direct);
- }
-
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
- /*
- * port 0 for serdes lines 4,6, and port 1 for
- * serdes lines 5
- */
- sata_port = line_num & 1;
- DEBUG_INIT_FULL_S(" - SATA port ");
- DEBUG_INIT_FULL_D_10(sata_port, 2);
- DEBUG_INIT_FULL_S("\n");
- reg_write(SATA_COMPHY_CTRL_REG(sata_port),
- rx_high_imp_mode);
- DEBUG_WR_REG(SATA_COMPHY_CTRL_REG(sata_port),
- rx_high_imp_mode);
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
- DEBUG_INIT_FULL_S(" - QSGMII\n");
- reg_write(SGMII_COMPHY_CTRL_REG(0), rx_high_imp_mode);
- DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(0),
- rx_high_imp_mode);
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
- sgmii_port = 0;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
- sgmii_port = 1;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
- sgmii_port = 2;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
- sgmii_port = 3;
- else
- continue;
- DEBUG_INIT_FULL_S(" - SGMII port ");
- DEBUG_INIT_FULL_D_10(sgmii_port, 2);
- DEBUG_INIT_FULL_S("\n");
- reg_write(SGMII_COMPHY_CTRL_REG(sgmii_port), rx_high_imp_mode);
- DEBUG_WR_REG(SGMII_COMPHY_CTRL_REG(sgmii_port),
- rx_high_imp_mode);
- } /* for each serdes lane */
-
- /* Step 6 [PEX-Only] PEX-Main configuration (X4 or X1): */
- DEBUG_INIT_FULL_S("Step 6: [PEX-Only] PEX-Main configuration (X4 or X1)\n");
- tmp = reg_read(SOC_CTRL_REG);
- DEBUG_RD_REG(SOC_CTRL_REG, tmp);
- tmp &= 0x200;
- if (info->pex_mode[0] == PEX_BUS_MODE_X1)
- tmp |= PCIE0_QUADX1_EN;
- if (info->pex_mode[1] == PEX_BUS_MODE_X1)
- tmp |= PCIE1_QUADX1_EN;
- if (((reg_read(MPP_SAMPLE_AT_RESET(0)) & PEX_CLK_100MHZ_MASK) >>
- PEX_CLK_100MHZ_OFFSET) == 0x1)
- tmp |= (PCIE0_CLK_OUT_EN_MASK | PCIE1_CLK_OUT_EN_MASK);
-
- reg_write(SOC_CTRL_REG, tmp);
- DEBUG_WR_REG(SOC_CTRL_REG, tmp);
-
- /* 6.2 PCI Express Link Capabilities */
- DEBUG_INIT_FULL_S("Step 6.2: [PEX-Only] PCI Express Link Capabilities\n");
-
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- line_cfg = get_line_cfg(line_num, info);
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
- /*
- * PCI Express Control
- * 0xX1A00 [0]:
- * 0x0 X4-Link.
- * 0x1 X1-Link
- */
- pex_unit = line_num >> 2;
- pex_if = MV_SERDES_NUM_TO_PEX_NUM(line_num);
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
- continue;
-
- /* set Common Clock Configuration */
- tmp = reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
- DEBUG_RD_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
- tmp |= (1 << 6);
- reg_write(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
- DEBUG_WR_REG(PEX_LINK_CTRL_STATUS_REG(pex_if), tmp);
-
- tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
- DEBUG_RD_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
- tmp &= ~(0x3FF);
- if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X1)
- tmp |= (0x1 << 4);
- if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
- tmp |= (0x4 << 4);
- if (0 == PEX_CAPABILITY_GET(satr11))
- tmp |= 0x1;
- else
- tmp |= 0x2;
- DEBUG_INIT_FULL_S("Step 6.2: PEX ");
- DEBUG_INIT_FULL_D(pex_if, 1);
- DEBUG_INIT_FULL_C(" set GEN", (tmp & 3), 1);
- reg_write(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
- DEBUG_WR_REG(PEX_LINK_CAPABILITIES_REG(pex_if), tmp);
-
- /*
- * If pex is X4, no need to pass thru the other
- * 3X1 serdes lines
- */
- if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
- line_num += 3;
- }
- }
-
- /*
- * Step 7 [PEX-X4 Only] To create PEX-Link that contain 4-lanes you
- * need to config the register SOC_Misc/General Purpose2
- * (Address= 182F8)
- */
- DEBUG_INIT_FULL_S("Step 7: [PEX-X4 Only] To create PEX-Link\n");
- tmp = reg_read(GEN_PURP_RES_2_REG);
- DEBUG_RD_REG(GEN_PURP_RES_2_REG, tmp);
-
- tmp &= 0xFFFF0000;
- if (info->pex_mode[0] == PEX_BUS_MODE_X4)
- tmp |= 0x0000000F;
-
- if (info->pex_mode[1] == PEX_BUS_MODE_X4)
- tmp |= 0x000000F0;
-
- if (info->pex_mode[2] == PEX_BUS_MODE_X4)
- tmp |= 0x00000F00;
-
- if (info->pex_mode[3] == PEX_BUS_MODE_X4)
- tmp |= 0x0000F000;
-
- reg_write(GEN_PURP_RES_2_REG, tmp);
- DEBUG_WR_REG(GEN_PURP_RES_2_REG, tmp);
-
- /* Steps 8 , 9 ,10 - use prepared REG addresses and values */
- DEBUG_INIT_FULL_S("Steps 7,8,9,10 and 11\n");
-
- /* Prepare PHY parameters for each step according to MUX selection */
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- /* for each serdes lane */
-
- line_cfg = get_line_cfg(line_num, info);
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
- continue;
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
- pex_unit = line_num >> 2;
- pex_line_num = line_num % 4;
-
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
- continue;
- /*
- * 8) Configure the desire PHY_MODE (bits [7:5])
- * and REF_FREF_SEL (bits[4:0]) in the register Power
- * and PLL Control (Each MAC contain different Access
- * to reach its Serdes-Regfile).
- */
- if (((info->pex_mode[pex_unit] == PEX_BUS_MODE_X4) &&
- (0 == pex_line_num))
- || ((info->pex_mode[pex_unit] == PEX_BUS_MODE_X1))) {
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- (0x01 << 16) | (pex_line_num << 24) |
- 0xFC60);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0x01 << 16) | (pex_line_num << 24)
- | 0xFC60);
- /*
- * Step 8.1: [PEX-Only] Configure Max PLL Rate
- * (bit 8 in KVCO Calibration Control and
- * bits[10:9] in
- */
- /* Use Maximum PLL Rate(Bit 8) */
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- (0x02 << 16) | (1 << 31) |
- (pex_line_num << 24)); /* read command */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0x02 << 16) | (1 << 31) |
- (pex_line_num << 24));
- tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
- DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
- tmp &= ~(1 << 31);
- tmp |= (1 << 8);
- reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
-
- /* Use Maximum PLL Rate(Bits [10:9]) */
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- (0x81 << 16) | (1 << 31) |
- (pex_line_num << 24)); /* read command */
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0x81 << 16) | (1 << 31) |
- (pex_line_num << 24));
- tmp = reg_read(PEX_PHY_ACCESS_REG(pex_unit));
- DEBUG_RD_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
- tmp &= ~(1 << 31);
- tmp |= (3 << 9);
- reg_write(PEX_PHY_ACCESS_REG(pex_unit), tmp);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit), tmp);
- }
-
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
- /*
- * Port 0 for serdes lines 4,6, and port 1 for serdes
- * lines 5
- */
- sata_port = line_num & 1;
-
- /*
- * 8) Configure the desire PHY_MODE (bits [7:5]) and
- * REF_FREF_SEL (bits[4:0]) in the register Power
- * and PLL Control (Each MAC contain different Access
- * to reach its Serdes-Regfile).
- */
- reg_write(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
- DEBUG_WR_REG(SATA_PWR_PLL_CTRL_REG(sata_port), 0xF801);
-
- /* 9) Configure the desire SEL_BITS */
- reg_write(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
- DEBUG_WR_REG(SATA_DIG_LP_ENA_REG(sata_port), 0x400);
-
- /* 10) Configure the desire REFCLK_SEL */
-
- reg_write(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
- DEBUG_WR_REG(SATA_REF_CLK_SEL_REG(sata_port), 0x400);
-
- /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
- tmp = reg_read(SATA_LP_PHY_EXT_CTRL_REG(sata_port));
- DEBUG_RD_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
- tmp |= 7;
- reg_write(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
- DEBUG_WR_REG(SATA_LP_PHY_EXT_CTRL_REG(sata_port), tmp);
-
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
- /*
- * 8) Configure the desire PHY_MODE (bits [7:5])
- * and REF_FREF_SEL (bits[4:0]) in the register
- */
- reg_write(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
- DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(0), 0xF881);
-
- /*
- * 9) Configure the desire SEL_BITS (bits [11:0]
- * in register
- */
- reg_write(SGMII_DIG_LP_ENA_REG(0), 0x400);
- DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(0), 0x400);
-
- /*
- * 10) Configure the desire REFCLK_SEL (bit [10])
- * in register
- */
- reg_write(SGMII_REF_CLK_SEL_REG(0), 0x400);
- DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(0), 0x400);
-
- /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
- tmp = reg_read(SGMII_SERDES_CFG_REG(0));
- DEBUG_RD_REG(SGMII_SERDES_CFG_REG(0), tmp);
- tmp |= 7;
- reg_write(SGMII_SERDES_CFG_REG(0), tmp);
- DEBUG_WR_REG(SGMII_SERDES_CFG_REG(0), tmp);
- continue;
- }
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII0])
- sgmii_port = 0;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII1])
- sgmii_port = 1;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII2])
- sgmii_port = 2;
- else if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SGMII3])
- sgmii_port = 3;
- else
- continue;
-
- /*
- * 8) Configure the desire PHY_MODE (bits [7:5]) and
- * REF_FREF_SEL (bits[4:0]) in the register
- */
- reg_write(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
- DEBUG_WR_REG(SGMII_PWR_PLL_CTRL_REG(sgmii_port), 0xF881);
-
- /* 9) Configure the desire SEL_BITS (bits [11:0] in register */
- reg_write(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
- DEBUG_WR_REG(SGMII_DIG_LP_ENA_REG(sgmii_port), 0);
-
- /* 10) Configure the desire REFCLK_SEL (bit [10]) in register */
- reg_write(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
- DEBUG_WR_REG(SGMII_REF_CLK_SEL_REG(sgmii_port), 0x400);
-
- /* 11) Power up to the PU_PLL,PU_RX,PU_TX. */
- tmp = reg_read(SGMII_SERDES_CFG_REG(sgmii_port));
- DEBUG_RD_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
- tmp |= 7;
- reg_write(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
- DEBUG_WR_REG(SGMII_SERDES_CFG_REG(sgmii_port), tmp);
-
- } /* for each serdes lane */
-
- /* Step 12 [PEX-Only] Last phase of PEX-PIPE Configuration */
- DEBUG_INIT_FULL_S("Steps 12: [PEX-Only] Last phase of PEX-PIPE Configuration\n");
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- /* for each serdes lane */
-
- line_cfg = get_line_cfg(line_num, info);
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
- continue;
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX]) {
- pex_unit = line_num >> 2;
- pex_line_num = line_num % 4;
- if (0 == pex_line_num) {
- reg_write(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC1 << 16) | 0x24);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG(pex_unit),
- (0xC1 << 16) | 0x24);
- }
- }
- }
-
- /*--------------------------------------------------------------*/
- /* Step 13: Wait 15ms before checking results */
- DEBUG_INIT_FULL_S("Steps 13: Wait 15ms before checking results");
- mdelay(15);
- tmp = 20;
- while (tmp) {
- status = MV_OK;
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- u32 tmp;
- line_cfg = get_line_cfg(line_num, info);
- if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
- continue;
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_PEX])
- continue;
-
- if (line_cfg == serdes_cfg[line_num][SERDES_UNIT_SATA]) {
- /*
- * Port 0 for serdes lines 4,6, and port 1
- * for serdes lines 5
- */
- sata_port = line_num & 1;
-
- tmp =
- reg_read(SATA_LP_PHY_EXT_STAT_REG
- (sata_port));
- DEBUG_RD_REG(SATA_LP_PHY_EXT_STAT_REG
- (sata_port), tmp);
- if ((tmp & 0x7) != 0x7)
- status = MV_ERROR;
- continue;
- }
-
- if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_QSGMII]) {
- tmp = reg_read(SGMII_SERDES_STAT_REG(0));
- DEBUG_RD_REG(SGMII_SERDES_STAT_REG(0), tmp);
- if ((tmp & 0x7) != 0x7)
- status = MV_ERROR;
- continue;
- }
-
- if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_SGMII0])
- sgmii_port = 0;
- else if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_SGMII1])
- sgmii_port = 1;
- else if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_SGMII2])
- sgmii_port = 2;
- else if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_SGMII3])
- sgmii_port = 3;
- else
- continue;
-
- tmp = reg_read(SGMII_SERDES_STAT_REG(sgmii_port));
- DEBUG_RD_REG(SGMII_SERDES_STAT_REG(sgmii_port), tmp);
- if ((tmp & 0x7) != 0x7)
- status = MV_ERROR;
- }
-
- if (status == MV_OK)
- break;
- mdelay(5);
- tmp--;
- }
-
- /*
- * Step14 [PEX-Only] In order to configure RC/EP mode please write
- * to register 0x0060 bits
- */
- DEBUG_INIT_FULL_S("Steps 14: [PEX-Only] In order to configure\n");
- for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
- continue;
- tmp =
- reg_read(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)));
- DEBUG_RD_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
- tmp);
- tmp &= ~(0xf << 20);
- if (info->pex_type == MV_PEX_ROOT_COMPLEX)
- tmp |= (0x4 << 20);
- else
- tmp |= (0x1 << 20);
- reg_write(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
- tmp);
- DEBUG_WR_REG(PEX_CAPABILITIES_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
- tmp);
- }
-
- /*
- * Step 15 [PEX-Only] Only for EP mode set to Zero bits 19 and 16 of
- * register 0x1a60
- */
- DEBUG_INIT_FULL_S("Steps 15: [PEX-Only] In order to configure\n");
- for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED)
- continue;
- if (info->pex_type == MV_PEX_END_POINT) {
- tmp =
- reg_read(PEX_DBG_CTRL_REG
- (MV_PEX_UNIT_TO_IF(pex_unit)));
- DEBUG_RD_REG(PEX_DBG_CTRL_REG
- (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
- tmp &= 0xfff6ffff;
- reg_write(PEX_DBG_CTRL_REG(MV_PEX_UNIT_TO_IF(pex_unit)),
- tmp);
- DEBUG_WR_REG(PEX_DBG_CTRL_REG
- (MV_PEX_UNIT_TO_IF(pex_unit)), tmp);
- }
- }
-
- if (info->serdes_m_phy_change) {
- MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
- u32 bus_speed;
- for (line_num = 0; line_num < max_serdes_lines; line_num++) {
- line_cfg = get_line_cfg(line_num, info);
- if (line_cfg ==
- serdes_cfg[line_num][SERDES_UNIT_UNCONNECTED])
- continue;
- serdes_m_phy_change = info->serdes_m_phy_change;
- bus_speed = info->bus_speed & (1 << line_num);
- while (serdes_m_phy_change->type !=
- SERDES_UNIT_UNCONNECTED) {
- switch (serdes_m_phy_change->type) {
- case SERDES_UNIT_PEX:
- if (line_cfg != SERDES_UNIT_PEX)
- break;
- pex_unit = line_num >> 2;
- pex_line_num = line_num % 4;
- if (info->pex_mode[pex_unit] ==
- PEX_BUS_DISABLED)
- break;
- if ((info->pex_mode[pex_unit] ==
- PEX_BUS_MODE_X4) && pex_line_num)
- break;
-
- if (bus_speed) {
- reg_write(PEX_PHY_ACCESS_REG
- (pex_unit),
- (pex_line_num << 24) |
- serdes_m_phy_change->val_hi_speed);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG
- (pex_unit),
- (pex_line_num <<
- 24) |
- serdes_m_phy_change->val_hi_speed);
- } else {
- reg_write(PEX_PHY_ACCESS_REG
- (pex_unit),
- (pex_line_num << 24) |
- serdes_m_phy_change->val_low_speed);
- DEBUG_WR_REG(PEX_PHY_ACCESS_REG
- (pex_unit),
- (pex_line_num <<
- 24) |
- serdes_m_phy_change->val_low_speed);
- }
- break;
- case SERDES_UNIT_SATA:
- if (line_cfg != SERDES_UNIT_SATA)
- break;
- /*
- * Port 0 for serdes lines 4,6, and
- * port 1 for serdes lines 5
- */
- sata_port = line_num & 1;
- if (bus_speed) {
- reg_write(SATA_BASE_REG
- (sata_port) |
- serdes_m_phy_change->reg_hi_speed,
- serdes_m_phy_change->val_hi_speed);
- DEBUG_WR_REG(SATA_BASE_REG
- (sata_port) |
- serdes_m_phy_change->reg_hi_speed,
- serdes_m_phy_change->val_hi_speed);
- } else {
- reg_write(SATA_BASE_REG
- (sata_port) |
- serdes_m_phy_change->reg_low_speed,
- serdes_m_phy_change->val_low_speed);
- DEBUG_WR_REG(SATA_BASE_REG
- (sata_port) |
- serdes_m_phy_change->reg_low_speed,
- serdes_m_phy_change->val_low_speed);
- }
- break;
- case SERDES_UNIT_SGMII0:
- case SERDES_UNIT_SGMII1:
- case SERDES_UNIT_SGMII2:
- case SERDES_UNIT_SGMII3:
- if (line_cfg == serdes_cfg[line_num]
- [SERDES_UNIT_SGMII0])
- sgmii_port = 0;
- else if (line_cfg ==
- serdes_cfg[line_num]
- [SERDES_UNIT_SGMII1])
- sgmii_port = 1;
- else if (line_cfg ==
- serdes_cfg[line_num]
- [SERDES_UNIT_SGMII2])
- sgmii_port = 2;
- else if (line_cfg ==
- serdes_cfg[line_num]
- [SERDES_UNIT_SGMII3])
- sgmii_port = 3;
- else
- break;
- if (bus_speed) {
- reg_write(MV_ETH_REGS_BASE
- (sgmii_port) |
- serdes_m_phy_change->reg_hi_speed,
- serdes_m_phy_change->val_hi_speed);
- DEBUG_WR_REG(MV_ETH_REGS_BASE
- (sgmii_port) |
- serdes_m_phy_change->reg_hi_speed,
- serdes_m_phy_change->val_hi_speed);
- } else {
- reg_write(MV_ETH_REGS_BASE
- (sgmii_port) |
- serdes_m_phy_change->reg_low_speed,
- serdes_m_phy_change->val_low_speed);
- DEBUG_WR_REG(MV_ETH_REGS_BASE
- (sgmii_port) |
- serdes_m_phy_change->reg_low_speed,
- serdes_m_phy_change->val_low_speed);
- }
- break;
- case SERDES_UNIT_QSGMII:
- if (line_cfg != SERDES_UNIT_QSGMII)
- break;
- if (bus_speed) {
- reg_write
- (serdes_m_phy_change->reg_hi_speed,
- serdes_m_phy_change->val_hi_speed);
- DEBUG_WR_REG
- (serdes_m_phy_change->reg_hi_speed,
- serdes_m_phy_change->val_hi_speed);
- } else {
- reg_write
- (serdes_m_phy_change->reg_low_speed,
- serdes_m_phy_change->val_low_speed);
- DEBUG_WR_REG
- (serdes_m_phy_change->reg_low_speed,
- serdes_m_phy_change->val_low_speed);
- }
- break;
- default:
- break;
- }
- serdes_m_phy_change++;
- }
- }
- }
-
- /* Step 16 [PEX-Only] Training Enable */
- DEBUG_INIT_FULL_S("Steps 16: [PEX-Only] Training Enable");
- tmp = reg_read(SOC_CTRL_REG);
- DEBUG_RD_REG(SOC_CTRL_REG, tmp);
- tmp &= ~(0x0F);
- for (pex_unit = 0; pex_unit < pex_max_unit_get(); pex_unit++) {
- reg_write(PEX_CAUSE_REG(pex_unit), 0);
- DEBUG_WR_REG(PEX_CAUSE_REG(pex_unit), 0);
- if (info->pex_mode[pex_unit] != PEX_BUS_DISABLED)
- tmp |= (0x1 << pex_unit);
- }
- reg_write(SOC_CTRL_REG, tmp);
- DEBUG_WR_REG(SOC_CTRL_REG, tmp);
-
- /* Step 17: Speed change to target speed and width */
- {
- u32 tmp_reg, tmp_pex_reg;
- u32 addr;
- u32 first_busno, next_busno;
- u32 max_link_width = 0;
- u32 neg_link_width = 0;
- pex_if_num = pex_max_if_get();
- mdelay(150);
- DEBUG_INIT_FULL_C("step 17: max_if= 0x", pex_if_num, 1);
- next_busno = 0;
- for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
- line_num = (pex_if <= 8) ? pex_if : 12;
- line_cfg = get_line_cfg(line_num, info);
- if (line_cfg != serdes_cfg[line_num][SERDES_UNIT_PEX])
- continue;
- pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
- DEBUG_INIT_FULL_S("step 17: PEX");
- DEBUG_INIT_FULL_D(pex_if, 1);
- DEBUG_INIT_FULL_C(" pex_unit= ", pex_unit, 1);
-
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
- DEBUG_INIT_FULL_C("PEX disabled interface ",
- pex_if, 1);
- if (pex_if < 8)
- pex_if += 3;
- continue;
- }
- first_busno = next_busno;
- if ((info->pex_type == MV_PEX_END_POINT) &&
- (0 == pex_if)) {
- if ((pex_if < 8) && (info->pex_mode[pex_unit] ==
- PEX_BUS_MODE_X4))
- pex_if += 3;
- continue;
- }
-
- tmp = reg_read(PEX_DBG_STATUS_REG(pex_if));
- DEBUG_RD_REG(PEX_DBG_STATUS_REG(pex_if), tmp);
- if ((tmp & 0x7f) == 0x7e) {
- next_busno++;
- tmp = reg_read(PEX_LINK_CAPABILITIES_REG(pex_if));
- max_link_width = tmp;
- DEBUG_RD_REG((PEX_LINK_CAPABILITIES_REG
- (pex_if)), tmp);
- max_link_width = ((max_link_width >> 4) & 0x3F);
- neg_link_width =
- reg_read(PEX_LINK_CTRL_STATUS_REG(pex_if));
- DEBUG_RD_REG((PEX_LINK_CTRL_STATUS_REG(pex_if)),
- neg_link_width);
- neg_link_width = ((neg_link_width >> 20) & 0x3F);
- if (max_link_width > neg_link_width) {
- tmp &= ~(0x3F << 4);
- tmp |= (neg_link_width << 4);
- reg_write(PEX_LINK_CAPABILITIES_REG
- (pex_if), tmp);
- DEBUG_WR_REG((PEX_LINK_CAPABILITIES_REG
- (pex_if)), tmp);
- mdelay(1); /* wait 1ms before reading capability for speed */
- DEBUG_INIT_S("PEX");
- DEBUG_INIT_D(pex_if, 1);
- DEBUG_INIT_C(": change width to X",
- neg_link_width, 1);
- }
- tmp_pex_reg =
- reg_read((PEX_CFG_DIRECT_ACCESS
- (pex_if,
- PEX_LINK_CAPABILITY_REG)));
- DEBUG_RD_REG((PEX_CFG_DIRECT_ACCESS
- (pex_if,
- PEX_LINK_CAPABILITY_REG)),
- tmp_pex_reg);
- tmp_pex_reg &= (0xF);
- if (tmp_pex_reg == 0x2) {
- tmp_reg =
- (reg_read
- (PEX_CFG_DIRECT_ACCESS
- (pex_if,
- PEX_LINK_CTRL_STAT_REG)) &
- 0xF0000) >> 16;
- DEBUG_RD_REG(PEX_CFG_DIRECT_ACCESS
- (pex_if,
- PEX_LINK_CTRL_STAT_REG),
- tmp_pex_reg);
- /* check if the link established is GEN1 */
- if (tmp_reg == 0x1) {
- pex_local_bus_num_set(pex_if,
- first_busno);
- pex_local_dev_num_set(pex_if,
- 1);
-
- DEBUG_INIT_FULL_S("** Link is Gen1, check the EP capability\n");
- /* link is Gen1, check the EP capability */
- addr =
- pex_cfg_read(pex_if,
- first_busno, 0,
- 0,
- 0x34) & 0xFF;
- DEBUG_INIT_FULL_C("pex_cfg_read: return addr=0x%x",
- addr, 4);
- if (addr == 0xff) {
- DEBUG_INIT_FULL_C("pex_cfg_read: return 0xff -->PEX (%d): Detected No Link.",
- pex_if, 1);
- continue;
- }
- while ((pex_cfg_read
- (pex_if, first_busno, 0,
- 0,
- addr) & 0xFF) !=
- 0x10) {
- addr =
- (pex_cfg_read
- (pex_if,
- first_busno, 0, 0,
- addr) & 0xFF00) >>
- 8;
- }
- if ((pex_cfg_read
- (pex_if, first_busno, 0, 0,
- addr + 0xC) & 0xF) >=
- 0x2) {
- tmp =
- reg_read
- (PEX_LINK_CTRL_STATUS2_REG
- (pex_if));
- DEBUG_RD_REG
- (PEX_LINK_CTRL_STATUS2_REG
- (pex_if), tmp);
- tmp &= ~(0x1 | 1 << 1);
- tmp |= (1 << 1);
- reg_write
- (PEX_LINK_CTRL_STATUS2_REG
- (pex_if), tmp);
- DEBUG_WR_REG
- (PEX_LINK_CTRL_STATUS2_REG
- (pex_if), tmp);
-
- tmp =
- reg_read
- (PEX_CTRL_REG
- (pex_if));
- DEBUG_RD_REG
- (PEX_CTRL_REG
- (pex_if), tmp);
- tmp |= (1 << 10);
- reg_write(PEX_CTRL_REG
- (pex_if),
- tmp);
- DEBUG_WR_REG
- (PEX_CTRL_REG
- (pex_if), tmp);
- mdelay(10); /* We need to wait 10ms before reading the PEX_DBG_STATUS_REG in order not to read the status of the former state */
- DEBUG_INIT_FULL_S
- ("Gen2 client!\n");
- } else {
- DEBUG_INIT_FULL_S
- ("GEN1 client!\n");
- }
- }
- }
- } else {
- DEBUG_INIT_FULL_S("PEX");
- DEBUG_INIT_FULL_D(pex_if, 1);
- DEBUG_INIT_FULL_S(" : Detected No Link. Status Reg(0x");
- DEBUG_INIT_FULL_D(PEX_DBG_STATUS_REG(pex_if),
- 8);
- DEBUG_INIT_FULL_C(") = 0x", tmp, 8);
- }
-
- if ((pex_if < 8) &&
- (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
- pex_if += 3;
- }
- }
-
- /* Step 18: update pex DEVICE ID */
- {
- u32 devId;
- pex_if_num = pex_max_if_get();
- ctrl_mode = ctrl_model_get();
- for (pex_if = 0; pex_if < pex_if_num; pex_if++) {
- pex_unit = (pex_if < 9) ? (pex_if >> 2) : 3;
- if (info->pex_mode[pex_unit] == PEX_BUS_DISABLED) {
- if ((pex_if < 8) &&
- (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
- pex_if += 3;
- continue;
- }
-
- devId = reg_read(PEX_CFG_DIRECT_ACCESS(
- pex_if, PEX_DEVICE_AND_VENDOR_ID));
- devId &= 0xFFFF;
- devId |= ((ctrl_mode << 16) & 0xffff0000);
- DEBUG_INIT_S("Update Device ID PEX");
- DEBUG_INIT_D(pex_if, 1);
- DEBUG_INIT_D(devId, 8);
- DEBUG_INIT_S("\n");
- reg_write(PEX_CFG_DIRECT_ACCESS
- (pex_if, PEX_DEVICE_AND_VENDOR_ID), devId);
- if ((pex_if < 8) &&
- (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4))
- pex_if += 3;
- }
- DEBUG_INIT_S("Update PEX Device ID 0x");
- DEBUG_INIT_D(ctrl_mode, 4);
- DEBUG_INIT_S("0\n");
- }
- tmp = reg_read(PEX_DBG_STATUS_REG(0));
- DEBUG_RD_REG(PEX_DBG_STATUS_REG(0), tmp);
-
- DEBUG_INIT_S(ENDED_OK);
- return MV_OK;
-}
-
-/* PEX configuration space read write */
-
-/*
- * pex_cfg_read - Read from configuration space
- *
- * DESCRIPTION:
- * This function performs a 32 bit read from PEX configuration space.
- * It supports both type 0 and type 1 of Configuration Transactions
- * (local and over bridge). In order to read from local bus segment, use
- * bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers
- * will result configuration transaction of type 1 (over bridge).
- *
- * INPUT:
- * pex_if - PEX interface number.
- * bus - PEX segment bus number.
- * dev - PEX device number.
- * func - Function number.
- * offss - Register offset.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * 32bit register data, 0xffffffff on error
- *
- */
-u32 pex_cfg_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 offs)
-{
- u32 pex_data = 0;
- u32 local_dev, local_bus;
- u32 val;
-
- if (pex_if >= MV_PEX_MAX_IF)
- return 0xFFFFFFFF;
-
- if (dev >= MAX_PEX_DEVICES) {
- DEBUG_INIT_C("pex_cfg_read: ERR. device number illigal ", dev,
- 1);
- return 0xFFFFFFFF;
- }
-
- if (func >= MAX_PEX_FUNCS) {
- DEBUG_INIT_C("pex_cfg_read: ERR. function num illigal ", func,
- 1);
- return 0xFFFFFFFF;
- }
-
- if (bus >= MAX_PEX_BUSSES) {
- DEBUG_INIT_C("pex_cfg_read: ERR. bus number illigal ", bus, 1);
- return MV_ERROR;
- }
- val = reg_read(PEX_STATUS_REG(pex_if));
-
- local_dev =
- ((val & PXSR_PEX_DEV_NUM_MASK) >> PXSR_PEX_DEV_NUM_OFFS);
- local_bus =
- ((val & PXSR_PEX_BUS_NUM_MASK) >> PXSR_PEX_BUS_NUM_OFFS);
-
- /* Speed up the process. In case on no link, return MV_ERROR */
- if ((dev != local_dev) || (bus != local_bus)) {
- pex_data = reg_read(PEX_STATUS_REG(pex_if));
-
- if ((pex_data & PXSR_DL_DOWN))
- return MV_ERROR;
- }
-
- /*
- * In PCI Express we have only one device number
- * and this number is the first number we encounter else that the
- * local_dev spec pex define return on config read/write on any device
- */
- if (bus == local_bus) {
- if (local_dev == 0) {
- /*
- * If local dev is 0 then the first number we encounter
- * after 0 is 1
- */
- if ((dev != 1) && (dev != local_dev))
- return MV_ERROR;
- } else {
- /*
- * If local dev is not 0 then the first number we
- * encounter is 0
- */
- if ((dev != 0) && (dev != local_dev))
- return MV_ERROR;
- }
- }
-
- /* Creating PEX address to be passed */
- pex_data = (bus << PXCAR_BUS_NUM_OFFS);
- pex_data |= (dev << PXCAR_DEVICE_NUM_OFFS);
- pex_data |= (func << PXCAR_FUNC_NUM_OFFS);
- pex_data |= (offs & PXCAR_REG_NUM_MASK); /* lgacy register space */
- /* extended register space */
- pex_data |= (((offs & PXCAR_REAL_EXT_REG_NUM_MASK) >>
- PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS);
-
- pex_data |= PXCAR_CONFIG_EN;
-
- /* Write the address to the PEX configuration address register */
- reg_write(PEX_CFG_ADDR_REG(pex_if), pex_data);
-
- /*
- * In order to let the PEX controller absorbed the address of the read
- * transaction we perform a validity check that the address was written
- */
- if (pex_data != reg_read(PEX_CFG_ADDR_REG(pex_if)))
- return MV_ERROR;
-
- /* cleaning Master Abort */
- reg_bit_set(PEX_CFG_DIRECT_ACCESS(pex_if, PEX_STATUS_AND_COMMAND),
- PXSAC_MABORT);
- /* Read the Data returned in the PEX Data register */
- pex_data = reg_read(PEX_CFG_DATA_REG(pex_if));
-
- DEBUG_INIT_FULL_C(" --> ", pex_data, 4);
-
- return pex_data;
-}
-
-/*
- * pex_local_bus_num_set - Set PEX interface local bus number.
- *
- * DESCRIPTION:
- * This function sets given PEX interface its local bus number.
- * Note: In case the PEX interface is PEX-X, the information is read-only.
- *
- * INPUT:
- * pex_if - PEX interface number.
- * bus_num - Bus number.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * MV_NOT_ALLOWED in case PEX interface is PEX-X.
- * MV_BAD_PARAM on bad parameters ,
- * otherwise MV_OK
- *
- */
-int pex_local_bus_num_set(u32 pex_if, u32 bus_num)
-{
- u32 val;
-
- if (bus_num >= MAX_PEX_BUSSES) {
- DEBUG_INIT_C("pex_local_bus_num_set: ERR. bus number illigal %d\n",
- bus_num, 4);
- return MV_ERROR;
- }
-
- val = reg_read(PEX_STATUS_REG(pex_if));
- val &= ~PXSR_PEX_BUS_NUM_MASK;
- val |= (bus_num << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), val);
-
- return MV_OK;
-}
-
-/*
- * pex_local_dev_num_set - Set PEX interface local device number.
- *
- * DESCRIPTION:
- * This function sets given PEX interface its local device number.
- * Note: In case the PEX interface is PEX-X, the information is read-only.
- *
- * INPUT:
- * pex_if - PEX interface number.
- * dev_num - Device number.
- *
- * OUTPUT:
- * None.
- *
- * RETURN:
- * MV_NOT_ALLOWED in case PEX interface is PEX-X.
- * MV_BAD_PARAM on bad parameters ,
- * otherwise MV_OK
- *
- */
-int pex_local_dev_num_set(u32 pex_if, u32 dev_num)
-{
- u32 val;
-
- if (pex_if >= MV_PEX_MAX_IF)
- return MV_BAD_PARAM;
-
- val = reg_read(PEX_STATUS_REG(pex_if));
- val &= ~PXSR_PEX_DEV_NUM_MASK;
- val |= (dev_num << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK;
- reg_write(PEX_STATUS_REG(pex_if), val);
-
- return MV_OK;
-}
+++ /dev/null
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/soc.h>
-
-#include "high_speed_env_spec.h"
-
-MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
- /* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
- {
- /* PEX: Change of Slew Rate port0 */
- SERDES_UNIT_PEX, 0x0,
- (0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
- }, {
- /* PEX: Change PLL BW port0 */
- SERDES_UNIT_PEX, 0x0,
- (0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
- }, {
- /* SATA: Slew rate change port 0 */
- SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
- }, {
- /* SATA: Slew rate change port 0 */
- SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
- }, {
- /* SATA: Slew rate change port 0 */
- SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
- }, {
- /* SATA: Slew rate change port 0 */
- SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
- }, {
- /* SGMII: FFE setting Port0 */
- SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
- }, {
- /* SGMII: SELMUP and SELMUF Port0 */
- SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
- }, {
- /* SGMII: Amplitude new setting gen2 Port3 */
- SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
- }, {
- /* QSGMII: Amplitude and slew rate change */
- SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
- }, {
- /* QSGMII: SELMUP and SELMUF */
- SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
- }, {
- /* QSGMII: 0x72e18 */
- SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
- }, {
- /* Null terminated */
- SERDES_UNIT_UNCONNECTED, 0, 0
- }
-};
-
-MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
- /* Z1B */
- {MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Default */
- {MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* PEX module */
- /* Z1A */
- {MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
- {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
- PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
- {MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
- {PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0030, serdes_change_m_phy} /* PEX module - Z1A */
-};
-
-MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
- /* A0 */
- {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
- {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
- {MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
- {MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
- {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
- {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
- {MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
- {PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
-};
-
-MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy}, /* Default */
- {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x00f4, serdes_change_m_phy}, /* Switch module */
-};
-
-MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0010, serdes_change_m_phy}, /* CPU0 */
- {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0010, serdes_change_m_phy} /* CPU1-3 */
-};
-
-MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0010, serdes_change_m_phy}, /* CPU0 */
- {MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0010, serdes_change_m_phy} /* CPU1-3 */
-};
-
-MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
- {MV_PEX_END_POINT, 0x22321111, 0x00000000,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0010, serdes_change_m_phy} /* Default */
-};
-
-MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
- {MV_PEX_END_POINT, 0x23321111, 0x00000000,
- {PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0010, serdes_change_m_phy} /* Default */
-};
-
-MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
- {PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
- 0x0000, serdes_change_m_phy} /* No PEX in FPGA */
-};
-
-MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
- {PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
- 0x0030, serdes_change_m_phy} /* Default */
-};
-
-/*
- * ARMADA-XP CUSTOMER BOARD
- */
-MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x00000030, serdes_change_m_phy}, /* Default */
- {MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x00000030, serdes_change_m_phy}, /* Switch module */
-};
-
-MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
- {MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
- {PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
- 0x0030, serdes_change_m_phy} /* Default */
-};
-
-MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
- db88f78xx0_serdes_cfg,
- rd78460_serdes_cfg,
- db78X60pcac_serdes_cfg,
- fpga88f78xx0_serdes_cfg,
- db88f78xx0rev2_serdes_cfg,
- rd78460nas_serdes_cfg,
- db78X60amc_serdes_cfg,
- db78X60pcacrev2_serdes_cfg,
- rd78460server_rev2_serdes_cfg,
- rd78460AXP_GP_serdes_cfg,
- rd78460customer_serdes_cfg
-};
-
-u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
-u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
+++ /dev/null
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef __HIGHSPEED_ENV_SPEC_H
-#define __HIGHSPEED_ENV_SPEC_H
-
-#include "../../../drivers/ddr/mvebu/ddr3_hw_training.h"
-
-typedef enum {
- SERDES_UNIT_UNCONNECTED = 0x0,
- SERDES_UNIT_PEX = 0x1,
- SERDES_UNIT_SATA = 0x2,
- SERDES_UNIT_SGMII0 = 0x3,
- SERDES_UNIT_SGMII1 = 0x4,
- SERDES_UNIT_SGMII2 = 0x5,
- SERDES_UNIT_SGMII3 = 0x6,
- SERDES_UNIT_QSGMII = 0x7,
- SERDES_UNIT_SETM = 0x8,
- SERDES_LAST_UNIT
-} MV_BIN_SERDES_UNIT_INDX;
-
-
-typedef enum {
- PEX_BUS_DISABLED = 0,
- PEX_BUS_MODE_X1 = 1,
- PEX_BUS_MODE_X4 = 2,
- PEX_BUS_MODE_X8 = 3
-} MV_PEX_UNIT_CFG;
-
-typedef enum pex_type {
- MV_PEX_ROOT_COMPLEX, /* root complex device */
- MV_PEX_END_POINT /* end point device */
-} MV_PEX_TYPE;
-
-typedef struct serdes_change_m_phy {
- MV_BIN_SERDES_UNIT_INDX type;
- u32 reg_low_speed;
- u32 val_low_speed;
- u32 reg_hi_speed;
- u32 val_hi_speed;
-} MV_SERDES_CHANGE_M_PHY;
-
-/*
- * Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
- */
-typedef struct board_serdes_conf {
- MV_PEX_TYPE pex_type; /* MV_PEX_ROOT_COMPLEX MV_PEX_END_POINT */
- u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
- u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
- MV_PEX_UNIT_CFG pex_mode[4];
-
- /*
- * Bus speed - one bit per SERDES line:
- * Low speed (0) High speed (1)
- * PEX 2.5 G (10 bit) 5 G (20 bit)
- * SATA 1.5 G 3 G
- * SGMII 1.25 Gbps 3.125 Gbps
- */
- u32 bus_speed;
-
- MV_SERDES_CHANGE_M_PHY *serdes_m_phy_change;
-} MV_BIN_SERDES_CFG;
-
-
-#define BIN_SERDES_CFG { \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
- {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
- {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
- {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
- {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
- {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
- {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 10 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 11 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 12 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 13 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 14 */ \
- {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 15 */ \
-}
-
-#endif /* __HIGHSPEED_ENV_SPEC_H */
+++ /dev/null
-/*
- * Copyright (C) Marvell International Ltd. and its affiliates
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/soc.h>
-
-#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
-
-/*
- * ARM Timers Registers Map
- */
-#define CNTMR_CTRL_REG &tmr_regs->ctrl
-#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
-#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
-
-/*
- * ARM Timers Control Register
- * CPU_TIMERS_CTRL_REG (CTCR)
- */
-#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
-#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
-
-#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
-#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
-
-/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
-#if defined(CONFIG_ARMADA_XP)
-#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
-#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
-#else
-#define CTCR_ARM_TIMER_25MHZ(cntr) 0
-#endif
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-/* Timer reload and current value registers */
-struct kwtmr_val {
- u32 reload; /* Timer reload reg */
- u32 val; /* Timer value reg */
-};
-
-/* Timer registers */
-struct kwtmr_registers {
- u32 ctrl; /* Timer control reg */
- u32 pad[3];
- struct kwtmr_val tmr[4];
- u32 wdt_reload;
- u32 wdt_val;
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct kwtmr_registers *tmr_regs =
- (struct kwtmr_registers *)MVEBU_TIMER_BASE;
-
-static inline ulong read_timer(void)
-{
- return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec +
- (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- uint current;
- ulong delayticks;
-
- current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
- delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
-
- if (current < delayticks) {
- delayticks -= current;
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
- while ((TIMER_LOAD_VAL - delayticks) <
- readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
- } else {
- while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
- (current - delayticks)) ;
- }
-}
-
-/*
- * init the counter
- */
-int timer_init(void)
-{
- /* load value into timer */
- writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
- writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
-
- /* enable timer in auto reload mode */
- clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
- CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
- CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
-
- /* init the timestamp and lastdec value */
- lastdec = read_timer();
- timestamp = 0;
-
- return 0;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- return (ulong)CONFIG_SYS_HZ;
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
- LENGTH = CONFIG_SPL_MAX_SIZE }
-MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
- LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- .text :
- {
- __start = .;
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- *(.vectors)
- } >.sram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*_i2c_*)));
- } >.sram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
default y
choice
- prompt "Target select"
+ prompt "Mainboard vendor"
+ default VENDOR_COREBOOT
-config TARGET_COREBOOT
- bool "Support coreboot"
- help
- This target is used for running U-Boot on top of Coreboot. In
- this case Coreboot does the early inititalisation, and U-Boot
- takes over once the RAM, video and CPU are fully running.
- U-Boot is loaded as a fallback payload from Coreboot, in
- Coreboot terminology. This method was used for the Chromebook
- Pixel when launched.
-
-config TARGET_CHROMEBOOK_LINK
- bool "Support Chromebook link"
- help
- This is the Chromebook Pixel released in 2013. It uses an Intel
- i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
- SDRAM. It has a Panther Point platform controller hub, PCIe
- WiFi and Bluetooth. It also includes a 720p webcam, USB SD
- reader, microphone and speakers, display port and 32GB SATA
- solid state drive. There is a Chrome OS EC connected on LPC,
- and it provides a 2560x1700 high resolution touch-enabled LCD
- display.
-
-config TARGET_CHROMEBOX_PANTHER
- bool "Support Chromebox panther (not available)"
- select n
- help
- Note: At present this must be used with Coreboot. See README.x86
- for instructions.
-
- This is the Asus Chromebox CN60 released in 2014. It uses an Intel
- Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
- Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
- includes a USB SD reader, four USB3 ports, display port and HDMI
- video output and a 16GB SATA solid state drive. There is no Chrome
- OS EC on this model.
-
-config TARGET_CROWNBAY
- bool "Support Intel Crown Bay CRB"
- help
- This is the Intel Crown Bay Customer Reference Board. It contains
- the Intel Atom Processor E6xx populated on the COM Express module
- with 1GB DDR2 soldered down memory and a carrier board with the
- Intel Platform Controller Hub EG20T, other system components and
- peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
-
-config TARGET_MINNOWMAX
- bool "Support Intel Minnowboard MAX"
- help
- This is the Intel Minnowboard MAX. It contains an Atom E3800
- processor in a small form factor with Ethernet, micro-SD, USB 2,
- USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
- It requires some binary blobs - see README.x86 for details.
+config VENDOR_COREBOOT
+ bool "coreboot"
- Note that PCIE_ECAM_BASE is set up by the FSP so the value used
- by U-Boot matches that value.
+config VENDOR_GOOGLE
+ bool "Google"
-config TARGET_GALILEO
- bool "Support Intel Galileo"
- help
- This is the Intel Galileo board, which is the first in a family of
- Arduino-certified development and prototyping boards based on Intel
- architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
- single-core, single-thread, Intel Pentium processor instrunction set
- architecture (ISA) compatible, operating at speeds up to 400Mhz,
- along with 256MB DDR3 memory. It supports a wide range of industry
- standard I/O interfaces, including a full-sized mini-PCIe slot,
- one 100Mb Ethernet port, a microSD card slot, a USB host port and
- a USB client port.
+config VENDOR_INTEL
+ bool "Intel"
endchoice
-config DM_SPI
- default y
+# board-specific options below
+source "board/coreboot/Kconfig"
+source "board/google/Kconfig"
+source "board/intel/Kconfig"
-config DM_SPI_FLASH
- default y
+# platform-specific options below
+source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/coreboot/Kconfig"
+source "arch/x86/cpu/ivybridge/Kconfig"
+source "arch/x86/cpu/quark/Kconfig"
+source "arch/x86/cpu/queensbay/Kconfig"
+
+# architecture-specific options below
config SYS_MALLOC_F_LEN
default 0x800
detecting obvious failures.
config MARK_GRAPHICS_MEM_WRCOMB
- bool "Mark graphics memory as write-combining."
+ bool "Mark graphics memory as write-combining"
default n
help
- The graphics performance may increase if the graphics
- memory is set as write-combining cache type. This option
- enables marking the graphics memory as write-combining.
+ The graphics performance may increase if the graphics
+ memory is set as write-combining cache type. This option
+ enables marking the graphics memory as write-combining.
menu "Display"
Stack top address which is used in FspInit after DRAM is ready and
CAR is disabled.
-source "arch/x86/cpu/baytrail/Kconfig"
-
-source "arch/x86/cpu/coreboot/Kconfig"
-
-source "arch/x86/cpu/ivybridge/Kconfig"
-
-source "arch/x86/cpu/quark/Kconfig"
+config MAX_CPUS
+ int "Maximum number of CPUs permitted"
+ default 4
+ help
+ When using multi-CPU chips it is possible for U-Boot to start up
+ more than one CPU. The stack memory used by all of these CPUs is
+ pre-allocated so at present U-Boot wants to know the maximum
+ number of CPUs that may be present. Set this to at least as high
+ as the number of CPUs in your system (it uses about 4KB of RAM for
+ each CPU).
+
+config SMP
+ bool "Enable Symmetric Multiprocessing"
+ default n
+ help
+ Enable use of more than one CPU in U-Boot and the Operating System
+ when loaded. Each CPU will be started up and information can be
+ obtained using the 'cpu' command. If this option is disabled, then
+ only one CPU will be enabled regardless of the number of CPUs
+ available.
-source "arch/x86/cpu/queensbay/Kconfig"
+config AP_STACK_SIZE
+ hex
+ default 0x1000
+ help
+ Each additional CPU started by U-Boot requires its own stack. This
+ option sets the stack size used by each CPU and directly affects
+ the memory used by this initialisation process. Typically 4KB is
+ enough space.
config TSC_CALIBRATION_BYPASS
bool "Bypass Time-Stamp Counter (TSC) calibration"
help
The running frequency in MHz of Time-Stamp Counter (TSC).
-source "board/coreboot/coreboot/Kconfig"
+menu "System tables"
-source "board/google/chromebook_link/Kconfig"
+config GENERATE_PIRQ_TABLE
+ bool "Generate a PIRQ table"
+ default n
+ help
+ Generate a PIRQ routing table for this board. The PIRQ routing table
+ is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
+ at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
+ It specifies the interrupt router information as well how all the PCI
+ devices' interrupt pins are wired to PIRQs.
+
+config GENERATE_SFI_TABLE
+ bool "Generate a SFI (Simple Firmware Interface) table"
+ help
+ The Simple Firmware Interface (SFI) provides a lightweight method
+ for platform firmware to pass information to the operating system
+ via static tables in memory. Kernel SFI support is required to
+ boot on SFI-only platforms. If you have ACPI tables then these are
+ used instead.
-source "board/google/chromebox_panther/Kconfig"
+ U-Boot writes this table in write_sfi_table() just before booting
+ the OS.
-source "board/intel/crownbay/Kconfig"
+ For more information, see http://simplefirmware.org
+
+endmenu
-source "board/intel/minnowmax/Kconfig"
+config MAX_PIRQ_LINKS
+ int
+ default 8
+ help
+ This variable specifies the number of PIRQ interrupt links which are
+ routable. On most older chipsets, this is 4, PIRQA through PIRQD.
+ Some newer chipsets offer more than four links, commonly up to PIRQH.
-source "board/intel/galileo/Kconfig"
+config IRQ_SLOT_COUNT
+ int
+ default 128
+ help
+ U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
+ which in turns forms a table of exact 4KiB. The default value 128
+ should be enough for most boards. If this does not fit your board,
+ change it according to your needs.
config PCIE_ECAM_BASE
hex
obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-y += lapic.o
+obj-$(CONFIG_SMP) += mp_init.o
obj-y += mtrr.o
obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_SMP) += sipi_vector.o
obj-y += turbo.o
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += cpu.o
obj-y += early_uart.o
obj-y += fsp_configs.o
obj-y += pci.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on code from coreboot
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <asm/cpu.h>
+#include <asm/lapic.h>
+#include <asm/mp.h>
+#include <asm/msr.h>
+#include <asm/turbo.h>
+
+#ifdef CONFIG_SMP
+static int enable_smis(struct udevice *cpu, void *unused)
+{
+ return 0;
+}
+
+static struct mp_flight_record mp_steps[] = {
+ MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
+ /* Wait for APs to finish initialization before proceeding. */
+ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
+};
+
+static int detect_num_cpus(void)
+{
+ int ecx = 0;
+
+ /*
+ * Use the algorithm described in Intel 64 and IA-32 Architectures
+ * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+ * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+ * of CPUID Extended Topology Leaf.
+ */
+ while (1) {
+ struct cpuid_result leaf_b;
+
+ leaf_b = cpuid_ext(0xb, ecx);
+
+ /*
+ * Bay Trail doesn't have hyperthreading so just determine the
+ * number of cores by from level type (ecx[15:8] == * 2)
+ */
+ if ((leaf_b.ecx & 0xff00) == 0x0200)
+ return leaf_b.ebx & 0xffff;
+ ecx++;
+ }
+}
+
+static int baytrail_init_cpus(void)
+{
+ struct mp_params mp_params;
+
+ lapic_setup();
+
+ mp_params.num_cpus = detect_num_cpus();
+ mp_params.parallel_microcode_load = 0,
+ mp_params.flight_plan = &mp_steps[0];
+ mp_params.num_records = ARRAY_SIZE(mp_steps);
+ mp_params.microcode_pointer = 0;
+
+ if (mp_init(&mp_params)) {
+ printf("Warning: MP init failure\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
+
+int x86_init_cpus(void)
+{
+#ifdef CONFIG_SMP
+ debug("Init additional CPUs\n");
+ baytrail_init_cpus();
+#endif
+
+ return 0;
+}
+
+static void set_max_freq(void)
+{
+ msr_t perf_ctl;
+ msr_t msr;
+
+ /* Enable speed step */
+ msr = msr_read(MSR_IA32_MISC_ENABLES);
+ msr.lo |= (1 << 16);
+ msr_write(MSR_IA32_MISC_ENABLES, msr);
+
+ /*
+ * Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
+ * the PERF_CTL
+ */
+ msr = msr_read(MSR_IACORE_RATIOS);
+ perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+
+ /*
+ * Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
+ * the PERF_CTL
+ */
+ msr = msr_read(MSR_IACORE_VIDS);
+ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+ perf_ctl.hi = 0;
+
+ msr_write(MSR_IA32_PERF_CTL, perf_ctl);
+}
+
+static int cpu_x86_baytrail_probe(struct udevice *dev)
+{
+ debug("Init BayTrail core\n");
+
+ /*
+ * On BayTrail the turbo disable bit is actually scoped at the
+ * building-block level, not package. For non-BSP cores that are
+ * within a building block, enable turbo. The cores within the BSP's
+ * building block will just see it already enabled and move on.
+ */
+ if (lapicid())
+ turbo_enable();
+
+ /* Dynamic L2 shrink enable and threshold */
+ msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f000f, 0xe0008),
+
+ /* Disable C1E */
+ msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
+ msr_setbits_64(MSR_POWER_MISC, 0x44);
+
+ /* Set this core to max frequency ratio */
+ set_max_freq();
+
+ return 0;
+}
+
+static unsigned bus_freq(void)
+{
+ msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+ switch (clk_info.lo & 0x3) {
+ case 0:
+ return 83333333;
+ case 1:
+ return 100000000;
+ case 2:
+ return 133333333;
+ case 3:
+ return 116666666;
+ default:
+ return 0;
+ }
+}
+
+static unsigned long tsc_freq(void)
+{
+ msr_t platform_info;
+ ulong bclk = bus_freq();
+
+ if (!bclk)
+ return 0;
+
+ platform_info = msr_read(MSR_PLATFORM_INFO);
+
+ return bclk * ((platform_info.lo >> 8) & 0xff);
+}
+
+static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ info->cpu_freq = tsc_freq();
+ info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+
+ return 0;
+}
+
+static int cpu_x86_baytrail_bind(struct udevice *dev)
+{
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "intel,apic-id", -1);
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_x86_baytrail_ops = {
+ .get_desc = x86_cpu_get_desc,
+ .get_info = baytrail_get_info,
+};
+
+static const struct udevice_id cpu_x86_baytrail_ids[] = {
+ { .compatible = "intel,baytrail-cpu" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
+ .name = "cpu_x86_baytrail",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_baytrail_ids,
+ .bind = cpu_x86_baytrail_bind,
+ .probe = cpu_x86_baytrail_probe,
+ .ops = &cpu_x86_baytrail_ops,
+};
int cpu_mmc_init(bd_t *bis)
{
- printf("mmc init\n");
return pci_mmc_init("ValleyView SDHCI", mmc_supported,
ARRAY_SIZE(mmc_supported));
}
CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -D__I386__ -Werror
+PLATFORM_CPPFLAGS += -D__I386__
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=0xffff0000
.of_match = pci_x86_ids,
.ops = &pci_x86_ops,
};
+
+static const struct udevice_id generic_pch_ids[] = {
+ { .compatible = "intel,pch" },
+ { }
+};
+
+U_BOOT_DRIVER(generic_pch_drv) = {
+ .name = "pch",
+ .id = UCLASS_PCH,
+ .of_match = generic_pch_ids,
+};
#include <common.h>
#include <command.h>
+#include <cpu.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
+#include <asm/tables.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
void setup_gdt(gd_t *id, u64 *gdt_addr)
{
+ id->arch.gdt = gdt_addr;
/* CS: code, read/execute, 4 GB, base 0 */
gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
asm("wbinvd\n");
}
-void __attribute__ ((regparm(0))) generate_gpf(void);
-
-/* segment 0x70 is an arbitrary segment which does not exist */
-asm(".globl generate_gpf\n"
- ".hidden generate_gpf\n"
- ".type generate_gpf, @function\n"
- "generate_gpf:\n"
- "ljmp $0x70, $0x47114711\n");
-
__weak void reset_cpu(ulong addr)
{
- printf("Resetting using x86 Triple Fault\n");
- set_vector(13, generate_gpf); /* general protection fault handler */
- set_vector(8, generate_gpf); /* double fault handler */
- generate_gpf(); /* start the show */
+ /* Do a hard reset through the chipset's reset control register */
+ outb(SYS_RST | RST_CPU, PORT_RESET);
+ for (;;)
+ cpu_hlt();
+}
+
+void x86_full_reset(void)
+{
+ outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
}
int dcache_status(void)
return ptr;
}
+int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
int default_print_cpuinfo(void)
{
printf("CPU: %s, vendor %s, device %xh\n",
#endif
outb(val, POST_PORT);
}
+
+#ifndef CONFIG_SYS_COREBOOT
+int last_stage_init(void)
+{
+ write_tables();
+
+ return 0;
+}
+#endif
+
+__weak int x86_init_cpus(void)
+{
+ return 0;
+}
+
+int cpu_init_r(void)
+{
+ return x86_init_cpus();
+}
+
+static const struct cpu_ops cpu_x86_ops = {
+ .get_desc = x86_cpu_get_desc,
+};
+
+static const struct udevice_id cpu_x86_ids[] = {
+ { .compatible = "cpu-x86" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_drv) = {
+ .name = "cpu_x86",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_ids,
+ .ops = &cpu_x86_ops,
+};
return 0;
}
+void *x86_get_idt(void)
+{
+ return &idt_ptr;
+}
+
void __do_irq(int irq)
{
printf("Unhandled IRQ : %d\n", irq);
#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <asm/post.h>
+#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/arch/microcode.h>
/* Issue warm reset, will be "CPU only" due to soft reset data */
outb(0x0, PORT_RESET);
- outb(0x6, PORT_RESET);
+ outb(SYS_RST | RST_CPU, PORT_RESET);
cpu_hlt();
/* Not reached */
/* System is not happy after keyboard reset... */
debug("Issuing CF9 warm reset\n");
- outb(0x6, 0xcf9);
- cpu_hlt();
+ reset_cpu(0);
}
/* Early chipset init required before RAM init can work */
int intel_early_me_init_done(u8 status)
{
- u8 reset;
int count;
u32 mebase_l, mebase_h;
struct me_hfs hfs;
/* Check status after acknowledgement */
intel_early_me_status();
- reset = 0;
switch (hfs.ack_data) {
case ME_HFS_ACK_CONTINUE:
/* Continue to boot */
case ME_HFS_ACK_RESET:
/* Non-power cycle reset */
set_global_reset(0);
- reset = 0x06;
+ reset_cpu(0);
break;
case ME_HFS_ACK_PWR_CYCLE:
/* Power cycle reset */
set_global_reset(0);
- reset = 0x0e;
+ x86_full_reset();
break;
case ME_HFS_ACK_GBL_RESET:
/* Global reset */
set_global_reset(1);
- reset = 0x0e;
+ x86_full_reset();
break;
case ME_HFS_ACK_S3:
case ME_HFS_ACK_S4:
break;
}
- /* Perform the requested reset */
- if (reset) {
- outb(reset, 0xcf9);
- cpu_hlt();
- }
return -1;
}
debug("CPU: %u has core %u\n", cpu->apic_id, new_cpu->apic_id);
-#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
- /* Start the new cpu */
+#if 0 && CONFIG_SMP && CONFIG_MAX_CPUS > 1
+ /* TODO(sjg@chromium.org): Start the new cpu */
if (!start_cpu(new_cpu)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
/* If MRC data is not found we cannot continue S3 resume. */
if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
debug("Giving up in sdram_initialize: No MRC data\n");
- outb(0x6, PORT_RESET);
- cpu_hlt();
+ reset_cpu(0);
}
/* Pass console handler in pei_data */
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Based on code from the coreboot file of the same name
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/atomic.h>
+#include <asm/cpu.h>
+#include <asm/interrupt.h>
+#include <asm/lapic.h>
+#include <asm/mp.h>
+#include <asm/mtrr.h>
+#include <asm/sipi.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <linux/linkage.h>
+
+/* This also needs to match the sipi.S assembly code for saved MSR encoding */
+struct saved_msr {
+ uint32_t index;
+ uint32_t lo;
+ uint32_t hi;
+} __packed;
+
+
+struct mp_flight_plan {
+ int num_records;
+ struct mp_flight_record *records;
+};
+
+static struct mp_flight_plan mp_info;
+
+struct cpu_map {
+ struct udevice *dev;
+ int apic_id;
+ int err_code;
+};
+
+static inline void barrier_wait(atomic_t *b)
+{
+ while (atomic_read(b) == 0)
+ asm("pause");
+ mfence();
+}
+
+static inline void release_barrier(atomic_t *b)
+{
+ mfence();
+ atomic_set(b, 1);
+}
+
+/* Returns 1 if timeout waiting for APs. 0 if target APs found */
+static int wait_for_aps(atomic_t *val, int target, int total_delay,
+ int delay_step)
+{
+ int timeout = 0;
+ int delayed = 0;
+
+ while (atomic_read(val) != target) {
+ udelay(delay_step);
+ delayed += delay_step;
+ if (delayed >= total_delay) {
+ timeout = 1;
+ break;
+ }
+ }
+
+ return timeout;
+}
+
+static void ap_do_flight_plan(struct udevice *cpu)
+{
+ int i;
+
+ for (i = 0; i < mp_info.num_records; i++) {
+ struct mp_flight_record *rec = &mp_info.records[i];
+
+ atomic_inc(&rec->cpus_entered);
+ barrier_wait(&rec->barrier);
+
+ if (rec->ap_call != NULL)
+ rec->ap_call(cpu, rec->ap_arg);
+ }
+}
+
+static int find_cpu_by_apid_id(int apic_id, struct udevice **devp)
+{
+ struct udevice *dev;
+
+ *devp = NULL;
+ for (uclass_find_first_device(UCLASS_CPU, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ if (plat->cpu_id == apic_id) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+/*
+ * By the time APs call ap_init() caching has been setup, and microcode has
+ * been loaded
+ */
+static void ap_init(unsigned int cpu_index)
+{
+ struct udevice *dev;
+ int apic_id;
+ int ret;
+
+ /* Ensure the local apic is enabled */
+ enable_lapic();
+
+ apic_id = lapicid();
+ ret = find_cpu_by_apid_id(apic_id, &dev);
+ if (ret) {
+ debug("Unknown CPU apic_id %x\n", apic_id);
+ goto done;
+ }
+
+ debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id,
+ dev ? dev->name : "(apic_id not found)");
+
+ /* Walk the flight plan */
+ ap_do_flight_plan(dev);
+
+ /* Park the AP */
+ debug("parking\n");
+done:
+ stop_this_cpu();
+}
+
+static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = {
+ MTRR_FIX_64K_00000_MSR, MTRR_FIX_16K_80000_MSR, MTRR_FIX_16K_A0000_MSR,
+ MTRR_FIX_4K_C0000_MSR, MTRR_FIX_4K_C8000_MSR, MTRR_FIX_4K_D0000_MSR,
+ MTRR_FIX_4K_D8000_MSR, MTRR_FIX_4K_E0000_MSR, MTRR_FIX_4K_E8000_MSR,
+ MTRR_FIX_4K_F0000_MSR, MTRR_FIX_4K_F8000_MSR,
+};
+
+static inline struct saved_msr *save_msr(int index, struct saved_msr *entry)
+{
+ msr_t msr;
+
+ msr = msr_read(index);
+ entry->index = index;
+ entry->lo = msr.lo;
+ entry->hi = msr.hi;
+
+ /* Return the next entry */
+ entry++;
+ return entry;
+}
+
+static int save_bsp_msrs(char *start, int size)
+{
+ int msr_count;
+ int num_var_mtrrs;
+ struct saved_msr *msr_entry;
+ int i;
+ msr_t msr;
+
+ /* Determine number of MTRRs need to be saved */
+ msr = msr_read(MTRR_CAP_MSR);
+ num_var_mtrrs = msr.lo & 0xff;
+
+ /* 2 * num_var_mtrrs for base and mask. +1 for IA32_MTRR_DEF_TYPE */
+ msr_count = 2 * num_var_mtrrs + NUM_FIXED_MTRRS + 1;
+
+ if ((msr_count * sizeof(struct saved_msr)) > size) {
+ printf("Cannot mirror all %d msrs.\n", msr_count);
+ return -ENOSPC;
+ }
+
+ msr_entry = (void *)start;
+ for (i = 0; i < NUM_FIXED_MTRRS; i++)
+ msr_entry = save_msr(fixed_mtrrs[i], msr_entry);
+
+ for (i = 0; i < num_var_mtrrs; i++) {
+ msr_entry = save_msr(MTRR_PHYS_BASE_MSR(i), msr_entry);
+ msr_entry = save_msr(MTRR_PHYS_MASK_MSR(i), msr_entry);
+ }
+
+ msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
+
+ return msr_count;
+}
+
+static int load_sipi_vector(atomic_t **ap_countp)
+{
+ struct sipi_params_16bit *params16;
+ struct sipi_params *params;
+ static char msr_save[512];
+ char *stack;
+ ulong addr;
+ int code_len;
+ int size;
+ int ret;
+
+ /* Copy in the code */
+ code_len = ap_start16_code_end - ap_start16;
+ debug("Copying SIPI code to %x: %d bytes\n", AP_DEFAULT_BASE,
+ code_len);
+ memcpy((void *)AP_DEFAULT_BASE, ap_start16, code_len);
+
+ addr = AP_DEFAULT_BASE + (ulong)sipi_params_16bit - (ulong)ap_start16;
+ params16 = (struct sipi_params_16bit *)addr;
+ params16->ap_start = (uint32_t)ap_start;
+ params16->gdt = (uint32_t)gd->arch.gdt;
+ params16->gdt_limit = X86_GDT_SIZE - 1;
+ debug("gdt = %x, gdt_limit = %x\n", params16->gdt, params16->gdt_limit);
+
+ params = (struct sipi_params *)sipi_params;
+ debug("SIPI 32-bit params at %p\n", params);
+ params->idt_ptr = (uint32_t)x86_get_idt();
+
+ params->stack_size = CONFIG_AP_STACK_SIZE;
+ size = params->stack_size * CONFIG_MAX_CPUS;
+ stack = memalign(size, 4096);
+ if (!stack)
+ return -ENOMEM;
+ params->stack_top = (u32)(stack + size);
+
+ params->microcode_ptr = 0;
+ params->msr_table_ptr = (u32)msr_save;
+ ret = save_bsp_msrs(msr_save, sizeof(msr_save));
+ if (ret < 0)
+ return ret;
+ params->msr_count = ret;
+
+ params->c_handler = (uint32_t)&ap_init;
+
+ *ap_countp = ¶ms->ap_count;
+ atomic_set(*ap_countp, 0);
+ debug("SIPI vector is ready\n");
+
+ return 0;
+}
+
+static int check_cpu_devices(int expected_cpus)
+{
+ int i;
+
+ for (i = 0; i < expected_cpus; i++) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_find_device(UCLASS_CPU, i, &dev);
+ if (ret) {
+ debug("Cannot find CPU %d in device tree\n", i);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+/* Returns 1 for timeout. 0 on success */
+static int apic_wait_timeout(int total_delay, int delay_step)
+{
+ int total = 0;
+ int timeout = 0;
+
+ while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY) {
+ udelay(delay_step);
+ total += delay_step;
+ if (total >= total_delay) {
+ timeout = 1;
+ break;
+ }
+ }
+
+ return timeout;
+}
+
+static int start_aps(int ap_count, atomic_t *num_aps)
+{
+ int sipi_vector;
+ /* Max location is 4KiB below 1MiB */
+ const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;
+
+ if (ap_count == 0)
+ return 0;
+
+ /* The vector is sent as a 4k aligned address in one byte */
+ sipi_vector = AP_DEFAULT_BASE >> 12;
+
+ if (sipi_vector > max_vector_loc) {
+ printf("SIPI vector too large! 0x%08x\n",
+ sipi_vector);
+ return -1;
+ }
+
+ debug("Attempting to start %d APs\n", ap_count);
+
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ debug("Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000, 50)) {
+ debug("timed out. Aborting.\n");
+ return -1;
+ } else {
+ debug("done.\n");
+ }
+ }
+
+ /* Send INIT IPI to all but self */
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
+ lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
+ LAPIC_DM_INIT);
+ debug("Waiting for 10ms after sending INIT.\n");
+ mdelay(10);
+
+ /* Send 1st SIPI */
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ debug("Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000, 50)) {
+ debug("timed out. Aborting.\n");
+ return -1;
+ } else {
+ debug("done.\n");
+ }
+ }
+
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
+ lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
+ LAPIC_DM_STARTUP | sipi_vector);
+ debug("Waiting for 1st SIPI to complete...");
+ if (apic_wait_timeout(10000, 50)) {
+ debug("timed out.\n");
+ return -1;
+ } else {
+ debug("done.\n");
+ }
+
+ /* Wait for CPUs to check in up to 200 us */
+ wait_for_aps(num_aps, ap_count, 200, 15);
+
+ /* Send 2nd SIPI */
+ if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) {
+ debug("Waiting for ICR not to be busy...");
+ if (apic_wait_timeout(1000, 50)) {
+ debug("timed out. Aborting.\n");
+ return -1;
+ } else {
+ debug("done.\n");
+ }
+ }
+
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(0));
+ lapic_write_around(LAPIC_ICR, LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT |
+ LAPIC_DM_STARTUP | sipi_vector);
+ debug("Waiting for 2nd SIPI to complete...");
+ if (apic_wait_timeout(10000, 50)) {
+ debug("timed out.\n");
+ return -1;
+ } else {
+ debug("done.\n");
+ }
+
+ /* Wait for CPUs to check in */
+ if (wait_for_aps(num_aps, ap_count, 10000, 50)) {
+ debug("Not all APs checked in: %d/%d.\n",
+ atomic_read(num_aps), ap_count);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
+{
+ int i;
+ int ret = 0;
+ const int timeout_us = 100000;
+ const int step_us = 100;
+ int num_aps = mp_params->num_cpus - 1;
+
+ for (i = 0; i < mp_params->num_records; i++) {
+ struct mp_flight_record *rec = &mp_params->flight_plan[i];
+
+ /* Wait for APs if the record is not released */
+ if (atomic_read(&rec->barrier) == 0) {
+ /* Wait for the APs to check in */
+ if (wait_for_aps(&rec->cpus_entered, num_aps,
+ timeout_us, step_us)) {
+ debug("MP record %d timeout.\n", i);
+ ret = -1;
+ }
+ }
+
+ if (rec->bsp_call != NULL)
+ rec->bsp_call(cpu, rec->bsp_arg);
+
+ release_barrier(&rec->barrier);
+ }
+ return ret;
+}
+
+static int init_bsp(struct udevice **devp)
+{
+ char processor_name[CPU_MAX_NAME_LEN];
+ int apic_id;
+ int ret;
+
+ cpu_get_name(processor_name);
+ debug("CPU: %s.\n", processor_name);
+
+ enable_lapic();
+
+ apic_id = lapicid();
+ ret = find_cpu_by_apid_id(apic_id, devp);
+ if (ret) {
+ printf("Cannot find boot CPU, APIC ID %d\n", apic_id);
+ return ret;
+ }
+
+ return 0;
+}
+
+int mp_init(struct mp_params *p)
+{
+ int num_aps;
+ atomic_t *ap_count;
+ struct udevice *cpu;
+ int ret;
+
+ /* This will cause the CPUs devices to be bound */
+ struct uclass *uc;
+ ret = uclass_get(UCLASS_CPU, &uc);
+ if (ret)
+ return ret;
+
+ ret = init_bsp(&cpu);
+ if (ret) {
+ debug("Cannot init boot CPU: err=%d\n", ret);
+ return ret;
+ }
+
+ if (p == NULL || p->flight_plan == NULL || p->num_records < 1) {
+ printf("Invalid MP parameters\n");
+ return -1;
+ }
+
+ ret = check_cpu_devices(p->num_cpus);
+ if (ret)
+ debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
+
+ /* Copy needed parameters so that APs have a reference to the plan */
+ mp_info.num_records = p->num_records;
+ mp_info.records = p->flight_plan;
+
+ /* Load the SIPI vector */
+ ret = load_sipi_vector(&ap_count);
+ if (ap_count == NULL)
+ return -1;
+
+ /*
+ * Make sure SIPI data hits RAM so the APs that come up will see
+ * the startup code even if the caches are disabled
+ */
+ wbinvd();
+
+ /* Start the APs providing number of APs and the cpus_entered field */
+ num_aps = p->num_cpus - 1;
+ ret = start_aps(num_aps, ap_count);
+ if (ret) {
+ mdelay(1000);
+ debug("%d/%d eventually checked in?\n", atomic_read(ap_count),
+ num_aps);
+ return ret;
+ }
+
+ /* Walk the flight plan for the BSP */
+ ret = bsp_do_flight_plan(cpu, p);
+ if (ret) {
+ debug("CPU init failed: err=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+int mp_init_cpu(struct udevice *cpu, void *unused)
+{
+ return device_probe(cpu);
+}
return 0;
}
+
+void pci_assign_irqs(int bus, int device, int func, u8 irq[4])
+{
+ pci_dev_t bdf;
+ u8 pin, line;
+
+ bdf = PCI_BDF(bus, device, func);
+
+ pin = x86_pci_read_config8(bdf, PCI_INTERRUPT_PIN);
+
+ /* PCI spec says all values except 1..4 are reserved */
+ if ((pin < 1) || (pin > 4))
+ return;
+
+ line = irq[pin - 1];
+
+ debug("Assigning IRQ %d to PCI device %d.%x.%d (INT%c)\n",
+ line, bus, device, func, 'A' + pin - 1);
+
+ x86_pci_write_config8(bdf, PCI_INTERRUPT_LINE, line);
+}
CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
}
+static void quark_enable_legacy_seg(void)
+{
+ u32 hmisc2;
+
+ hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
+ hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
+}
+
int arch_cpu_init(void)
{
struct pci_controller *hose;
*/
quark_setup_bars();
+ /* Turn on legacy segments (A/B/E/F) decode to system RAM */
+ quark_enable_legacy_seg();
+
unprotect_spi_flash();
return 0;
void reset_cpu(ulong addr)
{
/* cold reset */
- outb(0x08, PORT_RESET);
+ x86_full_reset();
}
int cpu_mmc_init(bd_t *bis)
#
obj-y += fsp_configs.o
-obj-y += tnc.o topcliff.o
+obj-y += irq.o tnc.o topcliff.o
obj-$(CONFIG_PCI) += tnc_pci.o
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/post.h>
+#include <asm/processor.h>
+#include <asm/pirq_routing.h>
+#include <asm/arch/device.h>
+#include <asm/arch/tnc.h>
+#include <asm/arch/irq.h>
+
+static struct irq_routing_table *pirq_routing_table;
+
+bool pirq_check_irq_routed(int link, u8 irq)
+{
+ u8 pirq;
+
+ pirq = x86_pci_read_config8(TNC_LPC, LINK_N2V(link));
+ pirq &= 0xf;
+
+ /* IRQ# 0/1/2/8/13 are reserved */
+ if (pirq < 3 || pirq == 8 || pirq == 13)
+ return false;
+
+ return pirq == irq ? true : false;
+}
+
+int pirq_translate_link(int link)
+{
+ return LINK_V2N(link);
+}
+
+void pirq_assign_irq(int link, u8 irq)
+{
+ /* IRQ# 0/1/2/8/13 are reserved */
+ if (irq < 3 || irq == 8 || irq == 13)
+ return;
+
+ x86_pci_write_config8(TNC_LPC, LINK_N2V(link), irq);
+}
+
+static inline void fill_irq_info(struct irq_info **slotp, int *entries, u8 bus,
+ u8 device, u8 func, u8 pin, u8 pirq)
+{
+ struct irq_info *slot = *slotp;
+
+ slot->bus = bus;
+ slot->devfn = (device << 3) | func;
+ slot->irq[pin - 1].link = LINK_N2V(pirq);
+ slot->irq[pin - 1].bitmap = PIRQ_BITMAP;
+ (*entries)++;
+ (*slotp)++;
+}
+
+/* PCIe port downstream INTx swizzle */
+static inline u8 pin_swizzle(u8 pin, int port)
+{
+ return (pin + port) % 4;
+}
+
+__weak int board_fill_irq_info(struct irq_info *slot)
+{
+ return 0;
+}
+
+static int create_pirq_routing_table(void)
+{
+ struct irq_routing_table *rt;
+ struct irq_info *slot;
+ int irq_entries = 0;
+ pci_dev_t tcf_bdf;
+ u8 tcf_bus, bus;
+ int i;
+
+ rt = malloc(sizeof(struct irq_routing_table));
+ if (!rt)
+ return -ENOMEM;
+ memset((char *)rt, 0, sizeof(struct irq_routing_table));
+
+ /* Populate the PIRQ table fields */
+ rt->signature = PIRQ_SIGNATURE;
+ rt->version = PIRQ_VERSION;
+ rt->rtr_bus = 0;
+ rt->rtr_devfn = (TNC_LPC_DEV << 3) | TNC_LPC_FUNC;
+ rt->rtr_vendor = PCI_VENDOR_ID_INTEL;
+ rt->rtr_device = PCI_DEVICE_ID_INTEL_ICH7_31;
+
+ slot = rt->slots;
+
+ /*
+ * Now fill in the irq_info entries in the PIRQ table
+ *
+ * We start from internal TunnelCreek PCI devices first, then
+ * followed by all the 4 PCIe ports downstream devices, including
+ * the Queensbay platform Topcliff chipset devices.
+ */
+ fill_irq_info(&slot, &irq_entries, 0, TNC_IGD_DEV,
+ TNC_IGD_FUNC, INTA, PIRQE);
+ fill_irq_info(&slot, &irq_entries, 0, TNC_SDVO_DEV,
+ TNC_SDVO_FUNC, INTA, PIRQF);
+ fill_irq_info(&slot, &irq_entries, 0, TNC_HDA_DEV,
+ TNC_HDA_FUNC, INTA, PIRQG);
+ fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE0_DEV,
+ TNC_PCIE0_FUNC, INTA, PIRQE);
+ fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE1_DEV,
+ TNC_PCIE1_FUNC, INTA, PIRQF);
+ fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE2_DEV,
+ TNC_PCIE2_FUNC, INTA, PIRQG);
+ fill_irq_info(&slot, &irq_entries, 0, TNC_PCIE3_DEV,
+ TNC_PCIE3_FUNC, INTA, PIRQH);
+
+ /* Check which PCIe port the Topcliff chipset is connected to */
+ tcf_bdf = pci_find_device(PCI_VENDOR_ID_INTEL, 0x8800, 0);
+ tcf_bus = PCI_BUS(tcf_bdf);
+ for (i = 0; i < 4; i++) {
+ bus = x86_pci_read_config8(PCI_BDF(0, TNC_PCIE0_DEV + i, 0),
+ PCI_SECONDARY_BUS);
+ if (bus == tcf_bus)
+ break;
+ }
+
+ /* Fill in the Topcliff chipset devices' irq info */
+ if (i < 4) {
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_PCIE_PORT_DEV,
+ TCF_PCIE_PORT_FUNC, INTA, pin_swizzle(PIRQA, i));
+
+ tcf_bus++;
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
+ TCF_GBE_FUNC, INTA, pin_swizzle(PIRQA, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_0,
+ TCF_GPIO_FUNC, INTA, pin_swizzle(PIRQA, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
+ TCF_USB1_OHCI0_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
+ TCF_USB1_OHCI1_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
+ TCF_USB1_OHCI2_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
+ TCF_USB1_EHCI_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_2,
+ TCF_USB_DEVICE_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
+ TCF_SDIO0_FUNC, INTC, pin_swizzle(PIRQC, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_4,
+ TCF_SDIO1_FUNC, INTC, pin_swizzle(PIRQC, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_6,
+ TCF_SATA_FUNC, INTD, pin_swizzle(PIRQD, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
+ TCF_USB2_OHCI0_FUNC, INTA, pin_swizzle(PIRQA, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
+ TCF_USB2_OHCI1_FUNC, INTA, pin_swizzle(PIRQA, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
+ TCF_USB2_OHCI2_FUNC, INTA, pin_swizzle(PIRQA, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_8,
+ TCF_USB2_EHCI_FUNC, INTA, pin_swizzle(PIRQA, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
+ TCF_DMA1_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
+ TCF_UART0_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
+ TCF_UART1_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
+ TCF_UART2_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_10,
+ TCF_UART3_FUNC, INTB, pin_swizzle(PIRQB, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
+ TCF_DMA2_FUNC, INTC, pin_swizzle(PIRQC, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
+ TCF_SPI_FUNC, INTC, pin_swizzle(PIRQC, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
+ TCF_I2C_FUNC, INTC, pin_swizzle(PIRQC, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
+ TCF_CAN_FUNC, INTC, pin_swizzle(PIRQC, i));
+ fill_irq_info(&slot, &irq_entries, tcf_bus, TCF_DEV_12,
+ TCF_1588_FUNC, INTC, pin_swizzle(PIRQC, i));
+ }
+
+ /* Call board-specific routine to fill in add-in card's irq info */
+ irq_entries += board_fill_irq_info(slot);
+
+ rt->size = irq_entries * sizeof(struct irq_info) + 32;
+
+ pirq_routing_table = rt;
+
+ return 0;
+}
+
+void pirq_init(void)
+{
+ struct tnc_rcba *rcba;
+ u32 base;
+
+ base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct tnc_rcba *)base;
+
+ /* Make sure all internal PCI devices are using INTA */
+ writel(INTA, &rcba->d02ip);
+ writel(INTA, &rcba->d03ip);
+ writel(INTA, &rcba->d27ip);
+ writel(INTA, &rcba->d31ip);
+ writel(INTA, &rcba->d23ip);
+ writel(INTA, &rcba->d24ip);
+ writel(INTA, &rcba->d25ip);
+ writel(INTA, &rcba->d26ip);
+
+ /*
+ * Route TunnelCreek PCI device interrupt pin to PIRQ
+ *
+ * Since PCIe downstream ports received INTx are routed to PIRQ
+ * A/B/C/D directly and not configurable, we route internal PCI
+ * device's INTx to PIRQ E/F/G/H.
+ */
+ writew(PIRQE, &rcba->d02ir);
+ writew(PIRQF, &rcba->d03ir);
+ writew(PIRQG, &rcba->d27ir);
+ writew(PIRQH, &rcba->d31ir);
+ writew(PIRQE, &rcba->d23ir);
+ writew(PIRQF, &rcba->d24ir);
+ writew(PIRQG, &rcba->d25ir);
+ writew(PIRQH, &rcba->d26ir);
+
+ if (create_pirq_routing_table()) {
+ debug("Failed to create pirq routing table\n");
+ } else {
+ /* Route PIRQ */
+ pirq_route_irqs(pirq_routing_table->slots,
+ get_irq_slot_count(pirq_routing_table));
+ }
+}
+
+u32 write_pirq_routing_table(u32 addr)
+{
+ return copy_pirq_routing_table(addr, pirq_routing_table);
+}
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
-#include <asm/arch/tnc.h>
+#include <asm/arch/device.h>
+#include <asm/arch/irq.h>
#include <asm/fsp/fsp_support.h>
#include <asm/processor.h>
{
u32 bc;
- bc = x86_pci_read_config32(PCH_LPC_DEV, 0xd8);
+ bc = x86_pci_read_config32(TNC_LPC, 0xd8);
bc |= 0x1; /* unprotect the flash */
- x86_pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+ x86_pci_write_config32(TNC_LPC, 0xd8, bc);
}
int arch_cpu_init(void)
return 0;
}
+
+int arch_misc_init(void)
+{
+ pirq_init();
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Taken from coreboot file of the same name
+ */
+
+/*
+ * The SIPI vector is responsible for initializing the APs in the sytem. It
+ * loads microcode, sets up MSRs, and enables caching before calling into
+ * C code
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
+#include <asm/sipi.h>
+
+#define CODE_SEG (X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE)
+#define DATA_SEG (X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE)
+
+/*
+ * First we have the 16-bit section. Every AP process starts here.
+ * The simple task is to load U-Boot's Global Descriptor Table (GDT) to allow
+ * U-Boot's 32-bit code to become visible, then jump to ap_start.
+ *
+ * Note that this code is copied to RAM below 1MB in mp_init.c, and runs from
+ * there, but the 32-bit code (ap_start and onwards) is part of U-Boot and
+ * is therefore relocated to the top of RAM with other U-Boot code. This
+ * means that for the 16-bit code we must write relocatable code, but for the
+ * rest, we can do what we like.
+ */
+.text
+.code16
+.globl ap_start16
+ap_start16:
+ cli
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB */
+
+ /* setup the data segment */
+ movw %cs, %ax
+ movw %ax, %ds
+
+ /* Use an address relative to the data segment for the GDT */
+ movl $gdtaddr, %ebx
+ subl $ap_start16, %ebx
+
+ data32 lgdt (%ebx)
+
+ movl %cr0, %eax
+ andl $(~(X86_CR0_PG | X86_CR0_AM | X86_CR0_WP | X86_CR0_NE | \
+ X86_CR0_TS | X86_CR0_EM | X86_CR0_MP)), %eax
+ orl $(X86_CR0_NW | X86_CR0_CD | X86_CR0_PE), %eax
+ movl %eax, %cr0
+
+ movl $ap_start_jmp, %eax
+ subl $ap_start16, %eax
+ movw %ax, %bp
+
+ /* Jump to ap_start within U-Boot */
+data32 cs ljmp *(%bp)
+
+ .align 4
+.globl sipi_params_16bit
+sipi_params_16bit:
+ /* 48-bit far pointer */
+ap_start_jmp:
+ .long 0 /* offset set to ap_start by U-Boot */
+ .word CODE_SEG /* segment */
+
+ .word 0 /* padding */
+gdtaddr:
+ .word 0 /* limit */
+ .long 0 /* table */
+ .word 0 /* unused */
+
+.globl ap_start16_code_end
+ap_start16_code_end:
+
+/*
+ * Set up the special 'fs' segment for global_data. Then jump to ap_continue
+ * to set up the AP.
+ */
+.globl ap_start
+ap_start:
+ .code32
+ movw $DATA_SEG, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %gs
+
+ movw $(X86_GDT_ENTRY_32BIT_FS * X86_GDT_ENTRY_SIZE), %ax
+ movw %ax, %fs
+
+ /* Load the Interrupt descriptor table */
+ mov idt_ptr, %ebx
+ lidt (%ebx)
+
+ /* Obtain cpu number */
+ movl ap_count, %eax
+1:
+ movl %eax, %ecx
+ inc %ecx
+ lock cmpxchg %ecx, ap_count
+ jnz 1b
+
+ /* Setup stacks for each CPU */
+ movl stack_size, %eax
+ mul %ecx
+ movl stack_top, %edx
+ subl %eax, %edx
+ mov %edx, %esp
+ /* Save cpu number */
+ mov %ecx, %esi
+
+ /* Determine if one should check microcode versions */
+ mov microcode_ptr, %edi
+ test %edi, %edi
+ jz microcode_done /* Bypass if no microde exists */
+
+ /* Get the Microcode version */
+ mov $1, %eax
+ cpuid
+ mov $MSR_IA32_UCODE_REV, %ecx
+ rdmsr
+ /* If something already loaded skip loading again */
+ test %edx, %edx
+ jnz microcode_done
+
+ /* Determine if parallel microcode loading is allowed */
+ cmp $0xffffffff, microcode_lock
+ je load_microcode
+
+ /* Protect microcode loading */
+lock_microcode:
+ lock bts $0, microcode_lock
+ jc lock_microcode
+
+load_microcode:
+ /* Load new microcode */
+ mov $MSR_IA32_UCODE_WRITE, %ecx
+ xor %edx, %edx
+ mov %edi, %eax
+ /*
+ * The microcode pointer is passed in pointing to the header. Adjust
+ * pointer to reflect the payload (header size is 48 bytes)
+ */
+ add $UCODE_HEADER_LEN, %eax
+ pusha
+ wrmsr
+ popa
+
+ /* Unconditionally unlock microcode loading */
+ cmp $0xffffffff, microcode_lock
+ je microcode_done
+
+ xor %eax, %eax
+ mov %eax, microcode_lock
+
+microcode_done:
+ /*
+ * Load MSRs. Each entry in the table consists of:
+ * 0: index,
+ * 4: value[31:0]
+ * 8: value[63:32]
+ * See struct saved_msr in mp_init.c.
+ */
+ mov msr_table_ptr, %edi
+ mov msr_count, %ebx
+ test %ebx, %ebx
+ jz 1f
+load_msr:
+ mov (%edi), %ecx
+ mov 4(%edi), %eax
+ mov 8(%edi), %edx
+ wrmsr
+ add $12, %edi
+ dec %ebx
+ jnz load_msr
+
+1:
+ /* Enable caching */
+ mov %cr0, %eax
+ andl $(~(X86_CR0_CD | X86_CR0_NW)), %eax
+ mov %eax, %cr0
+
+ /* c_handler(cpu_num) */
+ movl %esi, %eax /* cpu_num */
+ mov c_handler, %eax
+ call *%eax
+
+ .align 4
+.globl sipi_params
+sipi_params:
+idt_ptr:
+ .long 0
+stack_top:
+ .long 0
+stack_size:
+ .long 0
+microcode_lock:
+ .long 0
+microcode_ptr:
+ .long 0
+msr_table_ptr:
+ .long 0
+msr_count:
+ .long 0
+c_handler:
+ .long 0
+ap_count:
+ .long 0
pch {
reg = <0x0000f800 0 0 0 0>;
- compatible = "intel,bd82x6x";
+ compatible = "intel,bd82x6x", "intel,pch";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
model = "Intel Crown Bay";
compatible = "intel,crownbay", "intel,queensbay";
+ aliases {
+ spi0 = "/spi";
+ };
+
config {
silent_console = <0>;
};
spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich7";
+ compatible = "intel,ich-spi";
spi-flash@0 {
reg = <0>;
compatible = "sst,25vf016b", "spi-flash";
model = "Intel Galileo";
compatible = "intel,galileo", "intel,quark";
+ aliases {
+ spi0 = "/spi";
+ };
+
config {
silent_console = <0>;
};
aliases {
serial0 = &serial;
+ spi0 = "/spi";
};
config {
silent_console = <0>;
};
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x20>;
+ bank-name = "C";
+ };
+
+ gpiod {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x60 0x20>;
+ bank-name = "D";
+ };
+
+ gpioe {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x80 0x20>;
+ bank-name = "E";
+ };
+
+ gpiof {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0xA0 0x20>;
+ bank-name = "F";
+ };
+
chosen {
stdout-path = "/serial";
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "intel,baytrail-cpu";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "intel,baytrail-cpu";
+ reg = <1>;
+ intel,apic-id = <4>;
+ };
+
+ };
+
spi {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "intel,ich";
+ compatible = "intel,ich-spi";
spi-flash@0 {
reg = <0>;
- compatible = "sst,25vf016b", "spi-flash";
+ compatible = "stmicro,n25q064a", "spi-flash";
memory-map = <0xff800000 0x00800000>;
};
};
#define _X86_ARCH_GPIO_H_
/* Where in config space is the register that points to the GPIO registers? */
-#define PCI_CFG_GPIOBASE 0x44
+#define PCI_CFG_GPIOBASE 0x48
#endif /* _X86_ARCH_GPIO_H_ */
#ifndef __ASM_ARCH_MICROCODE_H
#define __ASM_ARCH_MICROCODE_H
-/* Length of the public header on Intel microcode blobs */
-#define UCODE_HEADER_LEN 0x30
-
#ifndef __ASSEMBLY__
/**
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
-#define MSR_POWER_CTL 0x1fc
#define MSR_PKGC3_IRTL 0x60a
#define MSR_PKGC6_IRTL 0x60b
#define MSR_PP1_CURRENT_CONFIG 0x602
#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
-#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_SKU 0x614
#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
/* Port 0x03: Host Bridge Message Port Registers */
+/* Host Miscellaneous Controls 2 */
+#define HMISC2 0x03
+
+#define HMISC2_SEGE 0x00000002
+#define HMISC2_SEGF 0x00000004
+#define HMISC2_SEGAB 0x00000010
+
/* Host Memory I/O Boundary */
#define HM_BOUND 0x08
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _QUEENSBAY_DEVICE_H_
+#define _QUEENSBAY_DEVICE_H_
+
+#include <pci.h>
+
+/* TunnelCreek PCI Devices */
+#define TNC_HOST_BRIDGE_DEV 0
+#define TNC_HOST_BRIDGE_FUNC 0
+#define TNC_IGD_DEV 2
+#define TNC_IGD_FUNC 0
+#define TNC_SDVO_DEV 3
+#define TNC_SDVO_FUNC 0
+#define TNC_PCIE0_DEV 23
+#define TNC_PCIE0_FUNC 0
+#define TNC_PCIE1_DEV 24
+#define TNC_PCIE1_FUNC 0
+#define TNC_PCIE2_DEV 25
+#define TNC_PCIE2_FUNC 0
+#define TNC_PCIE3_DEV 26
+#define TNC_PCIE3_FUNC 0
+#define TNC_HDA_DEV 27
+#define TNC_HDA_FUNC 0
+#define TNC_LPC_DEV 31
+#define TNC_LPC_FUNC 0
+
+#define TNC_HOST_BRIDGE \
+ PCI_BDF(0, TNC_HOST_BRIDGE_DEV, TNC_HOST_BRIDGE_FUNC)
+#define TNC_IGD \
+ PCI_BDF(0, TNC_IGD_DEV, TNC_IGD_FUNC)
+#define TNC_SDVO \
+ PCI_BDF(0, TNC_SDVO_DEV, TNC_SDVO_FUNC)
+#define TNC_PCIE0 \
+ PCI_BDF(0, TNC_PCIE0_DEV, TNC_PCIE0_FUNC)
+#define TNC_PCIE1 \
+ PCI_BDF(0, TNC_PCIE1_DEV, TNC_PCIE1_FUNC)
+#define TNC_PCIE2 \
+ PCI_BDF(0, TNC_PCIE2_DEV, TNC_PCIE2_FUNC)
+#define TNC_PCIE3 \
+ PCI_BDF(0, TNC_PCIE3_DEV, TNC_PCIE3_FUNC)
+#define TNC_HDA \
+ PCI_BDF(0, TNC_HDA_DEV, TNC_HDA_FUNC)
+#define TNC_LPC \
+ PCI_BDF(0, TNC_LPC_DEV, TNC_LPC_FUNC)
+
+/* Topcliff IOH PCI Devices */
+#define TCF_PCIE_PORT_DEV 0
+#define TCF_PCIE_PORT_FUNC 0
+
+#define TCF_DEV_0 0
+#define TCF_PKT_HUB_FUNC 0
+#define TCF_GBE_FUNC 1
+#define TCF_GPIO_FUNC 2
+
+#define TCF_DEV_2 2
+#define TCF_USB1_OHCI0_FUNC 0
+#define TCF_USB1_OHCI1_FUNC 1
+#define TCF_USB1_OHCI2_FUNC 2
+#define TCF_USB1_EHCI_FUNC 3
+#define TCF_USB_DEVICE_FUNC 4
+
+#define TCF_DEV_4 4
+#define TCF_SDIO0_FUNC 0
+#define TCF_SDIO1_FUNC 1
+
+#define TCF_DEV_6 6
+#define TCF_SATA_FUNC 0
+
+#define TCF_DEV_8 8
+#define TCF_USB2_OHCI0_FUNC 0
+#define TCF_USB2_OHCI1_FUNC 1
+#define TCF_USB2_OHCI2_FUNC 2
+#define TCF_USB2_EHCI_FUNC 3
+
+#define TCF_DEV_10 10
+#define TCF_DMA1_FUNC 0
+#define TCF_UART0_FUNC 1
+#define TCF_UART1_FUNC 2
+#define TCF_UART2_FUNC 3
+#define TCF_UART3_FUNC 4
+
+#define TCF_DEV_12 12
+#define TCF_DMA2_FUNC 0
+#define TCF_SPI_FUNC 1
+#define TCF_I2C_FUNC 2
+#define TCF_CAN_FUNC 3
+#define TCF_1588_FUNC 4
+
+#endif /* _QUEENSBAY_DEVICE_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ARCH_IRQ_H_
+#define _ARCH_IRQ_H_
+
+enum pci_int_pin {
+ INTX,
+ INTA,
+ INTB,
+ INTC,
+ INTD
+};
+
+enum pirq_pin {
+ PIRQA,
+ PIRQB,
+ PIRQC,
+ PIRQD,
+ PIRQE,
+ PIRQF,
+ PIRQG,
+ PIRQH
+};
+
+/* PIRQ link number and value conversion */
+#define LINK_V2N(link) (link - 0x60)
+#define LINK_N2V(link) (link + 0x60)
+
+#define PIRQ_BITMAP 0xdee0
+
+struct irq_info;
+
+/**
+ * board_fill_irq_info() - Board-specific irq_info fill routine
+ *
+ * This fills the irq_info table for any board-specific add-in cards.
+ *
+ * @slot: pointer to the struct irq_info that is to be filled in
+ * @return: number of entries were written to the struct irq_info
+ */
+int board_fill_irq_info(struct irq_info *slot);
+
+/**
+ * pirq_init() - Initialize platform PIRQ routing
+ *
+ * This initializes the PIRQ routing on the platform and configures all PCI
+ * devices' interrupt line register to a working IRQ number on the 8259 PIC.
+ */
+void pirq_init(void);
+
+#endif /* _ARCH_IRQ_H_ */
#ifndef _X86_ARCH_TNC_H_
#define _X86_ARCH_TNC_H_
-#include <pci.h>
+/* Memory BAR Enable */
+#define MEM_BAR_EN 0x00000001
-/* PCI Configuration Space (D31:F0): LPC */
-#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
+/* LPC PCI Configuration Registers */
+#define LPC_RCBA 0xf0
+
+/* Root Complex Register Block */
+struct tnc_rcba {
+ u32 rctl;
+ u32 esd;
+ u32 rsvd1[2];
+ u32 hdd;
+ u32 rsvd2;
+ u32 hdba;
+ u32 rsvd3[3129];
+ u32 d31ip;
+ u32 rsvd4[3];
+ u32 d27ip;
+ u32 rsvd5;
+ u32 d02ip;
+ u32 rsvd6;
+ u32 d26ip;
+ u32 d25ip;
+ u32 d24ip;
+ u32 d23ip;
+ u32 d03ip;
+ u32 rsvd7[3];
+ u16 d31ir;
+ u16 rsvd8[3];
+ u16 d27ir;
+ u16 d26ir;
+ u16 d25ir;
+ u16 d24ir;
+ u16 d23ir;
+ u16 rsvd9[7];
+ u16 d02ir;
+ u16 d03ir;
+};
#endif /* _X86_ARCH_TNC_H_ */
--- /dev/null
+#ifndef _ASM_X86_ATOMIC_H
+#define _ASM_X86_ATOMIC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/processor.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+/*
+ * Atomic operations that C can't guarantee us. Useful for
+ * resource counting etc..
+ */
+
+#define ATOMIC_INIT(i) { (i) }
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+static inline int atomic_read(const atomic_t *v)
+{
+ return ACCESS_ONCE((v)->counter);
+}
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+static inline void atomic_set(atomic_t *v, int i)
+{
+ v->counter = i;
+}
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+ asm volatile(LOCK_PREFIX "addl %1,%0"
+ : "+m" (v->counter)
+ : "ir" (i));
+}
+
+/**
+ * atomic_sub - subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ asm volatile(LOCK_PREFIX "subl %1,%0"
+ : "+m" (v->counter)
+ : "ir" (i));
+}
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+static inline void atomic_inc(atomic_t *v)
+{
+ asm volatile(LOCK_PREFIX "incl %0"
+ : "+m" (v->counter));
+}
+
+/**
+ * atomic_dec - decrement atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+static inline void atomic_dec(atomic_t *v)
+{
+ asm volatile(LOCK_PREFIX "decl %0"
+ : "+m" (v->counter));
+}
+
+/**
+ * atomic_inc_short - increment of a short integer
+ * @v: pointer to type int
+ *
+ * Atomically adds 1 to @v
+ * Returns the new value of @u
+ */
+static inline short int atomic_inc_short(short int *v)
+{
+ asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
+ return *v;
+}
+
+/* These are x86-specific, used by some header files */
+#define atomic_clear_mask(mask, addr) \
+ asm volatile(LOCK_PREFIX "andl %0,%1" \
+ : : "r" (~(mask)), "m" (*(addr)) : "memory")
+
+#define atomic_set_mask(mask, addr) \
+ asm volatile(LOCK_PREFIX "orl %0,%1" \
+ : : "r" ((unsigned)(mask)), "m" (*(addr)) \
+ : "memory")
+
+#endif /* _ASM_X86_ATOMIC_H */
return ((f1^f2) & flag) != 0;
}
+static inline void mfence(void)
+{
+ __asm__ __volatile__("mfence" : : : "memory");
+}
+
/**
* cpu_enable_paging_pae() - Enable PAE-paging
*
*/
char *cpu_get_name(char *name);
+/**
+ *
+* x86_cpu_get_desc() - Get a description string for an x86 CPU
+*
+* This uses cpu_get_name() and is suitable to use as the get_desc() method for
+* the CPU uclass.
+*
+* @dev: Device to check (UCLASS_CPU)
+* @buf: Buffer to place string
+* @size: Size of string space
+* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+*/
+int x86_cpu_get_desc(struct udevice *dev, char *buf, int size);
+
/**
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
*
#ifndef _ASM_X86_E820_H
#define _ASM_X86_E820_H
-#define E820MAP 0x2d0 /* our map */
-#define E820MAX 128 /* number of entries in E820MAP */
-/*
- * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
- * constrained space in the zeropage. If we have more nodes than
- * that, and if we've booted off EFI firmware, then the EFI tables
- * passed us from the EFI firmware can list more nodes. Size our
- * internal memory map tables to have room for these additional
- * nodes, based on up to three entries per node for which the
- * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
- * plus E820MAX, allowing space for the possible duplicate E820
- * entries that might need room in the same arrays, prior to the
- * call to sanitize_e820_map() to remove duplicates. The allowance
- * of three memory map entries per node is "enough" entries for
- * the initial hardware platform motivating this mechanism to make
- * use of additional EFI map entries. Future platforms may want
- * to allow more than three entries per node or otherwise refine
- * this size.
- */
-
-/*
- * Odd: 'make headers_check' complains about numa.h if I try
- * to collapse the next two #ifdef lines to a single line:
- * #if defined(__KERNEL__) && defined(CONFIG_EFI)
- */
-#ifdef __KERNEL__
-#ifdef CONFIG_EFI
-#include <linux/numa.h>
-#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES)
-#else /* ! CONFIG_EFI */
-#define E820_X_MAX E820MAX
-#endif
-#else /* ! __KERNEL__ */
-#define E820_X_MAX E820MAX
-#endif
-
-#define E820NR 0x1e8 /* # entries in E820MAP */
+#define E820MAX 128 /* number of entries in E820MAP */
#define E820_RAM 1
#define E820_RESERVED 2
#define E820_NVS 4
#define E820_UNUSABLE 5
-/* reserved RAM used by kernel itself */
-#define E820_RESERVED_KERN 128
-
#ifndef __ASSEMBLY__
#include <linux/types.h>
+
struct e820entry {
__u64 addr; /* start of memory segment */
__u64 size; /* size of memory segment */
__u32 type; /* type of memory segment */
} __attribute__((packed));
-struct e820map {
- __u32 nr_map;
- struct e820entry map[E820_X_MAX];
-};
-
#define ISA_START_ADDRESS 0xa0000
#define ISA_END_ADDRESS 0x100000
-#define BIOS_BEGIN 0x000a0000
-#define BIOS_END 0x00100000
-
-#ifdef __KERNEL__
-/* see comment in arch/x86/kernel/e820.c */
-extern struct e820map e820;
-extern struct e820map e820_saved;
-
-extern unsigned long pci_mem_start;
-extern int e820_any_mapped(u64 start, u64 end, unsigned type);
-extern int e820_all_mapped(u64 start, u64 end, unsigned type);
-extern void e820_add_region(u64 start, u64 size, int type);
-extern void e820_print_map(char *who);
-extern int
-sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, u32 *pnr_map);
-extern u64 e820_update_range(u64 start, u64 size, unsigned old_type,
- unsigned new_type);
-extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type,
- int checktype);
-extern void update_e820(void);
-extern void e820_setup_gap(void);
-extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize,
- unsigned long start_addr, unsigned long long end_addr);
-struct setup_data;
-extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data);
-
-#if defined(CONFIG_X86_64) || \
- (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION))
-extern void e820_mark_nosave_regions(unsigned long limit_pfn);
-#else
-static inline void e820_mark_nosave_regions(unsigned long limit_pfn)
-{
-}
-#endif
-
-#ifdef CONFIG_MEMTEST
-extern void early_memtest(unsigned long start, unsigned long end);
-#else
-static inline void early_memtest(unsigned long start, unsigned long end)
-{
-}
-#endif
-
-extern unsigned long end_user_pfn;
-
-extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align);
-extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align);
-extern void reserve_early(u64 start, u64 end, char *name);
-extern void reserve_early_overlap_ok(u64 start, u64 end, char *name);
-extern void free_early(u64 start, u64 end);
-extern void early_res_to_bootmem(u64 start, u64 end);
-extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align);
-
-extern unsigned long e820_end_of_ram_pfn(void);
-extern unsigned long e820_end_of_low_ram_pfn(void);
-extern int e820_find_active_region(const struct e820entry *ei,
- unsigned long start_pfn,
- unsigned long last_pfn,
- unsigned long *ei_startpfn,
- unsigned long *ei_endpfn);
-extern void e820_register_active_regions(int nid, unsigned long start_pfn,
- unsigned long end_pfn);
-extern u64 e820_hole_size(u64 start, u64 end);
-extern void finish_e820_parsing(void);
-extern void e820_reserve_resources(void);
-extern void e820_reserve_resources_late(void);
-extern void setup_memory_map(void);
-extern char *default_machine_specific_memory_setup(void);
-
-/*
- * Returns true iff the specified range [s,e) is completely contained inside
- * the ISA region.
- */
-/*
-static inline bool is_ISA_range(u64 s, u64 e)
-{
- return s >= ISA_START_ADDRESS && e <= ISA_END_ADDRESS;
-}
-*/
-#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
-#ifdef __KERNEL__
-/* #include <linux/ioport.h> */
-
-#define HIGH_MEMORY (1024*1024)
-#endif /* __KERNEL__ */
-
#endif /* _ASM_X86_E820_H */
/* MRC training data to save for the next boot */
char *mrc_output;
unsigned int mrc_output_len;
+ void *gdt; /* Global descriptor table */
};
#endif
#define UART0_BASE 0x3f8
#define UART1_BASE 0x2f8
+#define UART0_IRQ 4
+#define UART1_IRQ 3
+
#endif
*/
void configure_irq_trigger(int int_num, bool is_level_triggered);
+void *x86_get_idt(void);
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * Taken from coreboot file of the same name
+ */
+
+#ifndef _X86_MP_H_
+#define _X86_MP_H_
+
+#include <asm/atomic.h>
+
+typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);
+
+/*
+ * A mp_flight_record details a sequence of calls for the APs to perform
+ * along with the BSP to coordinate sequencing. Each flight record either
+ * provides a barrier for each AP before calling the callback or the APs
+ * are allowed to perform the callback without waiting. Regardless, each
+ * record has the cpus_entered field incremented for each record. When
+ * the BSP observes that the cpus_entered matches the number of APs
+ * the bsp_call is called with bsp_arg and upon returning releases the
+ * barrier allowing the APs to make further progress.
+ *
+ * Note that ap_call() and bsp_call() can be NULL. In the NULL case the
+ * callback will just not be called.
+ */
+struct mp_flight_record {
+ atomic_t barrier;
+ atomic_t cpus_entered;
+ mp_callback_t ap_call;
+ void *ap_arg;
+ mp_callback_t bsp_call;
+ void *bsp_arg;
+} __attribute__((aligned(ARCH_DMA_MINALIGN)));
+
+#define MP_FLIGHT_RECORD(barrier_, ap_func_, ap_arg_, bsp_func_, bsp_arg_) \
+ { \
+ .barrier = ATOMIC_INIT(barrier_), \
+ .cpus_entered = ATOMIC_INIT(0), \
+ .ap_call = ap_func_, \
+ .ap_arg = ap_arg_, \
+ .bsp_call = bsp_func_, \
+ .bsp_arg = bsp_arg_, \
+ }
+
+#define MP_FR_BLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
+ MP_FLIGHT_RECORD(0, ap_func, ap_arg, bsp_func, bsp_arg)
+
+#define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \
+ MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)
+
+/*
+ * The mp_params structure provides the arguments to the mp subsystem
+ * for bringing up APs.
+ *
+ * At present this is overkill for U-Boot, but it may make it easier to add
+ * SMM support.
+ */
+struct mp_params {
+ int num_cpus; /* Total cpus include BSP */
+ int parallel_microcode_load;
+ const void *microcode_pointer;
+ /* Flight plan for APs and BSP */
+ struct mp_flight_record *flight_plan;
+ int num_records;
+};
+
+/*
+ * mp_init() will set up the SIPI vector and bring up the APs according to
+ * mp_params. Each flight record will be executed according to the plan. Note
+ * that the MP infrastructure uses SMM default area without saving it. It's
+ * up to the chipset or mainboard to either e820 reserve this area or save this
+ * region prior to calling mp_init() and restoring it after mp_init returns.
+ *
+ * At the time mp_init() is called the MTRR MSRs are mirrored into APs then
+ * caching is enabled before running the flight plan.
+ *
+ * The MP init has the following properties:
+ * 1. APs are brought up in parallel.
+ * 2. The ordering of cpu number and APIC ids is not deterministic.
+ * Therefore, one cannot rely on this property or the order of devices in
+ * the device tree unless the chipset or mainboard know the APIC ids
+ * a priori.
+ *
+ * mp_init() returns < 0 on error, 0 on success.
+ */
+int mp_init(struct mp_params *params);
+
+/* Probes the CPU device */
+int mp_init_cpu(struct udevice *cpu, void *unused);
+
+#endif /* _X86_MP_H_ */
#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
+#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd
#define MSR_PLATFORM_INFO 0x000000ce
+#define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2
+#define SINGLE_PCTL (1 << 11)
+
#define MSR_MTRRcap 0x000000fe
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
+#define MSR_POWER_MISC 0x00000120
+#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
+#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
#define MSR_IA32_SYSENTER_CS 0x00000174
#define MSR_IA32_SYSENTER_ESP 0x00000175
#define MSR_IA32_MCG_STATUS 0x0000017a
#define MSR_IA32_MCG_CTL 0x0000017b
+#define MSR_IA32_MISC_ENABLES 0x000001a0
#define MSR_OFFCORE_RSP_0 0x000001a6
#define MSR_OFFCORE_RSP_1 0x000001a7
#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
#define MSR_LBR_SELECT 0x000001c8
#define MSR_LBR_TOS 0x000001c9
+#define MSR_POWER_CTL 0x000001fc
#define MSR_LBR_NHM_FROM 0x00000680
#define MSR_LBR_NHM_TO 0x000006c0
#define MSR_LBR_CORE_FROM 0x00000040
/* Run Time Average Power Limiting (RAPL) Interface */
-#define MSR_RAPL_POWER_UNIT 0x00000606
+#define MSR_PKG_POWER_SKU_UNIT 0x00000606
#define MSR_PKG_POWER_LIMIT 0x00000610
#define MSR_PKG_ENERGY_STATUS 0x00000611
#define MSR_PP1_POLICY 0x00000642
#define MSR_CORE_C1_RES 0x00000660
+#define MSR_IACORE_RATIOS 0x0000066a
+#define MSR_IACORE_TURBO_RATIOS 0x0000066c
+#define MSR_IACORE_VIDS 0x0000066b
+#define MSR_IACORE_TURBO_VIDS 0x0000066d
+#define MSR_PKG_TURBO_CFG1 0x00000670
+#define MSR_CPU_TURBO_WKLD_CFG1 0x00000671
+#define MSR_CPU_TURBO_WKLD_CFG2 0x00000672
+#define MSR_CPU_THERM_CFG1 0x00000673
+#define MSR_CPU_THERM_CFG2 0x00000674
+#define MSR_CPU_THERM_SENS_CFG 0x00000675
#define MSR_AMD64_MC0_MASK 0xc0010044
#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
#define MSR_IA32_MISC_ENABLE 0x000001a0
+#define H_MISC_DISABLE_TURBO (1 << 6)
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
#define wrmsrl(msr, val) \
native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32))
+static inline void msr_clrsetbits_64(unsigned msr, u64 clear, u64 set)
+{
+ u64 val;
+
+ val = native_read_msr(msr);
+ val &= ~clear;
+ val |= set;
+ wrmsrl(msr, val);
+}
+
+static inline void msr_setbits_64(unsigned msr, u64 set)
+{
+ u64 val;
+
+ val = native_read_msr(msr);
+ val |= set;
+ wrmsrl(msr, val);
+}
+
+static inline void msr_clrbits_64(unsigned msr, u64 clear)
+{
+ u64 val;
+
+ val = native_read_msr(msr);
+ val &= ~clear;
+ wrmsrl(msr, val);
+}
+
/* rdmsr with exception handling */
#define rdmsr_safe(msr, p1, p2) \
({ \
/* Number of MTRRs supported */
#define MTRR_COUNT 8
+#define NUM_FIXED_MTRRS 11
+#define RANGES_PER_FIXED_MTRR 8
+#define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
+
+#define MTRR_FIX_64K_00000_MSR 0x250
+#define MTRR_FIX_16K_80000_MSR 0x258
+#define MTRR_FIX_16K_A0000_MSR 0x259
+#define MTRR_FIX_4K_C0000_MSR 0x268
+#define MTRR_FIX_4K_C8000_MSR 0x269
+#define MTRR_FIX_4K_D0000_MSR 0x26a
+#define MTRR_FIX_4K_D8000_MSR 0x26b
+#define MTRR_FIX_4K_E0000_MSR 0x26c
+#define MTRR_FIX_4K_E8000_MSR 0x26d
+#define MTRR_FIX_4K_F0000_MSR 0x26e
+#define MTRR_FIX_4K_F8000_MSR 0x26f
+
#if !defined(__ASSEMBLER__)
/**
int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
ulong value, enum pci_size_t size);
+/**
+ * Assign IRQ number to a PCI device
+ *
+ * This function assigns IRQ for a PCI device. If the device does not exist
+ * or does not require interrupts then this function has no effect.
+ *
+ * @bus: PCI bus number
+ * @device: PCI device number
+ * @func: PCI function number
+ * @irq: An array of IRQ numbers that are assigned to INTA through
+ * INTD of this PCI device.
+ */
+void pci_assign_irqs(int bus, int device, int func, u8 irq[4]);
+
#endif /* __ASSEMBLY__ */
#endif /* _PCI_I386_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PIRQ_ROUTING_H_
+#define _PIRQ_ROUTING_H_
+
+/*
+ * This is the maximum number on interrupt entries that a PCI device may have.
+ * This is NOT the number of slots or devices in the system
+ * This is NOT the number of entries in the PIRQ table
+ *
+ * This tells us that in the PIRQ table, we are going to have 4 link-bitmap
+ * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD.
+ *
+ * CAUTION: If you change this, PIRQ routing will not work correctly.
+ */
+#define MAX_INTX_ENTRIES 4
+
+#define PIRQ_SIGNATURE \
+ (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
+#define PIRQ_VERSION 0x0100
+
+struct __packed irq_info {
+ u8 bus; /* Bus number */
+ u8 devfn; /* Device and function number */
+ struct __packed {
+ u8 link; /* IRQ line ID, 0=not routed */
+ u16 bitmap; /* Available IRQs */
+ } irq[MAX_INTX_ENTRIES];
+ u8 slot; /* Slot number, 0=onboard */
+ u8 rfu;
+};
+
+struct __packed irq_routing_table {
+ u32 signature; /* PIRQ_SIGNATURE */
+ u16 version; /* PIRQ_VERSION */
+ u16 size; /* Table size in bytes */
+ u8 rtr_bus; /* busno of the interrupt router */
+ u8 rtr_devfn; /* devfn of the interrupt router */
+ u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
+ u16 rtr_vendor; /* Vendor ID of the interrupt router */
+ u16 rtr_device; /* Device ID of the interrupt router */
+ u32 miniport_data;
+ u8 rfu[11];
+ u8 checksum; /* Modulo 256 checksum must give zero */
+ struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
+};
+
+/**
+ * get_irq_slot_count() - Get the number of entries in the irq_info table
+ *
+ * This calculates the number of entries for the irq_info table.
+ *
+ * @rt: pointer to the base address of the struct irq_info
+ * @return: number of entries
+ */
+static inline int get_irq_slot_count(struct irq_routing_table *rt)
+{
+ return (rt->size - 32) / sizeof(struct irq_info);
+}
+
+/**
+ * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC
+ *
+ * This function checks whether an IRQ is routed to 8259 PIC for a given link.
+ *
+ * Note: this function should be provided by the platform codes, as the
+ * implementation of interrupt router may be different.
+ *
+ * @link: link number which represents a PIRQ
+ * @irq: the 8259 IRQ number
+ * @return: true if the irq is already routed to 8259 for a given link,
+ * false elsewise
+ */
+bool pirq_check_irq_routed(int link, u8 irq);
+
+/**
+ * pirq_translate_link() - Translate a link value
+ *
+ * This function translates a platform-specific link value to a link number.
+ * On Intel platforms, the link value is normally a offset into the PCI
+ * configuration space into the legacy bridge.
+ *
+ * Note: this function should be provided by the platform codes, as the
+ * implementation of interrupt router may be different.
+ *
+ * @link: platform-specific link value
+ * @return: link number which represents a PIRQ
+ */
+int pirq_translate_link(int link);
+
+/**
+ * pirq_assign_irq() - Assign an IRQ to a PIRQ link
+ *
+ * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to
+ * the 8259 PIC.
+ *
+ * Note: this function should be provided by the platform codes, as the
+ * implementation of interrupt router may be different.
+ *
+ * @link: link number which represents a PIRQ
+ * @irq: IRQ to which the PIRQ is routed
+ */
+void pirq_assign_irq(int link, u8 irq);
+
+/**
+ * pirq_route_irqs() - Route PIRQs to 8259 PIC
+ *
+ * This function configures all PCI devices' interrupt pins and maps them to
+ * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt
+ * line register in the configuration space of the PCI device for OS to use.
+ * The configuration source is taken from a struct irq_info table, the format
+ * of which is defined in PIRQ routing table spec and PCI BIOS spec.
+ *
+ * @irq: pointer to the base address of the struct irq_info
+ * @num: number of entries in the struct irq_info
+ */
+void pirq_route_irqs(struct irq_info *irq, int num);
+
+/**
+ * copy_pirq_routing_table() - Copy a PIRQ routing table
+ *
+ * This helper function copies the given PIRQ routing table to a given address.
+ * Before copying, it does several sanity tests against the PIRQ routing table.
+ * It also fixes up the table checksum and align the given address to a 16 byte
+ * boundary to meet the PIRQ routing table spec requirements.
+ *
+ * @addr: address to store the copied PIRQ routing table
+ * @rt: pointer to the PIRQ routing table to copy from
+ * @return: end address of the copied PIRQ routing table
+ */
+u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt);
+
+#endif /* _PIRQ_ROUTING_H_ */
#define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE)
+/* Length of the public header on Intel microcode blobs */
+#define UCODE_HEADER_LEN 0x30
+
#ifndef __ASSEMBLY__
+/*
+ * This register is documented in (for example) the Intel Atom Processor E3800
+ * Product Family Datasheet in "PCU - Power Management Controller (PMC)".
+ *
+ * RST_CNT: Reset Control Register (RST_CNT) Offset cf9.
+ *
+ * The naming follows Intel's naming.
+ */
#define PORT_RESET 0xcf9
+enum {
+ SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */
+ RST_CPU = 1 << 2, /* initiate reset */
+ FULL_RST = 1 << 3, /* full power cycle */
+};
+
+/**
+ * x86_full_reset() - reset everything: perform a full power cycle
+ */
+void x86_full_reset(void);
+
static inline __attribute__((always_inline)) void cpu_hlt(void)
{
asm("hlt");
--- /dev/null
+/*
+ * Copyright(c) 2009 Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
+ */
+
+#ifndef _LINUX_SFI_H
+#define _LINUX_SFI_H
+
+#include <errno.h>
+#include <linux/types.h>
+
+/* Table signatures reserved by the SFI specification */
+#define SFI_SIG_SYST "SYST"
+#define SFI_SIG_FREQ "FREQ"
+#define SFI_SIG_CPUS "CPUS"
+#define SFI_SIG_MTMR "MTMR"
+#define SFI_SIG_MRTC "MRTC"
+#define SFI_SIG_MMAP "MMAP"
+#define SFI_SIG_APIC "APIC"
+#define SFI_SIG_XSDT "XSDT"
+#define SFI_SIG_WAKE "WAKE"
+#define SFI_SIG_DEVS "DEVS"
+#define SFI_SIG_GPIO "GPIO"
+
+#define SFI_SIGNATURE_SIZE 4
+#define SFI_OEM_ID_SIZE 6
+#define SFI_OEM_TABLE_ID_SIZE 8
+
+#define SFI_NAME_LEN 16
+#define SFI_TABLE_MAX_ENTRIES 16
+
+#define SFI_GET_NUM_ENTRIES(ptable, entry_type) \
+ ((ptable->header.len - sizeof(struct sfi_table_header)) / \
+ (sizeof(entry_type)))
+/*
+ * Table structures must be byte-packed to match the SFI specification,
+ * as they are provided by the BIOS.
+ */
+struct __packed sfi_table_header {
+ char sig[SFI_SIGNATURE_SIZE];
+ u32 len;
+ u8 rev;
+ u8 csum;
+ char oem_id[SFI_OEM_ID_SIZE];
+ char oem_table_id[SFI_OEM_TABLE_ID_SIZE];
+};
+
+struct __packed sfi_table_simple {
+ struct sfi_table_header header;
+ u64 pentry[1];
+};
+
+/* Comply with UEFI spec 2.1 */
+struct __packed sfi_mem_entry {
+ u32 type;
+ u64 phys_start;
+ u64 virt_start;
+ u64 pages;
+ u64 attrib;
+};
+
+struct __packed sfi_cpu_table_entry {
+ u32 apic_id;
+};
+
+struct __packed sfi_cstate_table_entry {
+ u32 hint; /* MWAIT hint */
+ u32 latency; /* latency in ms */
+};
+
+struct __packed sfi_apic_table_entry {
+ u64 phys_addr; /* phy base addr for APIC reg */
+};
+
+struct __packed sfi_freq_table_entry {
+ u32 freq_mhz; /* in MHZ */
+ u32 latency; /* transition latency in ms */
+ u32 ctrl_val; /* value to write to PERF_CTL */
+};
+
+struct __packed sfi_wake_table_entry {
+ u64 phys_addr; /* pointer to where the wake vector locates */
+};
+
+struct __packed sfi_timer_table_entry {
+ u64 phys_addr; /* phy base addr for the timer */
+ u32 freq_hz; /* in HZ */
+ u32 irq;
+};
+
+struct __packed sfi_rtc_table_entry {
+ u64 phys_addr; /* phy base addr for the RTC */
+ u32 irq;
+};
+
+struct __packed sfi_device_table_entry {
+ u8 type; /* bus type, I2C, SPI or ...*/
+ u8 host_num; /* attached to host 0, 1...*/
+ u16 addr;
+ u8 irq;
+ u32 max_freq;
+ char name[SFI_NAME_LEN];
+};
+
+enum {
+ SFI_DEV_TYPE_SPI = 0,
+ SFI_DEV_TYPE_I2C,
+ SFI_DEV_TYPE_UART,
+ SFI_DEV_TYPE_HSI,
+ SFI_DEV_TYPE_IPC,
+ SFI_DEV_TYPE_SD,
+};
+
+struct __packed sfi_gpio_table_entry {
+ char controller_name[SFI_NAME_LEN];
+ u16 pin_no;
+ char pin_name[SFI_NAME_LEN];
+};
+
+struct sfi_xsdt_header {
+ uint32_t oem_revision;
+ uint32_t creator_id;
+ uint32_t creator_revision;
+};
+
+typedef int (*sfi_table_handler) (struct sfi_table_header *table);
+
+/**
+ * write_sfi_table() - Write Simple Firmware Interface tables
+ *
+ * @base: Address to write table to
+ * @return address to use for the next table
+ */
+u32 write_sfi_table(u32 base);
+
+#endif /*_LINUX_SFI_H */
--- /dev/null
+/*
+ * Copyright (c) 2015 Gooogle, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_SIPI_H
+#define _ASM_SIPI_H
+
+#define AP_DEFAULT_BASE 0x30000
+#define AP_DEFAULT_SIZE 0x10000
+
+#ifndef __ASSEMBLER__
+
+/**
+ * struct sipi_params_16bit - 16-bit SIPI entry-point parameters
+ *
+ * These are set up in the same space as the SIPI 16-bit code so that each AP
+ * can access the parameters when it boots.
+ *
+ * Each of these must be set up for the AP to boot, except @segment which is
+ * set in the assembly code.
+ *
+ * @ap_start: 32-bit SIPI entry point for U-Boot
+ * @segment: Code segment for U-Boot
+ * @pad: Padding (not used)
+ * @gdt_limit: U-Boot GDT limit (X86_GDT_SIZE - 1)
+ * @gdt: U-Boot GDT (gd->arch.gdt)
+ * @unused: Not used
+ */
+struct __packed sipi_params_16bit {
+ u32 ap_start;
+ u16 segment;
+ u16 pad;
+ u16 gdt_limit;
+ u32 gdt;
+ u16 unused;
+};
+
+/**
+ * struct sipi_params - 32-bit SIP entry-point parameters
+ *
+ * These are used by the AP init code and must be set up before the APs start.
+ *
+ * The stack area extends down from @stack_top, with @stack_size allocated
+ * for each AP.
+ *
+ * @idt_ptr: Interrupt descriptor table pointer
+ * @stack_top: Top of the AP stack area
+ * @stack_size: Size of each AP's stack
+ * @microcode_lock: Used to ensure only one AP loads microcode at once
+ * 0xffffffff enables parallel loading.
+ * @microcode_ptr: Pointer to microcode, or 0 if none
+ * @msr_table_ptr: Pointer to saved MSRs, a list of struct saved_msr
+ * @msr_count: Number of saved MSRs
+ * @c_handler: C function to call once early init is complete
+ * @ap_count: Shared atomic value to allocate CPU indexes
+ */
+struct sipi_params {
+ u32 idt_ptr;
+ u32 stack_top;
+ u32 stack_size;
+ u32 microcode_lock;
+ u32 microcode_ptr;
+ u32 msr_table_ptr;
+ u32 msr_count;
+ u32 c_handler;
+ atomic_t ap_count;
+};
+
+/* 16-bit AP entry point */
+void ap_start16(void);
+
+/* end of 16-bit code/data, marks the region to be copied to SIP vector */
+void ap_start16_code_end(void);
+
+/* 32-bit AP entry point */
+void ap_start(void);
+
+extern char sipi_params_16bit[];
+extern char sipi_params[];
+
+#endif /* __ASSEMBLER__ */
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _X86_TABLES_H_
+#define _X86_TABLES_H_
+
+/*
+ * All x86 tables happen to like the address range from 0xf0000 to 0x100000.
+ * We use 0xf0000 as the starting address to store those tables, including
+ * PIRQ routing table, Multi-Processor table and ACPI table.
+ */
+#define ROM_TABLE_ADDR 0xf0000
+
+/**
+ * table_compute_checksum() - Compute a table checksum
+ *
+ * This computes an 8-bit checksum for the configuration table.
+ * All bytes in the configuration table, including checksum itself and
+ * reserved bytes must add up to zero.
+ *
+ * @v: configuration table base address
+ * @len: configuration table size
+ * @return: the 8-bit checksum
+ */
+u8 table_compute_checksum(void *v, int len);
+
+/**
+ * write_tables() - Write x86 configuration tables
+ *
+ * This writes x86 configuration tables, including PIRQ routing table,
+ * Multi-Processor table and ACPI table. Whether a specific type of
+ * configuration table is written is controlled by a Kconfig option.
+ */
+void write_tables(void);
+
+/**
+ * write_pirq_routing_table() - Write PIRQ routing table
+ *
+ * This writes PIRQ routing table at a given address.
+ *
+ * @start: start address to write PIRQ routing table
+ * @return: end address of PIRQ routing table
+ */
+u32 write_pirq_routing_table(u32 start);
+
+#endif /* _X86_TABLES_H_ */
#define CPUID_LEAF_PM 6
#define PM_CAP_TURBO_MODE (1 << 1)
-#define MSR_IA32_MISC_ENABLES 0x1a0
-#define H_MISC_DISABLE_TURBO (1 << 6)
-
enum {
TURBO_UNKNOWN,
TURBO_UNAVAILABLE,
void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
void board_init_f_r(void) __attribute__ ((noreturn));
+int arch_misc_init(void);
+
/* Read the time stamp counter */
static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
{
void quick_ram_check(void);
+int x86_init_cpus(void);
+
#define PCI_VGA_RAM_IMAGE_START 0xc0000
#endif /* _U_BOOT_I386_H_ */
obj-$(CONFIG_PCI) += pci_type1.o
endif
obj-y += pch-uclass.o
+obj-y += pirq_routing.o
obj-y += relocate.o
obj-y += physmem.o
obj-$(CONFIG_X86_RAMTEST) += ramtest.o
+obj-y += sfi.o
obj-y += string.o
+obj-y += tables.o
obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o
-obj-$(CONFIG_VIDEO_VGA) += video.o
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
obj-$(CONFIG_HAVE_FSP) += fsp/
return default_print_cpuinfo();
}
-void reset_cpu(ulong addr)
-{
- /* cold reset */
- outb(0x06, PORT_RESET);
-}
-
-
int board_pci_post_scan(struct pci_controller *hose)
{
u32 status;
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/pirq_routing.h>
+#include <asm/tables.h>
+
+static bool irq_already_routed[16];
+
+static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
+{
+ int i, link;
+ u8 irq = 0;
+
+ /* IRQ sharing starts from IRQ#3 */
+ for (i = 3; i < 16; i++) {
+ /* Can we assign this IRQ? */
+ if (!((bitmap >> i) & 1))
+ continue;
+
+ /* We can, now let's assume we can use this IRQ */
+ irq = i;
+
+ /* Have we already routed it? */
+ if (irq_already_routed[irq])
+ continue;
+
+ for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) {
+ if (pirq_check_irq_routed(link, irq)) {
+ irq_already_routed[irq] = true;
+ break;
+ }
+ }
+
+ /* If it's not yet routed, use it */
+ if (!irq_already_routed[irq]) {
+ irq_already_routed[irq] = true;
+ break;
+ }
+
+ /* But if it was already routed, try the next one */
+ }
+
+ /* Now we get our IRQ */
+ return irq;
+}
+
+void pirq_route_irqs(struct irq_info *irq, int num)
+{
+ unsigned char irq_slot[MAX_INTX_ENTRIES];
+ unsigned char pirq[CONFIG_MAX_PIRQ_LINKS];
+ int i, intx;
+
+ memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS);
+
+ /* Set PCI IRQs */
+ for (i = 0; i < num; i++) {
+ debug("PIRQ Entry %d Dev: %d.%x.%d\n", i,
+ irq->bus, irq->devfn >> 3, irq->devfn & 7);
+
+ for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) {
+ int link = irq->irq[intx].link;
+ int bitmap = irq->irq[intx].bitmap;
+ int irq = 0;
+
+ debug("INT%c link: %x bitmap: %x ",
+ 'A' + intx, link, bitmap);
+
+ if (!bitmap || !link) {
+ debug("not routed\n");
+ irq_slot[intx] = irq;
+ continue;
+ }
+
+ /* translate link value to link number */
+ link = pirq_translate_link(link);
+
+ /* yet not routed */
+ if (!pirq[link]) {
+ irq = pirq_get_next_free_irq(pirq, bitmap);
+ pirq[link] = irq;
+ } else {
+ irq = pirq[link];
+ }
+
+ debug("IRQ: %d\n", irq);
+ irq_slot[intx] = irq;
+
+ /* Assign IRQ in the interrupt router */
+ pirq_assign_irq(link, irq);
+ }
+
+ /* Bus, device, slots IRQs for {A,B,C,D} */
+ pci_assign_irqs(irq->bus, irq->devfn >> 3, irq->devfn & 7,
+ irq_slot);
+
+ irq++;
+ }
+
+ for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++)
+ debug("PIRQ%c: %d\n", 'A' + i, pirq[i]);
+}
+
+u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
+{
+ struct irq_routing_table *rom_rt;
+
+ /* Fix up the table checksum */
+ rt->checksum = table_compute_checksum(rt, rt->size);
+
+ /* Align the table to be 16 byte aligned */
+ addr = ALIGN(addr, 16);
+
+ debug("Copying Interrupt Routing Table to 0x%x\n", addr);
+ memcpy((void *)addr, rt, rt->size);
+
+ /*
+ * We do the sanity check here against the copied table after memcpy,
+ * as something might go wrong after the memcpy, which is normally
+ * due to the F segment decode is not turned on to systeam RAM.
+ */
+ rom_rt = (struct irq_routing_table *)addr;
+ if (rom_rt->signature != PIRQ_SIGNATURE ||
+ rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) {
+ printf("Interrupt Routing Table not valid\n");
+ return addr;
+ }
+
+ return addr + rt->size;
+}
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Intel Simple Firmware Interface (SFI)
+ *
+ * Yet another way to pass information to the Linux kernel.
+ *
+ * See https://simplefirmware.org/ for details
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <asm/cpu.h>
+#include <asm/ioapic.h>
+#include <asm/sfi.h>
+#include <asm/tables.h>
+#include <dm/uclass-internal.h>
+
+struct table_info {
+ u32 base;
+ int ptr;
+ u32 entry_start;
+ u64 table[SFI_TABLE_MAX_ENTRIES];
+ int count;
+};
+
+static void *get_entry_start(struct table_info *tab)
+{
+ if (tab->count == SFI_TABLE_MAX_ENTRIES)
+ return NULL;
+ tab->entry_start = tab->base + tab->ptr;
+ tab->table[tab->count] = tab->entry_start;
+ tab->entry_start += sizeof(struct sfi_table_header);
+
+ return (void *)tab->entry_start;
+}
+
+static void finish_table(struct table_info *tab, const char *sig, void *entry)
+{
+ struct sfi_table_header *hdr;
+
+ hdr = (struct sfi_table_header *)(tab->base + tab->ptr);
+ strcpy(hdr->sig, sig);
+ hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start);
+ hdr->rev = 1;
+ strncpy(hdr->oem_id, "U-Boot", SFI_OEM_ID_SIZE);
+ strncpy(hdr->oem_table_id, "Table v1", SFI_OEM_TABLE_ID_SIZE);
+ hdr->csum = 0;
+ hdr->csum = table_compute_checksum(hdr, hdr->len);
+ tab->ptr += hdr->len;
+ tab->ptr = ALIGN(tab->ptr, 16);
+ tab->count++;
+}
+
+static int sfi_write_system_header(struct table_info *tab)
+{
+ u64 *entry = get_entry_start(tab);
+ int i;
+
+ if (!entry)
+ return -ENOSPC;
+
+ for (i = 0; i < tab->count; i++)
+ *entry++ = tab->table[i];
+ finish_table(tab, SFI_SIG_SYST, entry);
+
+ return 0;
+}
+
+static int sfi_write_cpus(struct table_info *tab)
+{
+ struct sfi_cpu_table_entry *entry = get_entry_start(tab);
+ struct udevice *dev;
+ int count = 0;
+
+ if (!entry)
+ return -ENOSPC;
+
+ for (uclass_find_first_device(UCLASS_CPU, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ if (!device_active(dev))
+ continue;
+ entry->apic_id = plat->cpu_id;
+ entry++;
+ count++;
+ }
+
+ /* Omit the table if there is only one CPU */
+ if (count > 1)
+ finish_table(tab, SFI_SIG_CPUS, entry);
+
+ return 0;
+}
+
+static int sfi_write_apic(struct table_info *tab)
+{
+ struct sfi_apic_table_entry *entry = get_entry_start(tab);
+
+ if (!entry)
+ return -ENOSPC;
+
+ entry->phys_addr = IO_APIC_ADDR;
+ entry++;
+ finish_table(tab, SFI_SIG_APIC, entry);
+
+ return 0;
+}
+
+static int sfi_write_xsdt(struct table_info *tab)
+{
+ struct sfi_xsdt_header *entry = get_entry_start(tab);
+
+ if (!entry)
+ return -ENOSPC;
+
+ entry->oem_revision = 1;
+ entry->creator_id = 1;
+ entry->creator_revision = 1;
+ entry++;
+ finish_table(tab, SFI_SIG_XSDT, entry);
+
+ return 0;
+}
+
+u32 write_sfi_table(u32 base)
+{
+ struct table_info table;
+
+ table.base = base;
+ table.ptr = 0;
+ table.count = 0;
+ sfi_write_cpus(&table);
+ sfi_write_apic(&table);
+
+ /*
+ * The SFI specification marks the XSDT table as option, but Linux 4.0
+ * crashes on start-up when it is not provided.
+ */
+ sfi_write_xsdt(&table);
+
+ /* Finally, write out the system header which points to the others */
+ sfi_write_system_header(&table);
+
+ return base + table.ptr;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/sfi.h>
+#include <asm/tables.h>
+
+u8 table_compute_checksum(void *v, int len)
+{
+ u8 *bytes = v;
+ u8 checksum = 0;
+ int i;
+
+ for (i = 0; i < len; i++)
+ checksum -= bytes[i];
+
+ return checksum;
+}
+
+void write_tables(void)
+{
+ u32 __maybe_unused rom_table_end = ROM_TABLE_ADDR;
+
+#ifdef CONFIG_GENERATE_PIRQ_TABLE
+ rom_table_end = write_pirq_routing_table(rom_table_end);
+ rom_table_end = ALIGN(rom_table_end, 1024);
+#endif
+#ifdef CONFIG_GENERATE_SFI_TABLE
+ rom_table_end = write_sfi_table(rom_table_end);
+ rom_table_end = ALIGN(rom_table_end, 1024);
+#endif
+}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <pci.h>
-#include <stdio_dev.h>
-#include <i8042.h>
-#include <asm/ptrace.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-
-/* basic textmode I/O from linux kernel */
-static char *vidmem = (char *)0xb8000;
-static int vidport;
-static int lines, cols;
-static int orig_x, orig_y;
-
-static void beep(int dur)
-{
- int i;
-
- outb_p(3, 0x61);
- for (i = 0; i < 10*dur; i++)
- udelay(1000);
-
- outb_p(0, 0x61);
-}
-
-static void scroll(void)
-{
- int i;
-
- memcpy(vidmem, vidmem + cols * 2, (lines - 1) * cols * 2);
- for (i = (lines - 1) * cols * 2; i < lines * cols * 2; i += 2)
- vidmem[i] = ' ';
-}
-
-static void __video_putc(const char c, int *x, int *y)
-{
- if (c == '\n') {
- (*x) = 0;
- if (++(*y) >= lines) {
- scroll();
- (*y)--;
- }
- } else if (c == '\b') {
- if ((*x) != 0) {
- --(*x);
- vidmem[((*x) + cols * (*y)) * 2] = ' ';
- }
- } else if (c == '\r') {
- (*x) = 0;
-
- } else if (c == '\a') {
- beep(3);
-
- } else if (c == '\t') {
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- __video_putc(' ', x, y);
- } else if (c == '\v') {
- switch ((*x) % 8) {
- case 0:
- __video_putc(' ', x, y);
- case 7:
- __video_putc(' ', x, y);
- case 6:
- __video_putc(' ', x, y);
- case 5:
- __video_putc(' ', x, y);
- case 4:
- __video_putc(' ', x, y);
- case 3:
- __video_putc(' ', x, y);
- case 2:
- __video_putc(' ', x, y);
- case 1:
- __video_putc(' ', x, y);
- }
- } else if (c == '\f') {
- int i;
- for (i = 0; i < lines * cols * 2; i += 2)
- vidmem[i] = 0;
- (*x) = 0;
- (*y) = 0;
- } else {
- vidmem[((*x) + cols * (*y)) * 2] = c;
- if (++(*x) >= cols) {
- (*x) = 0;
- if (++(*y) >= lines) {
- scroll();
- (*y)--;
- }
- }
- }
-}
-
-static void video_putc(struct stdio_dev *dev, const char c)
-{
- int x, y, pos;
-
- x = orig_x;
- y = orig_y;
-
- __video_putc(c, &x, &y);
-
- orig_x = x;
- orig_y = y;
-
- pos = (x + cols * y) * 2; /* Update cursor position */
- outb_p(14, vidport);
- outb_p(0xff & (pos >> 9), vidport+1);
- outb_p(15, vidport);
- outb_p(0xff & (pos >> 1), vidport+1);
-}
-
-static void video_puts(struct stdio_dev *dev, const char *s)
-{
- int x, y, pos;
- char c;
-
- x = orig_x;
- y = orig_y;
-
- while ((c = *s++) != '\0')
- __video_putc(c, &x, &y);
-
- orig_x = x;
- orig_y = y;
-
- pos = (x + cols * y) * 2; /* Update cursor position */
- outb_p(14, vidport);
- outb_p(0xff & (pos >> 9), vidport+1);
- outb_p(15, vidport);
- outb_p(0xff & (pos >> 1), vidport+1);
-}
-
-int video_init(void)
-{
- u16 pos;
-
- static struct stdio_dev vga_dev;
- static struct stdio_dev kbd_dev;
-
- vidmem = (char *) 0xb8000;
- vidport = 0x3d4;
-
- lines = 25;
- cols = 80;
-
- outb_p(14, vidport);
- pos = inb_p(vidport+1);
- pos <<= 8;
- outb_p(15, vidport);
- pos |= inb_p(vidport+1);
-
- orig_x = pos%cols;
- orig_y = pos/cols;
-
-#if 0
- printf("pos %x %d %d\n", pos, orig_x, orig_y);
-#endif
- if (orig_y > lines)
- orig_x = orig_y = 0;
-
- memset(&vga_dev, 0, sizeof(vga_dev));
- strcpy(vga_dev.name, "vga");
- vga_dev.ext = 0;
- vga_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
- vga_dev.putc = video_putc; /* 'putc' function */
- vga_dev.puts = video_puts; /* 'puts' function */
-
- if (stdio_register(&vga_dev) == 0)
- return 1;
-
- if (i8042_kbd_init())
- return 1;
-
- memset(&kbd_dev, 0, sizeof(kbd_dev));
- strcpy(kbd_dev.name, "kbd");
- kbd_dev.ext = 0;
- kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
- kbd_dev.tstc = i8042_tstc; /* 'tstc' function */
- kbd_dev.getc = i8042_getc; /* 'getc' function */
-
- if (stdio_register(&kbd_dev) == 0)
- return 1;
-
- return 0;
-}
-
-
-int drv_video_init(void)
-{
- return video_init();
-}
#endif
#include <linux/compiler.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* Memory lay-out:
*
#define COMMAND_LINE_SIZE 2048
-unsigned generic_install_e820_map(unsigned max_entries,
- struct e820entry *entries)
+/*
+ * Install a default e820 table with 3 entries as follows:
+ *
+ * 0x000000-0x0a0000 Useable RAM
+ * 0x0a0000-0x100000 Reserved for ISA
+ * 0x100000-gd->ram_size Useable RAM
+ */
+__weak unsigned install_e820_map(unsigned max_entries,
+ struct e820entry *entries)
{
- return 0;
+ entries[0].addr = 0;
+ entries[0].size = ISA_START_ADDRESS;
+ entries[0].type = E820_RAM;
+ entries[1].addr = ISA_START_ADDRESS;
+ entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+ entries[1].type = E820_RESERVED;
+ entries[2].addr = ISA_END_ADDRESS;
+ entries[2].size = gd->ram_size - ISA_END_ADDRESS;
+ entries[2].type = E820_RAM;
+
+ return 3;
}
-unsigned install_e820_map(unsigned max_entries,
- struct e820entry *entries)
- __attribute__((weak, alias("generic_install_e820_map")));
-
static void build_command_line(char *command_line, int auto_boot)
{
char *env_command_line;
--- /dev/null
+if TARGET_DB_88F6820_GP
+
+config SYS_BOARD
+ default "db-88f6820-gp"
+
+config SYS_VENDOR
+ default "Marvell"
+
+config SYS_SOC
+ default "mvebu"
+
+config SYS_CONFIG_NAME
+ default "db-88f6820-gp"
+
+endif
--- /dev/null
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := db-88f6820-gp.o
--- /dev/null
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.
--- /dev/null
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT(nr) (1UL << (nr))
+
+#define ETH_PHY_CTRL_REG 0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
+ (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
+ BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
+ BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
+ (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
+ BIT(16) | BIT(17) | BIT(18)))
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
+#define DB_GP_88F68XX_GPP_POL_LOW 0x0
+#define DB_GP_88F68XX_GPP_POL_MID 0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+ u8 chip;
+ u8 addr;
+ u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+ { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
+ { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
+ { 0x20, 2, 0x1D }, /* Output Data, register#0 */
+ { 0x20, 3, 0x18 }, /* Output Data, register#1 */
+ { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
+ { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
+ { 0x21, 2, 0x08 }, /* Output Data, register#0 */
+ { 0x21, 3, 0xC0 } /* Output Data, register#1 */
+};
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+ writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+ writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+ writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+ writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+ writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+ writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+ writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+ /* Set GPP Out value */
+ writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+ /* Set GPP Polarity */
+ writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+ writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+ /* Set GPP Out Enable */
+ writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ int i;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ /* Init I2C IO expanders */
+ for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+ i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Marvell DB-88F6820-GP\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068
default "Marvell"
config SYS_SOC
- default "armada-xp"
+ default "mvebu"
config SYS_CONFIG_NAME
default "db-mv784mp-gp"
/* Configure and enable MV88E1545 PHY */
void reset_phy(void)
{
- u16 devadr = CONFIG_PHY_BASE_ADDR;
+ u8 phy_addr[] = CONFIG_PHY_ADDR;
+ u16 devadr = phy_addr[0];
char *name = "neta0";
u16 reg;
--- /dev/null
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if VENDOR_COREBOOT
+
+choice
+ prompt "Mainboard model"
+
+config TARGET_COREBOOT
+ bool "coreboot"
+ help
+ This target is used for running U-Boot on top of coreboot. In
+ this case coreboot does the early inititalisation, and U-Boot
+ takes over once the RAM, video and CPU are fully running.
+ U-Boot is loaded as a fallback payload from coreboot, in
+ coreboot terminology. This method was used for the Chromebook
+ Pixel when launched.
+
+endchoice
+
+source "board/coreboot/coreboot/Kconfig"
+
+endif
config SYS_SOC
default "coreboot"
+config SYS_TEXT_BASE
+ default 0x01110000
+
comment "coreboot-specific options"
config SYS_CONFIG_NAME
--- /dev/null
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if VENDOR_GOOGLE
+
+choice
+ prompt "Mainboard model"
+
+config TARGET_CHROMEBOOK_LINK
+ bool "Chromebook link"
+ help
+ This is the Chromebook Pixel released in 2013. It uses an Intel
+ i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+ SDRAM. It has a Panther Point platform controller hub, PCIe
+ WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+ reader, microphone and speakers, display port and 32GB SATA
+ solid state drive. There is a Chrome OS EC connected on LPC,
+ and it provides a 2560x1700 high resolution touch-enabled LCD
+ display.
+
+config TARGET_CHROMEBOX_PANTHER
+ bool "Chromebox panther (not available)"
+ select n
+ help
+ Note: At present this must be used with coreboot. See README.x86
+ for instructions.
+
+ This is the Asus Chromebox CN60 released in 2014. It uses an Intel
+ Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
+ Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
+ includes a USB SD reader, four USB3 ports, display port and HDMI
+ video output and a 16GB SATA solid state drive. There is no Chrome
+ OS EC on this model.
+
+endchoice
+
+source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
+
+endif
config SYS_CONFIG_NAME
default "chromebook_link"
+config SYS_TEXT_BASE
+ default 0xfff00000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
config SYS_CONFIG_NAME
default "chromebox_panther"
+config SYS_TEXT_BASE
+ default 0xfff00000
+
# Panther actually uses haswell, not ivybridge, so this is just a placeholder
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
--- /dev/null
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if VENDOR_INTEL
+
+choice
+ prompt "Mainboard model"
+
+config TARGET_CROWNBAY
+ bool "Crown Bay"
+ help
+ This is the Intel Crown Bay Customer Reference Board. It contains
+ the Intel Atom Processor E6xx populated on the COM Express module
+ with 1GB DDR2 soldered down memory and a carrier board with the
+ Intel Platform Controller Hub EG20T, other system components and
+ peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
+
+config TARGET_GALILEO
+ bool "Galileo"
+ help
+ This is the Intel Galileo board, which is the first in a family of
+ Arduino-certified development and prototyping boards based on Intel
+ architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
+ single-core, single-thread, Intel Pentium processor instrunction set
+ architecture (ISA) compatible, operating at speeds up to 400Mhz,
+ along with 256MB DDR3 memory. It supports a wide range of industry
+ standard I/O interfaces, including a full-sized mini-PCIe slot,
+ one 100Mb Ethernet port, a microSD card slot, a USB host port and
+ a USB client port.
+
+config TARGET_MINNOWMAX
+ bool "Minnowboard MAX"
+ help
+ This is the Intel Minnowboard MAX. It contains an Atom E3800
+ processor in a small form factor with Ethernet, micro-SD, USB 2,
+ USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+ It requires some binary blobs - see README.x86 for details.
+
+ Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+ by U-Boot matches that value.
+
+endchoice
+
+source "board/intel/crownbay/Kconfig"
+source "board/intel/galileo/Kconfig"
+source "board/intel/minnowmax/Kconfig"
+
+endif
config SYS_CONFIG_NAME
default "crownbay"
+config SYS_TEXT_BASE
+ default 0xfff00000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
int board_early_init_f(void)
{
- lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+ lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
return 0;
}
config SYS_CONFIG_NAME
default "galileo"
+config SYS_TEXT_BASE
+ default 0xfff10000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
config SYS_CONFIG_NAME
default "minnowmax"
+config SYS_TEXT_BASE
+ default 0xfff00000
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
int board_early_init_f(void)
{
- lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
+ lpc47m_enable_serial(SERIAL_DEV, UART0_BASE, UART0_IRQ);
return 0;
}
default "maxbcm"
config SYS_SOC
- default "armada-xp"
+ default "mvebu"
config SYS_CONFIG_NAME
default "maxbcm"
#include <linux/mbus.h>
#include "../drivers/ddr/mvebu/ddr3_hw_training.h"
-#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/high_speed_env_spec.h"
DECLARE_GLOBAL_DATA_PTR;
if ARCH_SUNXI
+# Note only one of these may be selected at a time! But hidden choices are
+# not supported by Kconfig
+config SUNXI_GEN_SUN4I
+ bool
+ ---help---
+ Select this for sunxi SoCs which have resets and clocks set up
+ as the original A10 (mach-sun4i).
+
+config SUNXI_GEN_SUN6I
+ bool
+ ---help---
+ Select this for sunxi SoCs which have sun6i like periphery, like
+ separate ahb reset control registers, custom pmic bus, new style
+ watchdog, etc.
+
+
choice
prompt "Sunxi SoC Variant"
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7
+ select SUNXI_GEN_SUN4I
select SUPPORT_SPL
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select CPU_V7
+ select SUNXI_GEN_SUN4I
select SUPPORT_SPL
config MACH_SUN6I
bool "sun6i (Allwinner A31)"
select CPU_V7
+ select SUNXI_GEN_SUN6I
select SUPPORT_SPL
config MACH_SUN7I
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
-config MACH_SUN8I
+config MACH_SUN8I_A23
bool "sun8i (Allwinner A23)"
select CPU_V7
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
+config MACH_SUN8I_A33
+ bool "sun8i (Allwinner A33)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
select SUPPORT_SPL
endchoice
+# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
+config MACH_SUN8I
+ bool
+ default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
+
+
config DRAM_CLK
int "sunxi dram clock speed"
default 312 if MACH_SUN6I || MACH_SUN8I
at the same time, the system can be only booted in the FEL mode.
Only enable this if you really know what you are doing.
-config FDTFILE
- string "Default fdtfile env setting for this board"
-
config OLD_SUNXI_KERNEL_COMPAT
boolean "Enable workarounds for booting old kernels"
default n
See I2C0_ENABLE help text.
endif
+config AXP_GPIO
+ boolean "Enable support for gpio-s on axp PMICs"
+ default n
+ ---help---
+ Say Y here to enable support for the gpio pins of the axp PMIC ICs.
+
config VIDEO
boolean "Enable graphical uboot console on HDMI, LCD or VGA"
default y
---help---
Set the GMAC Transmit Clock Delay Chain value.
+config NET
+ default y
+
+config NETDEVICES
+ default y
+
+config DM_ETH
+ default y
+
+config DM_SERIAL
+ default y
+
endif
F: configs/Wits_Pro_A20_DKT_defconfig
F: include/configs/sun8i.h
F: configs/Ippo_q8h_v1_2_defconfig
+F: configs/Ippo_q8h_v1_2_a33_1024x600_defconfig
A20-OLINUXINO-LIME BOARD
M: FUKAUMI Naoki <naobsd@gmail.com>
S: Maintained
F: configs/Ampe_A76_defconfig
+Astar MID756 BOARD
+M: VishnuPatekar <vishnupatekar0510@gmail.com>
+S: Maintained
+F: configs/Astar_MID756_defconfig
+
COLOMBUS BOARD
M: Maxime Ripard <maxime.ripard@free-electrons.com>
S: Maintained
#include <asm/arch/dram.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc.h>
-#include <asm/arch/usbc.h>
+#include <asm/arch/usb_phy.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/usb/musb.h>
#include <net.h>
/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
int soft_i2c_gpio_sda;
int soft_i2c_gpio_scl;
+
+static int soft_i2c_board_init(void)
+{
+ int ret;
+
+ soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
+ if (soft_i2c_gpio_sda < 0) {
+ printf("Error invalid soft i2c sda pin: '%s', err %d\n",
+ CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
+ return soft_i2c_gpio_sda;
+ }
+ ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
+ if (ret) {
+ printf("Error requesting soft i2c sda pin: '%s', err %d\n",
+ CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
+ return ret;
+ }
+
+ soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
+ if (soft_i2c_gpio_scl < 0) {
+ printf("Error invalid soft i2c scl pin: '%s', err %d\n",
+ CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
+ return soft_i2c_gpio_scl;
+ }
+ ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
+ if (ret) {
+ printf("Error requesting soft i2c scl pin: '%s', err %d\n",
+ CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int soft_i2c_board_init(void) { return 0; }
#endif
DECLARE_GLOBAL_DATA_PTR;
/* add board specific code here */
int board_init(void)
{
- int id_pfr1;
+ int id_pfr1, ret;
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
}
- return 0;
+ ret = axp_gpio_init();
+ if (ret)
+ return ret;
+
+ /* Uses dm gpio code so do this here and not in i2c_init_board() */
+ return soft_i2c_board_init();
}
int dram_init(void)
clock_twi_onoff(4, 1);
#endif
#endif
-
-#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
- soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
- soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
-#endif
}
#ifdef CONFIG_SPL_BUILD
#endif
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
+extern const struct musb_platform_ops sunxi_musb_ops;
+
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
}
}
+ ret = sunxi_usb_phy_probe();
+ if (ret)
+ return ret;
+
#if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET)
musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);
#endif
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set up clock gating */
-#ifndef CONFIG_MACH_SUN6I
- setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
-#else
+#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
+#else
+ setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
#endif
/* Set MII clock */
help
Print console devices and information.
+config CMD_CPU
+ bool "cpu"
+ help
+ Print information about available CPUs. This normally shows the
+ number of CPUs, type (e.g. manufacturer, architecture, product or
+ internal name) and clock frequency. Other information may be
+ available depending on the CPU driver.
+
config CMD_LICENSE
bool "license"
help
obj-$(CONFIG_CMD_CLK) += cmd_clk.o
obj-$(CONFIG_CMD_CONSOLE) += cmd_console.o
obj-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
+obj-$(CONFIG_CMD_CPU) += cmd_cpu.o
obj-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
obj-$(CONFIG_CMD_DATE) += cmd_date.o
obj-$(CONFIG_CMD_DEMO) += cmd_demo.o
#endif
/*
- * sjg: IMO this code should be
+ * TODO(sjg@chromium.org): IMO this code should be
* refactored to a single function, something like:
*
* void led_set_state(enum led_colour_t colour, int on);
{
#ifdef CONFIG_SYS_SDRAM_BASE
/*
- * Detect whether we have so much RAM it goes past the end of our
+ * Detect whether we have so much RAM that it goes past the end of our
* 32-bit address space. If so, clip the usable RAM so it doesn't.
*/
if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
static int reserve_fdt(void)
{
/*
- * If the device tree is sitting immediate above our image then we
+ * If the device tree is sitting immediately above our image then we
* must relocate it. If it is embedded in the data section, then it
* will be relocated with other data.
*/
gd->start_addr_sp &= ~0xf;
/*
- * let the architecture specific code tailor gd->start_addr_sp and
+ * let the architecture-specific code tailor gd->start_addr_sp and
* gd->irq_sp
*/
return arch_reserve_stacks();
/*
* Save local variables to board info struct
*/
-
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
bd->bi_memsize = gd->ram_size; /* size in bytes */
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_X86)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu.h>
+#include <dm.h>
+
+static const char *cpu_feature_name[CPU_FEAT_COUNT] = {
+ "L1 cache",
+ "MMU",
+};
+
+static int print_cpu_list(bool detail)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ char buf[100];
+ int ret;
+
+ ret = uclass_get(UCLASS_CPU, &uc);
+ if (ret) {
+ printf("Cannot find CPU uclass\n");
+ return ret;
+ }
+ uclass_foreach_dev(dev, uc) {
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct cpu_info info;
+ bool first;
+ int i;
+
+ ret = cpu_get_desc(dev, buf, sizeof(buf));
+ printf("%3d: %-10s %s\n", dev->seq, dev->name,
+ ret ? "<no description>" : buf);
+ if (!detail)
+ continue;
+ ret = cpu_get_info(dev, &info);
+ if (ret) {
+ printf("\t(no detail available");
+ if (ret != -ENOSYS)
+ printf(": err=%d\n", ret);
+ printf(")\n");
+ continue;
+ }
+ printf("\tID = %d, freq = ", plat->cpu_id);
+ print_freq(info.cpu_freq, "");
+ first = true;
+ for (i = 0; i < CPU_FEAT_COUNT; i++) {
+ if (info.features & (1 << i)) {
+ printf("%s%s", first ? ": " : ", ",
+ cpu_feature_name[i]);
+ first = false;
+ }
+ }
+ printf("\n");
+ }
+
+ return 0;
+}
+
+static int do_cpu_list(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ if (print_cpu_list(false))
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static int do_cpu_detail(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (print_cpu_list(true))
+ return CMD_RET_FAILURE;
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_cpu_sub[] = {
+ U_BOOT_CMD_MKENT(list, 2, 1, do_cpu_list, "", ""),
+ U_BOOT_CMD_MKENT(detail, 4, 0, do_cpu_detail, "", ""),
+};
+
+/*
+ * Process a cpu sub-command
+ */
+static int do_cpu(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *c = NULL;
+
+ /* Strip off leading 'cpu' command argument */
+ argc--;
+ argv++;
+
+ if (argc)
+ c = find_cmd_tbl(argv[0], cmd_cpu_sub, ARRAY_SIZE(cmd_cpu_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ cpu, 2, 1, do_cpu,
+ "display information about CPUs",
+ "list - list available CPUs\n"
+ "cpu detail - show CPU detail"
+);
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI"
-CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_MMC0_CD_PIN="PG1"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
-CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
CONFIG_USB1_VBUS_PIN="PG11"
CONFIG_VIDEO_HDMI=n
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
CONFIG_USB1_VBUS_PIN="PG11"
CONFIG_VIDEO_HDMI=n
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_AXP_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN5I=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_VIDEO_VGA=y
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
# Also see: http://linux-sunxi.org/Ainol_AW1
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun7i-a20-ainol-aw1.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo:141,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
-CONFIG_FDTFILE="sun5i-a13-ampe-a76.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PG12"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_AXP_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN5I=y
--- /dev/null
+# The Astar MID756 is a 7" tablet using the A33 SoC with a 800x480 LCD screen,
+# 512M RAM, 8G ROM and integrated sdio wifi.
+#
+# Also see: http://linux-sunxi.org/Softwinner_astar-rda
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-astar-mid756"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=480
+# zq = 0x3bbb
+CONFIG_DRAM_ZQ=15291
+# Wifi power
+CONFIG_AXP221_DLDO1_VOLT=3300
+# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
+CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-bananapi.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
CONFIG_GMAC_TX_DELAY=3
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-bananapro.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
CONFIG_USB1_VBUS_PIN="PH0"
CONFIG_USB2_VBUS_PIN="PH1"
CONFIG_GMAC_TX_DELAY=3
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
-CONFIG_FDTFILE="sun6i-a31s-cs908.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun4i-a10-chuwi-v7-cw0825.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
-CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
# No Vbus gpio for usb1
CONFIG_USB1_VBUS_PIN=""
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
CONFIG_GMAC_TX_DELAY=1
CONFIG_VIDEO_VGA=y
CONFIG_ARM=y
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_FDTFILE="sun6i-a31-hummingbird.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
CONFIG_ARM=y
# No Vbus gpio for usb2
CONFIG_USB2_VBUS_PIN=""
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
# headphones port for details see: http://linux-sunxi.org/Hyundai_A7HD
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun4i-a10-hyundai-a7hd.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB09"
CONFIG_USB0_VBUS_DET="PH5"
--- /dev/null
+# This is a defconfig for generic 7" tablets using the Ippo q8h v1.2 pcb,
+# with an A33 SoC (the pcb can take an A23 or an A33), and a 1024x600 LCD
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2-lcd1024x600"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
+CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:51000,le:159,ri:160,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
+CONFIG_VIDEO_LCD_POWER="PH7"
+CONFIG_VIDEO_LCD_BL_EN="PH6"
+CONFIG_VIDEO_LCD_BL_PWM="PH0"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_A33=y
+CONFIG_DRAM_CLK=480
+# zq = 0x3bbb
+CONFIG_DRAM_ZQ=15291
+# Wifi power
+CONFIG_AXP221_DLDO1_VOLT=3300
+# aldo1 is connected to VCC-IO, VCC-PD, VCC-USB and VCC-HP
+CONFIG_AXP221_ALDO1_VOLT=3000
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v1.2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN8I=y
+CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
# zq = 0xf74a
CONFIG_DRAM_ZQ=63306
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PH0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN8I=y
+CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=480
# zq = 0xf777
CONFIG_DRAM_ZQ=63351
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-pcduino3-nano.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
CONFIG_GMAC_TX_DELAY=3
CONFIG_USB1_VBUS_PIN="PH11"
CONFIG_ARM=y
CONFIG_DRAM_ZQ=122
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
CONFIG_DRAM_EMR1=4
-CONFIG_DM=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_SERIAL=y
-CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
-CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
-CONFIG_OF_SEPARATE=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
-CONFIG_DM_ETH=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-pcduino.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
# 1 USB A, 1 USB mini OTG, Bluetooth and Wireless LAN.
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-mk808c.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
# http://linux-sunxi.org/MSI_Primo73
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun7i-a20-primo73.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS=""
-CONFIG_FDTFILE="sun6i-a31s-primo81.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo:36,hs:64,vs:50,sync:3,vmode:0"
CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-marsboard.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
CONFIG_VIDEO_VGA=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
# For more details see: http://linux-sunxi.org/Mele_I7
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
-CONFIG_FDTFILE="sun6i-a31-i7.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
# No Vbus gpio for usb2
CONFIG_USB2_VBUS_PIN=""
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-m3.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
CONFIG_VIDEO_VGA=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,USB_EHCI,STATUSLED=234"
-CONFIG_FDTFILE="sun7i-a20-m5.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
CONFIG_VIDEO_HDMI=y
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB1_VBUS_PIN="PH6"
CONFIG_DRAM_ZQ=122
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC"
-CONFIG_FDTFILE="sun6i-a31-m9.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
# No Vbus gpio for usb2
CONFIG_USB2_VBUS_PIN=""
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
# http://www.orangepi.org/
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-orangepi.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
CONFIG_GMAC_TX_DELAY=3
CONFIG_USB1_VBUS_PIN="PH26"
CONFIG_USB2_VBUS_PIN="PH22"
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
# http://www.orangepi.org/
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-orangepi-mini.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
CONFIG_MMC0_CD_PIN="PH10"
CONFIG_MMC3_CD_PIN="PH11"
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
-CONFIG_FDTFILE="sun5i-a13-tzx-q8-713b7.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-tzx-q8-713b7"
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PG12"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_AXP_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN5I=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun5i-a13-utoo-p66.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB04"
CONFIG_USB0_VBUS_DET="PG01"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
CONFIG_VIDEO_LCD_TL059WV5C0=y
+CONFIG_AXP_GPIO=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_ARM=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
CONFIG_DRAM_EMR1=0
+CONFIG_DM_SERIAL=n
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-wexler-tab7200.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:210,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-wits-pro-a20-dkt.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22,lo:15,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
# Also see: http://linux-sunxi.org/Yones_Toptech_BD1078
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun7i-a20-yones-toptech-bd1078.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_MMC1_CD_PIN="PH2"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_AXP_GPIO=y
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_DCLK_PHASE=0
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
CONFIG_X86=y
+CONFIG_VENDOR_GOOGLE=y
CONFIG_TARGET_CHROMEBOOK_LINK=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
CONFIG_X86=y
+CONFIG_VENDOR_GOOGLE=y
CONFIG_TARGET_CHROMEBOX_PANTHER=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000"
CONFIG_X86=y
+CONFIG_VENDOR_COREBOOT=y
CONFIG_TARGET_COREBOOT=y
CONFIG_OF_CONTROL=y
CONFIG_DM_PCI=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_CROWNBAY=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
+CONFIG_GENERATE_PIRQ_TABLE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_TARGET_DB_88F6820_GP=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun5i-a13-forfun-q88db.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PG12"
CONFIG_USB0_VBUS_DET="PG1"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_AXP_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN5I=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff10000"
CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_GALILEO=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_ZQ=127
CONFIG_DRAM_EMR1=4
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
# Also see: http://linux-sunxi.org/INet_3F
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun4i-a10-inet-3f.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB9"
# Also see: http://linux-sunxi.org/INet_3W
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun4i-a10-inet-3w.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
CONFIG_MMC0_CD_PIN="PH20"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
-CONFIG_FDTFILE="sun5i-a13-inet-86vs.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB0_VBUS_PIN="PG12"
CONFIG_USB0_VBUS_DET="PG1"
CONFIG_VIDEO_LCD_POWER="AXP0-0"
CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
CONFIG_VIDEO_LCD_BL_PWM="PB2"
+CONFIG_AXP_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN5I=y
# For more details see: http://linux-sunxi.org/Jesurun_Q5
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI,MACPWR=SUNXI_GPH(19)"
-CONFIG_FDTFILE="sun4i-a10-jesurun-q5.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
CONFIG_X86=y
+CONFIG_VENDOR_INTEL=y
CONFIG_TARGET_MINNOWMAX=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
-CONFIG_VIDEO_X86=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_HAVE_INTEL_ME=y
+CONFIG_GENERATE_SFI_TABLE=y
+CONFIG_CPU=y
+CONFIG_CMD_CPU=y
+CONFIG_SMP=y
# Also see http://focalcrest.com/en/pc.html#pro02
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN6I=y
# No Vbus gpio for usb2
CONFIG_USB2_VBUS_PIN=""
CONFIG_ETH_DESIGNWARE=y
-CONFIG_NETDEVICES=y
-CONFIG_NET=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun5i-a10s-mk802.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
CONFIG_USB1_VBUS_PIN="PB10"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-mk802.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun4i-a10-mk802ii.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_MACH_SUN4I=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
# More details are available at: http://linux-sunxi.org/Gemei_G9
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
-CONFIG_FDTFILE="sun4i-gemei-g9.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_PANEL_LVDS=y
CONFIG_VIDEO_LCD_POWER="PH8"
* ./mainboard/google/link/descriptor.bin
* ./mainboard/google/link/me.bin
-* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
+* ./northbridge/intel/sandybridge/systemagent-r6.bin
The 3rd one should be renamed to mrc.bin.
As for the video ROM, you can get it here [2].
Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
directory: board/intel/minnowmax/vga.bin
-You still need two more binary blobs. These come from the sample SPI image
-provided in the FSP (SPI.bin at the time of writing).
+You still need two more binary blobs. The first comes from the original
+firmware image available from:
+
+http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
+
+Unzip it:
+
+ $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
Use ifdtool in the U-Boot tools directory to extract the images from that
file, for example:
+ $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
+
+This will provide the descriptor file - copy this into the correct place:
+
+ $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
+
+Then do the same with the sample SPI image provided in the FSP (SPI.bin at
+the time of writing) to obtain the last image. Note that this will also
+produce a flash descriptor file, but it does not seem to work, probably
+because it is not designed for the Minnowmax. That is why you need to get
+the flash descriptor from the original firmware as above.
+
$ ./tools/ifdtool -x BayleyBay/SPI.bin
$ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
- $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
Now you can build U-Boot and obtain u-boot.rom
source "drivers/core/Kconfig"
+source "drivers/cpu/Kconfig"
+
source "drivers/demo/Kconfig"
source "drivers/pci/Kconfig"
obj-$(CONFIG_BIOSEMU) += bios_emulator/
obj-y += block/
obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
+obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FPGA) += fpga/
obj-y += hwmon/
*/
if (clean_up) {
BE_exit();
- if (vga_info->BIOSImage)
+ if (vga_info->BIOSImage &&
+ (u32)(vga_info->BIOSImage) != 0xc0000)
free(vga_info->BIOSImage);
free(vga_info);
vga_info = NULL;
int device_bind_driver(struct udevice *parent, const char *drv_name,
const char *dev_name, struct udevice **devp)
+{
+ return device_bind_driver_to_node(parent, drv_name, dev_name, -1, devp);
+}
+
+int device_bind_driver_to_node(struct udevice *parent, const char *drv_name,
+ const char *dev_name, int node,
+ struct udevice **devp)
{
struct driver *drv;
int ret;
printf("Cannot find driver '%s'\n", drv_name);
return -ENOENT;
}
- ret = device_bind(parent, drv, dev_name, NULL, -1, devp);
+ ret = device_bind(parent, drv, dev_name, NULL, node, devp);
if (ret) {
printf("Cannot create device named '%s' (err=%d)\n",
dev_name, ret);
--- /dev/null
+config CPU
+ bool "Enable CPU drivers using Driver Model"
+ help
+ This allows drivers to be provided for CPUs and their type to be
+ specified in the board's device tree. For boards which support
+ multiple CPUs, then normally have to be set up in U-Boot so that
+ they can work correctly in the OS. This provides a framework for
+ finding out information about available CPUs and making changes.
--- /dev/null
+#
+# Copyright (c) 2015 Google, Inc
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-$(CONFIG_CPU) += cpu-uclass.o
--- /dev/null
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+
+int cpu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ struct cpu_ops *ops = cpu_get_ops(dev);
+
+ if (!ops->get_desc)
+ return -ENOSYS;
+
+ return ops->get_desc(dev, buf, size);
+}
+
+int cpu_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ struct cpu_ops *ops = cpu_get_ops(dev);
+
+ if (!ops->get_desc)
+ return -ENOSYS;
+
+ return ops->get_info(dev, info);
+}
+
+U_BOOT_DRIVER(cpu_bus) = {
+ .name = "cpu_bus",
+ .id = UCLASS_SIMPLE_BUS,
+ .per_child_platdata_auto_alloc_size = sizeof(struct cpu_platdata),
+};
+
+static int uclass_cpu_init(struct uclass *uc)
+{
+ struct udevice *dev;
+ int node;
+ int ret;
+
+ node = fdt_path_offset(gd->fdt_blob, "/cpus");
+ if (node < 0)
+ return 0;
+
+ ret = device_bind_driver_to_node(dm_root(), "cpu_bus", "cpus", node,
+ &dev);
+
+ return ret;
+}
+
+UCLASS_DRIVER(cpu) = {
+ .id = UCLASS_CPU,
+ .name = "cpu",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .init = uclass_cpu_init,
+};
#define ECC_SUPPORT
#define NEW_FABRIC_TWSI_ADDR 0x4E
-#ifdef DB_784MP_GP
+#ifdef CONFIG_DB_784MP_GP
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4E
#else
#define BUS_WIDTH_ECC_TWSI_ADDR 0x4F
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
+obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
endif
/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */
ifdef CONFIG_TEGRA_GPIO
--- /dev/null
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * X-Powers AXP Power Management ICs gpio driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
+#include <asm/gpio.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <errno.h>
+
+#ifdef CONFIG_AXP152_POWER
+#include <axp152.h>
+#elif defined CONFIG_AXP209_POWER
+#include <axp209.h>
+#elif defined CONFIG_AXP221_POWER
+#include <axp221.h>
+#else
+#error Unknown AXP model
+#endif
+
+static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val);
+
+static u8 axp_get_gpio_ctrl_reg(unsigned pin)
+{
+ switch (pin) {
+ case 0: return AXP_GPIO0_CTRL;
+ case 1: return AXP_GPIO1_CTRL;
+#ifdef AXP_GPIO2_CTRL
+ case 2: return AXP_GPIO2_CTRL;
+#endif
+#ifdef AXP_GPIO3_CTRL
+ case 3: return AXP_GPIO3_CTRL;
+#endif
+ }
+ return 0;
+}
+
+static int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
+{
+ u8 reg;
+
+ switch (pin) {
+#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
+ case SUNXI_GPIO_AXP0_VBUS_DETECT:
+ return 0;
+#endif
+ default:
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
+
+ return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
+ }
+}
+
+static int axp_gpio_direction_output(struct udevice *dev, unsigned pin,
+ int val)
+{
+ __maybe_unused int ret;
+ u8 reg;
+
+ switch (pin) {
+#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+ case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+ ret = pmic_bus_clrbits(AXP221_MISC_CTRL,
+ AXP221_MISC_CTRL_N_VBUSEN_FUNC);
+ if (ret)
+ return ret;
+
+ return axp_gpio_set_value(dev, pin, val);
+#endif
+ default:
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
+
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+}
+
+static int axp_gpio_get_value(struct udevice *dev, unsigned pin)
+{
+ u8 reg, val, mask;
+ int ret;
+
+ switch (pin) {
+#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
+ case SUNXI_GPIO_AXP0_VBUS_DETECT:
+ ret = pmic_bus_read(AXP_POWER_STATUS, &val);
+ mask = AXP_POWER_STATUS_VBUS_PRESENT;
+ break;
+#endif
+#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+ case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+ ret = pmic_bus_read(AXP221_VBUS_IPSOUT, &val);
+ mask = AXP221_VBUS_IPSOUT_DRIVEBUS;
+ break;
+#endif
+ default:
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
+
+ ret = pmic_bus_read(AXP_GPIO_STATE, &val);
+ mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
+ }
+ if (ret)
+ return ret;
+
+ return (val & mask) ? 1 : 0;
+}
+
+static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
+{
+ u8 reg;
+
+ switch (pin) {
+#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
+ case SUNXI_GPIO_AXP0_VBUS_ENABLE:
+ if (val)
+ return pmic_bus_setbits(AXP221_VBUS_IPSOUT,
+ AXP221_VBUS_IPSOUT_DRIVEBUS);
+ else
+ return pmic_bus_clrbits(AXP221_VBUS_IPSOUT,
+ AXP221_VBUS_IPSOUT_DRIVEBUS);
+#endif
+ default:
+ reg = axp_get_gpio_ctrl_reg(pin);
+ if (reg == 0)
+ return -EINVAL;
+
+ return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
+ AXP_GPIO_CTRL_OUTPUT_LOW);
+ }
+}
+
+static const struct dm_gpio_ops gpio_axp_ops = {
+ .direction_input = axp_gpio_direction_input,
+ .direction_output = axp_gpio_direction_output,
+ .get_value = axp_gpio_get_value,
+ .set_value = axp_gpio_set_value,
+};
+
+static int gpio_axp_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ /* Tell the uclass how many GPIOs we have */
+ uc_priv->bank_name = strdup(SUNXI_GPIO_AXP0_PREFIX);
+ uc_priv->gpio_count = SUNXI_GPIO_AXP0_GPIO_COUNT;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(gpio_axp) = {
+ .name = "gpio_axp",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_axp_ops,
+ .probe = gpio_axp_probe,
+};
+
+int axp_gpio_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_bus_init();
+ if (ret)
+ return ret;
+
+ /* There is no devicetree support for the axp yet, so bind directly */
+ ret = device_bind_driver(dm_root(), "gpio_axp", "AXP-gpio", &dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
+#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
-#ifdef CONFIG_AXP209_POWER
-#include <axp209.h>
-#endif
-#ifdef CONFIG_AXP221_POWER
-#include <axp221.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
int gpio_direction_input(unsigned gpio)
{
-#ifdef AXP_GPIO
- if (gpio >= SUNXI_GPIO_AXP0_START)
- return axp_gpio_direction_input(gpio - SUNXI_GPIO_AXP0_START);
-#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
return 0;
int gpio_direction_output(unsigned gpio, int value)
{
-#ifdef AXP_GPIO
- if (gpio >= SUNXI_GPIO_AXP0_START)
- return axp_gpio_direction_output(gpio - SUNXI_GPIO_AXP0_START,
- value);
-#endif
sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
return sunxi_gpio_output(gpio, value);
int gpio_get_value(unsigned gpio)
{
-#ifdef AXP_GPIO
- if (gpio >= SUNXI_GPIO_AXP0_START)
- return axp_gpio_get_value(gpio - SUNXI_GPIO_AXP0_START);
-#endif
return sunxi_gpio_input(gpio);
}
int gpio_set_value(unsigned gpio, int value)
{
-#ifdef AXP_GPIO
- if (gpio >= SUNXI_GPIO_AXP0_START)
- return axp_gpio_set_value(gpio - SUNXI_GPIO_AXP0_START, value);
-#endif
return sunxi_gpio_output(gpio, value);
}
-int sunxi_name_to_gpio_bank(const char *name)
-{
- int group = 0;
-
- if (*name == 'P' || *name == 'p')
- name++;
- if (*name >= 'A') {
- group = *name - (*name > 'a' ? 'a' : 'A');
- return group;
- }
-
- return -1;
-}
-
int sunxi_name_to_gpio(const char *name)
{
int group = 0;
long pin;
char *eptr;
-#ifdef AXP_GPIO
- if (strncasecmp(name, "AXP0-", 5) == 0) {
- name += 5;
- if (strcmp(name, "VBUS-DETECT") == 0)
- return SUNXI_GPIO_AXP0_START +
- SUNXI_GPIO_AXP0_VBUS_DETECT;
- if (strcmp(name, "VBUS-ENABLE") == 0)
- return SUNXI_GPIO_AXP0_START +
- SUNXI_GPIO_AXP0_VBUS_ENABLE;
- pin = simple_strtol(name, &eptr, 10);
- if (!*name || *eptr)
- return -1;
- return SUNXI_GPIO_AXP0_START + pin;
- }
-#endif
if (*name == 'P' || *name == 'p')
name++;
if (*name >= 'A') {
}
#endif
+int sunxi_name_to_gpio_bank(const char *name)
+{
+ int group = 0;
+
+ if (*name == 'P' || *name == 'p')
+ name++;
+ if (*name >= 'A') {
+ group = *name - (*name > 'a' ? 'a' : 'A');
+ return group;
+ }
+
+ return -1;
+}
+
#ifdef CONFIG_DM_GPIO
+/* TODO(sjg@chromium.org): Remove this function and use device tree */
+int sunxi_name_to_gpio(const char *name)
+{
+ unsigned int gpio;
+ int ret;
+#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+ char lookup[8];
+
+ if (strcasecmp(name, "AXP0-VBUS-DETECT") == 0) {
+ sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+ SUNXI_GPIO_AXP0_VBUS_DETECT);
+ name = lookup;
+ } else if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
+ sprintf(lookup, SUNXI_GPIO_AXP0_PREFIX "%d",
+ SUNXI_GPIO_AXP0_VBUS_ENABLE);
+ name = lookup;
+ }
+#endif
+ ret = gpio_lookup_name(name, NULL, NULL, &gpio);
+
+ return ret ? ret : gpio;
+}
+
static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
{
char *name;
- name = malloc(2);
+ name = malloc(3);
if (name) {
- name[0] = 'A' + bank;
- name[1] = '\0';
+ name[0] = 'P';
+ name[1] = 'A' + bank;
+ name[2] = '\0';
}
return name;
}
static const struct udevice_id sunxi_gpio_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-pinctrl" },
+ { .compatible = "allwinner,sun5i-a10s-pinctrl" },
+ { .compatible = "allwinner,sun5i-a13-pinctrl" },
+ { .compatible = "allwinner,sun6i-a31-pinctrl" },
+ { .compatible = "allwinner,sun6i-a31s-pinctrl" },
{ .compatible = "allwinner,sun7i-a20-pinctrl" },
+ { .compatible = "allwinner,sun8i-a23-pinctrl" },
+ { .compatible = "allwinner,sun9i-a80-pinctrl" },
{ }
};
outb(0xaa, port);
}
-void lpc47m_enable_serial(u16 dev, u16 iobase)
+void lpc47m_enable_serial(u16 dev, u16 iobase, u8 irq)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_irq(dev, PNP_IDX_IRQ0, irq);
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}
* (Which is just as well - otherwise we'd have to nobble the DMA engine
* too)
*/
- while (get_timer_us(bcm_host->last_write) < bcm_host->twoticks_delay)
+ while (get_timer(bcm_host->last_write) < bcm_host->twoticks_delay)
;
writel(val, host->ioaddr + reg);
- bcm_host->last_write = get_timer_us(0);
+ bcm_host->last_write = get_timer(0);
}
static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg)
struct bcm2835_sdhci_host *bcm_host;
struct sdhci_host *host;
- bcm_host = malloc(sizeof(*bcm_host));
+ bcm_host = calloc(1, sizeof(*bcm_host));
if (!bcm_host) {
- printf("sdhci_host malloc fail!\n");
+ printf("sdhci_host calloc fail!\n");
return 1;
}
host->cfg.host_caps |= MMC_MODE_4BIT;
host->cfg.host_caps &= ~MMC_MODE_8BIT;
}
- host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+ host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
/* Workaround for ESDHC errata ENGcm03648 */
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
- int timeout = 2500;
+ int timeout = 6000;
- /* Poll on DATA0 line for cmd with busy signal for 250 ms */
+ /* Poll on DATA0 line for cmd with busy signal for 600 ms */
while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
PRSSTAT_DAT0)) {
udelay(100);
return -1;
}
- cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
+ cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz;
#endif
host->name = "kona-sdhci";
host->ioaddr = reg_base;
host->quirks = quirks;
- host->host_caps = MMC_MODE_HC;
if (init_kona_mmc_core(host)) {
free(host);
if (!mmc_host_is_spi(mmc))
cmd.cmdarg = mmc->rca << 16;
- do {
+ while (1) {
err = mmc_send_cmd(mmc, &cmd, NULL);
if (!err) {
if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
} else if (--retries < 0)
return err;
- udelay(1000);
+ if (timeout-- <= 0)
+ break;
- } while (timeout--);
+ udelay(1000);
+ }
#ifdef CONFIG_MMC_TRACE
status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
int err;
struct mmc_cmd cmd;
- do {
+ while (1) {
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
if (err)
return err;
- udelay(1000);
- } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
+ if (cmd.response[0] & OCR_BUSY)
+ break;
- if (timeout <= 0)
- return UNUSABLE_ERR;
+ if (timeout-- <= 0)
+ return UNUSABLE_ERR;
+
+ udelay(1000);
+ }
if (mmc->version != SD_VERSION_2)
mmc->version = SD_VERSION_1_0;
return 0;
}
-/* We pass in the cmd since otherwise the init seems to fail */
-static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
- int use_arg)
+static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
{
+ struct mmc_cmd cmd;
int err;
- cmd->cmdidx = MMC_CMD_SEND_OP_COND;
- cmd->resp_type = MMC_RSP_R3;
- cmd->cmdarg = 0;
- if (use_arg && !mmc_host_is_spi(mmc)) {
- cmd->cmdarg =
+ cmd.cmdidx = MMC_CMD_SEND_OP_COND;
+ cmd.resp_type = MMC_RSP_R3;
+ cmd.cmdarg = 0;
+ if (use_arg && !mmc_host_is_spi(mmc))
+ cmd.cmdarg = OCR_HCS |
(mmc->cfg->voltages &
- (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
- (mmc->op_cond_response & OCR_ACCESS_MODE);
+ (mmc->ocr & OCR_VOLTAGE_MASK)) |
+ (mmc->ocr & OCR_ACCESS_MODE);
- if (mmc->cfg->host_caps & MMC_MODE_HC)
- cmd->cmdarg |= OCR_HCS;
- }
- err = mmc_send_cmd(mmc, cmd, NULL);
+ err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
- mmc->op_cond_response = cmd->response[0];
+ mmc->ocr = cmd.response[0];
return 0;
}
static int mmc_send_op_cond(struct mmc *mmc)
{
- struct mmc_cmd cmd;
int err, i;
/* Some cards seem to need this */
mmc_go_idle(mmc);
/* Asking to the card its capabilities */
- mmc->op_cond_pending = 1;
for (i = 0; i < 2; i++) {
- err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
+ err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
return err;
/* exit if not busy (flag seems to be inverted) */
- if (mmc->op_cond_response & OCR_BUSY)
- return 0;
+ if (mmc->ocr & OCR_BUSY)
+ break;
}
- return IN_PROGRESS;
+ mmc->op_cond_pending = 1;
+ return 0;
}
static int mmc_complete_op_cond(struct mmc *mmc)
int err;
mmc->op_cond_pending = 0;
- start = get_timer(0);
- do {
- err = mmc_send_op_cond_iter(mmc, &cmd, 1);
- if (err)
- return err;
- if (get_timer(start) > timeout)
- return UNUSABLE_ERR;
- udelay(100);
- } while (!(mmc->op_cond_response & OCR_BUSY));
+ if (!(mmc->ocr & OCR_BUSY)) {
+ start = get_timer(0);
+ while (1) {
+ err = mmc_send_op_cond_iter(mmc, 1);
+ if (err)
+ return err;
+ if (mmc->ocr & OCR_BUSY)
+ break;
+ if (get_timer(start) > timeout)
+ return UNUSABLE_ERR;
+ udelay(100);
+ }
+ }
if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
if (err)
return err;
+
+ mmc->ocr = cmd.response[0];
}
mmc->version = MMC_VERSION_UNKNOWN;
- mmc->ocr = cmd.response[0];
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
mmc->rca = 1;
if (err == TIMEOUT) {
err = mmc_send_op_cond(mmc);
- if (err && err != IN_PROGRESS) {
+ if (err) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("Card did not respond to voltage select!\n");
#endif
}
}
- if (err == IN_PROGRESS)
+ if (!err)
mmc->init_in_progress = 1;
return err;
{
int err = 0;
+ mmc->init_in_progress = 0;
if (mmc->op_cond_pending)
err = mmc_complete_op_cond(mmc);
mmc->has_init = 0;
else
mmc->has_init = 1;
- mmc->init_in_progress = 0;
return err;
}
int mmc_init(struct mmc *mmc)
{
- int err = IN_PROGRESS;
+ int err = 0;
unsigned start;
if (mmc->has_init)
if (!mmc->init_in_progress)
err = mmc_start_init(mmc);
- if (!err || err == IN_PROGRESS)
+ if (!err)
err = mmc_complete_init(mmc);
debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
return err;
.f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
.f_max = MVEBU_MMC_CLOCKRATE_MAX,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
- .host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HC |
+ .host_caps = MMC_MODE_4BIT | MMC_MODE_HS |
MMC_MODE_HS_52MHz,
.part_type = PART_TYPE_DOS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
- MMC_MODE_HS_52MHz | MMC_MODE_HS |
- MMC_MODE_HC;
+ MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
if (priv_data == NULL)
return -1;
- host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
- MMC_MODE_HC;
+ host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
switch (dev_index) {
case 0:
cfg->name = "S3C MMC";
cfg->ops = &s3cmmc_ops;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
- cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS;
+ cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;
cfg->f_min = 400000;
cfg->f_max = get_PCLK() / 2;
cfg->b_max = 0x80;
host->set_control_reg = &s5p_sdhci_set_control_reg;
host->set_clock = set_mmc_clk;
- host->host_caps = MMC_MODE_HC;
if (host->bus_width == 8)
host->host_caps |= MMC_MODE_8BIT;
SDHCI_BLOCK_SIZE);
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
+ } else if (cmd->resp_type & MMC_RSP_BUSY) {
+ sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
.name = DRIVER_NAME,
.ops = &sh_mmcif_ops,
.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
- MMC_MODE_8BIT | MMC_MODE_HC,
+ MMC_MODE_8BIT,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
*/
#include <common.h>
+#include <errno.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/io.h>
case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
}
- return -1;
+ return -EINVAL;
}
static int mmc_resource_init(int sdc_no)
mmchost->mmc_no = sdc_no;
cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
- if (cd_pin != -1) {
+ if (cd_pin >= 0) {
ret = gpio_request(cd_pin, "mmc_cd");
if (!ret)
ret = gpio_direction_input(cd_pin);
/* config ahb clock */
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
- defined(CONFIG_MACH_SUN9I)
+#ifdef CONFIG_SUNXI_GEN_SUN6I
/* unassert reset */
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
int cd_pin;
cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
- if (cd_pin == -1)
+ if (cd_pin < 0)
return 1;
return !gpio_get_value(cd_pin);
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
- cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+ cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->f_min = 400000;
.getcd = tegra_mmc_getcd,
};
-static int do_mmc_init(int dev_index)
+static int do_mmc_init(int dev_index, bool removable)
{
struct mmc_host *host;
struct mmc *mmc;
host->cfg.host_caps |= MMC_MODE_8BIT;
if (host->width >= 4)
host->cfg.host_caps |= MMC_MODE_4BIT;
- host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+ host->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* min freq is for card identification, and is the highest
host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
mmc = mmc_create(&host->cfg, host);
+ mmc->block_dev.removable = removable;
if (mmc == NULL)
return -1;
* @param node Device index (0-3)
* @param host Structure to fill in (reg, width, mmc_id)
*/
-static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
+static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
+ bool *removablep)
{
debug("%s: node = %d\n", __func__, node);
GPIOD_IS_IN);
gpio_request_by_name_nodev(blob, node, "power-gpios", 0,
&host->pwr_gpio, GPIOD_IS_OUT);
+ *removablep = !fdtdec_get_bool(blob, node, "non-removable");
debug("%s: found controller at %p, width = %d, periph_id = %d\n",
__func__, host->reg, host->width, host->mmc_id);
static int process_nodes(const void *blob, int node_list[], int count)
{
struct mmc_host *host;
+ bool removable;
int i, node;
debug("%s: count = %d\n", __func__, count);
host = &mmc_host[i];
host->id = i;
- if (mmc_get_config(blob, node, host)) {
+ if (mmc_get_config(blob, node, host, &removable)) {
printf("%s: failed to decode dev %d\n", __func__, i);
return -1;
}
- do_mmc_init(i);
+ do_mmc_init(i, removable);
}
return 0;
}
SDHCI_QUIRK_BROKEN_R1B;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
- host->host_caps = MMC_MODE_HC;
-
add_sdhci(host, 52000000, 52000000 >> 9);
return 0;
}
*/
#include <common.h>
+#include <dm.h>
#include <linux/err.h>
#include <malloc.h>
#include <miiphy.h>
#define EMAC_CRCERR (0x1 << 4)
#define EMAC_LENERR (0x3 << 5)
-#define DMA_CPU_TRRESHOLD 2000
+#define EMAC_RX_BUFSIZE 2000
struct emac_eth_dev {
- u32 speed;
- u32 duplex;
- u32 phy_configured;
+ struct emac_regs *regs;
+ struct mii_dev *bus;
+ struct phy_device *phydev;
int link_printed;
+#ifdef CONFIG_DM_ETH
+ uchar rx_buf[EMAC_RX_BUFSIZE];
+#endif
};
struct emac_rxhdr {
}
/* Read a word from phyxcer */
-static int emac_phy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_eth_dev *priv = bus->priv;
+ struct emac_regs *regs = priv->regs;
/* issue the phy address and reg */
writel(addr << 8 | reg, ®s->mac_madr);
/* push down the phy io line */
writel(0x0, ®s->mac_mcmd);
- /* and write data */
- *value = readl(®s->mac_mrdd);
-
- return 0;
+ /* And read data */
+ return readl(®s->mac_mrdd);
}
/* Write a word to phyxcer */
-static int emac_phy_write(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 value)
{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_eth_dev *priv = bus->priv;
+ struct emac_regs *regs = priv->regs;
/* issue the phy address and reg */
writel(addr << 8 | reg, ®s->mac_madr);
return 0;
}
-static void emac_setup(struct eth_device *dev)
+static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
+{
+ int ret, mask = 0xffffffff;
+
+#ifdef CONFIG_PHY_ADDR
+ mask = 1 << CONFIG_PHY_ADDR;
+#endif
+
+ priv->bus = mdio_alloc();
+ if (!priv->bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -ENOMEM;
+ }
+
+ priv->bus->read = emac_mdio_read;
+ priv->bus->write = emac_mdio_write;
+ priv->bus->priv = priv;
+ strcpy(priv->bus->name, "emac");
+
+ ret = mdio_register(priv->bus);
+ if (ret)
+ return ret;
+
+ priv->phydev = phy_find_by_mask(priv->bus, mask,
+ PHY_INTERFACE_MODE_MII);
+ if (!priv->phydev)
+ return -ENODEV;
+
+ phy_connect_dev(priv->phydev, dev);
+ phy_config(priv->phydev);
+
+ return 0;
+}
+
+static void emac_setup(struct emac_eth_dev *priv)
{
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_regs *regs = priv->regs;
u32 reg_val;
- u16 phy_val;
- u32 duplex_flag;
/* Set up TX */
writel(EMAC_TX_SETUP, ®s->tx_mode);
writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
/* Set MAC CTL1 */
- emac_phy_read(dev->name, 1, 0, &phy_val);
- debug("PHY SETUP, reg 0 value: %x\n", phy_val);
- duplex_flag = !!(phy_val & (1 << 8));
-
reg_val = 0;
- if (duplex_flag)
+ if (priv->phydev->duplex == DUPLEX_FULL)
reg_val = (0x1 << 0);
writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
writel(EMAC_MAC_MFL, ®s->mac_maxf);
}
-static void emac_reset(struct eth_device *dev)
+static void emac_reset(struct emac_eth_dev *priv)
{
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_regs *regs = priv->regs;
debug("resetting device\n");
udelay(200);
}
-static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
+static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
{
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
- struct emac_eth_dev *priv = dev->priv;
- u16 phy_reg;
+ struct emac_regs *regs = priv->regs;
+ int ret;
/* Init EMAC */
udelay(1);
/* Set up EMAC */
- emac_setup(dev);
+ emac_setup(priv);
- writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
- dev->enetaddr[2], ®s->mac_a1);
- writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
- dev->enetaddr[5], ®s->mac_a0);
+ writel(enetaddr[0] << 16 | enetaddr[1] << 8 | enetaddr[2],
+ ®s->mac_a1);
+ writel(enetaddr[3] << 16 | enetaddr[4] << 8 | enetaddr[5],
+ ®s->mac_a0);
mdelay(1);
- emac_reset(dev);
+ emac_reset(priv);
/* PHY POWER UP */
- emac_phy_read(dev->name, 1, 0, &phy_reg);
- emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
- mdelay(1);
-
- emac_phy_read(dev->name, 1, 0, &phy_reg);
-
- priv->speed = miiphy_speed(dev->name, 0);
- priv->duplex = miiphy_duplex(dev->name, 0);
+ ret = phy_startup(priv->phydev);
+ if (ret) {
+ printf("Could not initialize PHY %s\n",
+ priv->phydev->dev->name);
+ return ret;
+ }
/* Print link status only once */
if (!priv->link_printed) {
printf("ENET Speed is %d Mbps - %s duplex connection\n",
- priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
+ priv->phydev->speed,
+ priv->phydev->duplex ? "FULL" : "HALF");
priv->link_printed = 1;
}
/* Set EMAC SPEED depend on PHY */
- clrsetbits_le32(®s->mac_supp, 1 << 8,
- ((phy_reg & (0x1 << 13)) >> 13) << 8);
+ if (priv->phydev->speed == SPEED_100)
+ setbits_le32(®s->mac_supp, 1 << 8);
+ else
+ clrbits_le32(®s->mac_supp, 1 << 8);
/* Set duplex depend on phy */
- clrsetbits_le32(®s->mac_ctl1, 1 << 0,
- ((phy_reg & (0x1 << 8)) >> 8) << 0);
+ if (priv->phydev->duplex == DUPLEX_FULL)
+ setbits_le32(®s->mac_ctl1, 1 << 0);
+ else
+ clrbits_le32(®s->mac_ctl1, 1 << 0);
/* Enable RX/TX */
setbits_le32(®s->ctl, 0x7);
return 0;
}
-static void sunxi_emac_eth_halt(struct eth_device *dev)
-{
- /* Nothing to do here */
-}
-
-static int sunxi_emac_eth_recv(struct eth_device *dev)
+static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
{
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_regs *regs = priv->regs;
struct emac_rxhdr rxhdr;
u32 rxcount;
u32 reg_val;
/* Had one stuck? */
rxcount = readl(®s->rx_fbc);
if (!rxcount)
- return 0;
+ return -EAGAIN;
}
reg_val = readl(®s->rx_io_data);
/* Enable RX */
setbits_le32(®s->ctl, 0x1 << 2);
- return 0;
+ return -EAGAIN;
}
/* A packet ready now
/* Move data from EMAC */
if (good_packet) {
- if (rx_len > DMA_CPU_TRRESHOLD) {
+ if (rx_len > EMAC_RX_BUFSIZE) {
printf("Received packet is too big (len=%d)\n", rx_len);
- } else {
- emac_inblk_32bit((void *)®s->rx_io_data,
- net_rx_packets[0], rx_len);
-
- /* Pass to upper layer */
- net_process_received_packet(net_rx_packets[0], rx_len);
- return rx_len;
+ return -EMSGSIZE;
}
+ emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len);
+ return rx_len;
}
- return 0;
+ return -EIO; /* Bad packet */
}
-static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
+static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
+ int len)
{
- struct emac_regs *regs = (struct emac_regs *)dev->iobase;
+ struct emac_regs *regs = priv->regs;
/* Select channel 0 */
writel(0, ®s->tx_ins);
return 0;
}
-int sunxi_emac_initialize(void)
+static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
- struct emac_regs *regs =
- (struct emac_regs *)SUNXI_EMAC_BASE;
- struct eth_device *dev;
- struct emac_eth_dev *priv;
+ struct emac_regs *regs = priv->regs;
int pin;
- dev = malloc(sizeof(*dev));
- if (dev == NULL)
- return -ENOMEM;
-
- priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
- if (!priv) {
- free(dev);
- return -ENOMEM;
- }
-
- memset(dev, 0, sizeof(*dev));
- memset(priv, 0, sizeof(struct emac_eth_dev));
-
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
/* Set MII clock */
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
+}
+
+static int sunxi_emac_eth_start(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
+}
+
+static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct emac_eth_dev *priv = dev_get_priv(dev);
- dev->iobase = (int)regs;
- dev->priv = priv;
- dev->init = sunxi_emac_eth_init;
- dev->halt = sunxi_emac_eth_halt;
- dev->send = sunxi_emac_eth_send;
- dev->recv = sunxi_emac_eth_recv;
- strcpy(dev->name, "emac");
+ return _sunxi_emac_eth_send(priv, packet, length);
+}
+
+static int sunxi_emac_eth_recv(struct udevice *dev, uchar **packetp)
+{
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+ int rx_len;
- eth_register(dev);
+ rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
+ *packetp = priv->rx_buf;
- miiphy_register(dev->name, emac_phy_read, emac_phy_write);
+ return rx_len;
+}
+
+static void sunxi_emac_eth_stop(struct udevice *dev)
+{
+ /* Nothing to do here */
+}
+
+static int sunxi_emac_eth_probe(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ struct emac_eth_dev *priv = dev_get_priv(dev);
+
+ priv->regs = (struct emac_regs *)pdata->iobase;
+ sunxi_emac_board_setup(priv);
+
+ return sunxi_emac_init_phy(priv, dev);
+}
+
+static const struct eth_ops sunxi_emac_eth_ops = {
+ .start = sunxi_emac_eth_start,
+ .send = sunxi_emac_eth_send,
+ .recv = sunxi_emac_eth_recv,
+ .stop = sunxi_emac_eth_stop,
+};
+
+static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+
+ pdata->iobase = dev_get_addr(dev);
return 0;
}
+
+static const struct udevice_id sunxi_emac_eth_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-emac" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_sunxi_emac) = {
+ .name = "eth_sunxi_emac",
+ .id = UCLASS_ETH,
+ .of_match = sunxi_emac_eth_ids,
+ .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
+ .probe = sunxi_emac_eth_probe,
+ .ops = &sunxi_emac_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
struct pci_rom_data *rom_data;
u16 vendor, device;
u16 rom_vendor, rom_device;
+ u32 rom_class;
u32 vendev;
u32 mapped_vendev;
u32 rom_address;
/* Continue anyway */
}
- debug("PCI ROM image, Class Code %04x%02x, Code Type %02x\n",
- rom_data->class_hi, rom_data->class_lo, rom_data->type);
+ rom_class = (le16_to_cpu(rom_data->class_hi) << 8) | rom_data->class_lo;
+ debug("PCI ROM image, Class Code %06x, Code Type %02x\n",
+ rom_class, rom_data->type);
- if (class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
- debug("Class Code mismatch ROM %08x, dev %08x\n",
- (rom_data->class_hi << 8) | rom_data->class_lo,
- class);
+ if (class != rom_class) {
+ debug("Class Code mismatch ROM %06x, dev %06x\n",
+ rom_class, class);
}
*hdrp = rom_header;
return 0;
}
-int pci_rom_load(uint16_t class, struct pci_rom_header *rom_header,
+int pci_rom_load(struct pci_rom_header *rom_header,
struct pci_rom_header **ram_headerp)
{
struct pci_rom_data *rom_data;
{
struct pci_rom_header *rom, *ram;
int vesa_mode = -1;
- uint16_t class;
+ uint class;
bool emulate;
int ret;
/* Only execute VGA ROMs */
- pci_read_config_word(dev, PCI_CLASS_DEVICE, &class);
- if ((class ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
+ pci_read_config_dword(dev, PCI_REVISION_ID, &class);
+ if (((class >> 16) ^ PCI_CLASS_DISPLAY_VGA) & 0xff00) {
debug("%s: Class %#x, should be %#x\n", __func__, class,
PCI_CLASS_DISPLAY_VGA);
return -ENODEV;
}
+ class >>= 8;
if (!should_load_oprom(dev))
return -ENXIO;
if (ret)
return ret;
- ret = pci_rom_load(class, rom, &ram);
+ ret = pci_rom_load(rom, &ram);
if (ret)
return ret;
return v & AXP209_IRQ5_PEK_DOWN;
}
-
-static u8 axp209_get_gpio_ctrl_reg(unsigned int pin)
-{
- switch (pin) {
- case 0: return AXP209_GPIO0_CTRL;
- case 1: return AXP209_GPIO1_CTRL;
- case 2: return AXP209_GPIO2_CTRL;
- case 3: return AXP209_GPIO3_CTRL;
- }
- return 0;
-}
-
-int axp_gpio_direction_input(unsigned int pin)
-{
- if (pin == SUNXI_GPIO_AXP0_VBUS_DETECT)
- return 0;
-
- u8 reg = axp209_get_gpio_ctrl_reg(pin);
- /* GPIO3 is "special" */
- u8 val = (pin == 3) ? AXP209_GPIO3_INPUT : AXP209_GPIO_INPUT;
-
- return axp209_write(reg, val);
-}
-
-int axp_gpio_direction_output(unsigned int pin, unsigned int val)
-{
- u8 reg = axp209_get_gpio_ctrl_reg(pin);
-
- if (val) {
- val = (pin == 3) ? AXP209_GPIO3_OUTPUT_HIGH :
- AXP209_GPIO_OUTPUT_HIGH;
- } else {
- val = (pin == 3) ? AXP209_GPIO3_OUTPUT_LOW :
- AXP209_GPIO_OUTPUT_LOW;
- }
-
- return axp209_write(reg, val);
-}
-
-int axp_gpio_get_value(unsigned int pin)
-{
- u8 val, mask;
- int rc;
-
- if (pin == SUNXI_GPIO_AXP0_VBUS_DETECT) {
- rc = axp209_read(AXP209_POWER_STATUS, &val);
- mask = AXP209_POWER_STATUS_VBUS_USABLE;
- } else if (pin == 3) {
- rc = axp209_read(AXP209_GPIO3_CTRL, &val);
- mask = 1;
- } else {
- rc = axp209_read(AXP209_GPIO_STATE, &val);
- mask = 1 << (pin + 4);
- }
- if (rc)
- return rc;
-
- return (val & mask) ? 1 : 0;
-}
-
-int axp_gpio_set_value(unsigned int pin, unsigned int val)
-{
- return axp_gpio_direction_output(pin, val);
-}
#include <common.h>
#include <errno.h>
-#include <asm/arch/p2wi.h>
-#include <asm/arch/rsb.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
#include <axp221.h>
-/*
- * The axp221 uses the p2wi bus, the axp223 is identical (for all registers
- * used sofar) but uses the rsb bus. These functions abstract this.
- */
-static int pmic_bus_init(void)
-{
-#ifdef CONFIG_MACH_SUN6I
- p2wi_init();
- return p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
- AXP221_INIT_DATA);
-#else
- int ret;
-
- ret = rsb_init();
- if (ret)
- return ret;
-
- return rsb_set_device_address(AXP223_DEVICE_ADDR, AXP223_RUNTIME_ADDR);
-#endif
-}
-
-static int pmic_bus_read(const u8 addr, u8 *data)
-{
-#ifdef CONFIG_MACH_SUN6I
- return p2wi_read(addr, data);
-#else
- return rsb_read(AXP223_RUNTIME_ADDR, addr, data);
-#endif
-}
-
-static int pmic_bus_write(const u8 addr, u8 data)
-{
-#ifdef CONFIG_MACH_SUN6I
- return p2wi_write(addr, data);
-#else
- return rsb_write(AXP223_RUNTIME_ADDR, addr, data);
-#endif
-}
-
static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
{
if (mvolt < min)
return (mvolt - min) / div;
}
-static int axp221_setbits(u8 reg, u8 bits)
-{
- int ret;
- u8 val;
-
- ret = pmic_bus_read(reg, &val);
- if (ret)
- return ret;
-
- val |= bits;
- return pmic_bus_write(reg, val);
-}
-
-static int axp221_clrbits(u8 reg, u8 bits)
-{
- int ret;
- u8 val;
-
- ret = pmic_bus_read(reg, &val);
- if (ret)
- return ret;
-
- val &= ~bits;
- return pmic_bus_write(reg, val);
-}
-
int axp221_set_dcdc1(unsigned int mvolt)
{
int ret;
u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC1_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC1_EN);
ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg);
if (ret)
return ret;
- ret = axp221_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DCDC1SW_EN);
+ ret = pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DCDC1SW_EN);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC1_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC1_EN);
}
int axp221_set_dcdc2(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC2_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC2_EN);
ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC2_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC2_EN);
}
int axp221_set_dcdc3(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC3_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC3_EN);
ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC3_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC3_EN);
}
int axp221_set_dcdc4(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC4_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC4_EN);
ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC4_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC4_EN);
}
int axp221_set_dcdc5(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC5_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC5_EN);
ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_DCDC5_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_DCDC5_EN);
}
int axp221_set_dldo1(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO1_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO1_EN);
ret = pmic_bus_write(AXP221_DLDO1_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO1_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO1_EN);
}
int axp221_set_dldo2(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO2_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO2_EN);
ret = pmic_bus_write(AXP221_DLDO2_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO2_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO2_EN);
}
int axp221_set_dldo3(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO3_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO3_EN);
ret = pmic_bus_write(AXP221_DLDO3_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO3_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO3_EN);
}
int axp221_set_dldo4(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO4_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO4_EN);
ret = pmic_bus_write(AXP221_DLDO4_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL2,
- AXP221_OUTPUT_CTRL2_DLDO4_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO4_EN);
}
int axp221_set_aldo1(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_ALDO1_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO1_EN);
ret = pmic_bus_write(AXP221_ALDO1_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_ALDO1_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO1_EN);
}
int axp221_set_aldo2(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_ALDO2_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO2_EN);
ret = pmic_bus_write(AXP221_ALDO2_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL1,
- AXP221_OUTPUT_CTRL1_ALDO2_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO2_EN);
}
int axp221_set_aldo3(unsigned int mvolt)
u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL3,
- AXP221_OUTPUT_CTRL3_ALDO3_EN);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL3,
+ AXP221_OUTPUT_CTRL3_ALDO3_EN);
ret = pmic_bus_write(AXP221_ALDO3_CTRL, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL3,
- AXP221_OUTPUT_CTRL3_ALDO3_EN);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL3,
+ AXP221_OUTPUT_CTRL3_ALDO3_EN);
}
int axp221_set_eldo(int eldo_num, unsigned int mvolt)
}
if (mvolt == 0)
- return axp221_clrbits(AXP221_OUTPUT_CTRL2, bits);
+ return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, bits);
ret = pmic_bus_write(addr, cfg);
if (ret)
return ret;
- return axp221_setbits(AXP221_OUTPUT_CTRL2, bits);
+ return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits);
}
int axp221_init(void)
return 0;
}
-
-int axp_gpio_direction_input(unsigned int pin)
-{
- switch (pin) {
- case SUNXI_GPIO_AXP0_VBUS_DETECT:
- return 0;
- default:
- return -EINVAL;
- }
-}
-
-int axp_gpio_direction_output(unsigned int pin, unsigned int val)
-{
- int ret;
-
- switch (pin) {
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- ret = axp221_clrbits(AXP221_MISC_CTRL,
- AXP221_MISC_CTRL_N_VBUSEN_FUNC);
- if (ret)
- return ret;
-
- return axp_gpio_set_value(pin, val);
- default:
- return -EINVAL;
- }
-}
-
-int axp_gpio_get_value(unsigned int pin)
-{
- int ret;
- u8 val;
-
- switch (pin) {
- case SUNXI_GPIO_AXP0_VBUS_DETECT:
- ret = pmic_bus_read(AXP221_POWER_STATUS, &val);
- if (ret)
- return ret;
-
- return !!(val & AXP221_POWER_STATUS_VBUS_AVAIL);
- default:
- return -EINVAL;
- }
-}
-
-int axp_gpio_set_value(unsigned int pin, unsigned int val)
-{
- int ret;
-
- switch (pin) {
- case SUNXI_GPIO_AXP0_VBUS_ENABLE:
- if (val)
- ret = axp221_setbits(AXP221_VBUS_IPSOUT,
- AXP221_VBUS_IPSOUT_DRIVEBUS);
- else
- ret = axp221_clrbits(AXP221_VBUS_IPSOUT,
- AXP221_VBUS_IPSOUT_DRIVEBUS);
-
- if (ret)
- return ret;
- }
-
- return 0;
-}
#include <common.h>
#include <serial.h>
-#if defined(CONFIG_CPU_V6)
+#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
/*
- * ARMV6
+ * ARMV6 & ARMV7
*/
#define DCC_RBIT (1 << 30)
#define DCC_WBIT (1 << 29)
/*
- * Copyright (C) 2014 Roman Byshko
+ * Sunxi ehci glue
*
- * Roman Byshko <rbyshko@gmail.com>
+ * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
+ * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
*
* Based on code from
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <asm/arch/usbc.h>
#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/usb_phy.h>
+#include <asm/io.h>
#include "ehci.h"
int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
struct ehci_hcor **hcor)
{
- int err;
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int ahb_gate_offset;
- err = sunxi_usbc_request_resources(index + 1);
- if (err)
- return err;
+ ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 :
+ AHB_GATE_OFFSET_USB_EHCI0;
+ setbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset);
+#endif
- sunxi_usbc_enable(index + 1);
- sunxi_usbc_vbus_enable(index + 1);
+ sunxi_usb_phy_init(index + 1);
+ sunxi_usb_phy_power_on(index + 1);
- *hccr = sunxi_usbc_get_io_base(index + 1);
+ if (index == 0)
+ *hccr = (void *)SUNXI_USB1_BASE;
+ else
+ *hccr = (void *)SUNXI_USB2_BASE;
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
int ehci_hcd_stop(int index)
{
- sunxi_usbc_vbus_disable(index + 1);
- sunxi_usbc_disable(index + 1);
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int ahb_gate_offset;
- return sunxi_usbc_free_resources(index + 1);
+ sunxi_usb_phy_power_off(index + 1);
+ sunxi_usb_phy_exit(index + 1);
+
+ ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 :
+ AHB_GATE_OFFSET_USB_EHCI0;
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset);
+#endif
+ clrbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset);
+
+ return 0;
}
static inline u8 musb_read_configdata(void __iomem *mbase)
{
+#ifdef CONFIG_MACH_SUN8I_A33
+ /* <Sigh> allwinner saves a reg, and we need to hardcode this */
+ return 0xde;
+#else
musb_writeb(mbase, MUSB_INDEX, 0);
return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
+#endif
}
static inline u16 musb_read_hwvers(void __iomem *mbase)
#include <common.h>
#include <watchdog.h>
#ifdef CONFIG_ARCH_SUNXI
-#include <asm/arch/usbc.h>
+#include <asm/arch/usb_phy.h>
#endif
#include <asm/errno.h>
#include <linux/usb/ch9.h>
* when clearing reset on low-speed devices, temporary disable
* squelch detection to work around this.
*/
- sunxi_usbc_enable_squelch_detect(0, 0);
+ sunxi_usb_phy_enable_squelch_detect(0, 0);
#endif
power = musb_readb(mbase, MUSB_POWER);
musb_writeb(mbase, MUSB_POWER, ~MUSB_POWER_RESET & power);
#ifdef CONFIG_ARCH_SUNXI
- sunxi_usbc_enable_squelch_detect(0, 1);
+ sunxi_usb_phy_enable_squelch_detect(0, 1);
#endif
host->isr(0, host);
host_speed = (musb_readb(mbase, MUSB_POWER) & MUSB_POWER_HSMODE) ?
*/
#include <common.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/usbc.h>
+#include <asm/arch/usb_phy.h>
#include <asm-generic/gpio.h>
#include "linux-compat.h"
#include "musb_core.h"
if (is_host_enabled(musb)) {
/* port power on */
- sunxi_usbc_vbus_enable(0);
+ sunxi_usb_phy_power_on(0);
}
}
static void sunxi_musb_disable(struct musb *musb)
{
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
pr_debug("%s():\n", __func__);
/* Put the controller back in a pristane state for "usb reset" */
if (musb->is_active) {
- sunxi_usbc_disable(0);
- sunxi_usbc_enable(0);
+ sunxi_usb_phy_exit(0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+ clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+
+ mdelay(10);
+
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+ sunxi_usb_phy_init(0);
musb->is_active = 0;
}
}
static int sunxi_musb_init(struct musb *musb)
{
+ struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int err;
pr_debug("%s():\n", __func__);
- err = sunxi_usbc_request_resources(0);
- if (err)
- return err;
-
if (is_host_enabled(musb)) {
- err = sunxi_usbc_vbus_detect(0);
+ err = sunxi_usb_phy_vbus_detect(0);
if (err) {
eprintf("Error: A charger is plugged into the OTG\n");
- sunxi_usbc_free_resources(0);
return -EIO;
}
}
musb->isr = sunxi_musb_interrupt;
- sunxi_usbc_enable(0);
+
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
+#ifdef CONFIG_SUNXI_GEN_SUN6I
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
+#endif
+ sunxi_usb_phy_init(0);
USBC_ConfigFIFO_Base();
USBC_EnableDpDmPullUp(musb->mregs);
USBC_DisableDpDmPullUp(musb->mregs);
USBC_DisableIdPullUp(musb->mregs);
- sunxi_usbc_vbus_disable(0);
- sunxi_usbc_disable(0);
+ sunxi_usb_phy_power_off(0);
+ sunxi_usb_phy_exit(0);
- return sunxi_usbc_free_resources(0);
+ return 0;
}
const struct musb_platform_ops sunxi_musb_ops = {
CCM_HDMI_CTRL_PLL3);
/* Set ahb gating to pass */
-#ifdef CONFIG_MACH_SUN6I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
#endif
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-#ifdef CONFIG_MACH_SUN6I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
#endif
clock_set_pll3(0);
sunxi_frontend_init();
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
/* Reset off */
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
#endif
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
/* Reset off */
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
#else
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
* white while the lcd inits.
*/
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "lcd_backlight_enable");
gpio_direction_output(pin, 0);
}
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "lcd_backlight_pwm");
gpio_direction_output(pin, PWM_OFF);
}
reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_RESET);
- if (reset_pin != -1) {
+ if (reset_pin >= 0) {
gpio_request(reset_pin, "lcd_reset");
gpio_direction_output(reset_pin, 0); /* Assert reset */
}
/* Give the backlight some time to turn off and power up the panel. */
mdelay(40);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "lcd_power");
gpio_direction_output(pin, 1);
}
- if (reset_pin != -1)
+ if (reset_pin >= 0)
gpio_direction_output(reset_pin, 1); /* De-assert reset */
}
mdelay(40);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
- if (pin != -1)
+ if (pin >= 0)
gpio_direction_output(pin, 1);
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
- if (pin != -1)
+ if (pin >= 0)
gpio_direction_output(pin, PWM_ON);
}
static void sunxi_drc_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#ifdef CONFIG_SUNXI_GEN_SUN6I
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* On sun6i the drc must be clocked even when in pass-through mode */
+#ifdef CONFIG_MACH_SUN8I_A33
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
+#endif
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
#endif
int pin;
pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
- if (pin != -1) {
+ if (pin >= 0) {
gpio_request(pin, "vga_enable");
gpio_direction_output(pin, 1);
}
#define AXP152_POWEROFF (1 << 7)
+/* For axp_gpio.c */
+#define AXP_GPIO0_CTRL 0x90
+#define AXP_GPIO1_CTRL 0x91
+#define AXP_GPIO2_CTRL 0x92
+#define AXP_GPIO3_CTRL 0x93
+#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
+#define AXP_GPIO_STATE 0x97
+#define AXP_GPIO_STATE_OFFSET 0
+
int axp152_set_dcdc2(int mvolt);
int axp152_set_dcdc3(int mvolt);
int axp152_set_dcdc4(int mvolt);
AXP209_IRQ_ENABLE5 = 0x44,
AXP209_IRQ_STATUS5 = 0x4c,
AXP209_SHUTDOWN = 0x32,
- AXP209_GPIO0_CTRL = 0x90,
- AXP209_GPIO1_CTRL = 0x92,
- AXP209_GPIO2_CTRL = 0x93,
- AXP209_GPIO_STATE = 0x94,
- AXP209_GPIO3_CTRL = 0x95,
};
#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
#define AXP209_POWEROFF (1 << 7)
-#define AXP209_GPIO_OUTPUT_LOW 0x00 /* Drive pin low */
-#define AXP209_GPIO_OUTPUT_HIGH 0x01 /* Drive pin high */
-#define AXP209_GPIO_INPUT 0x02 /* Float pin */
-
-/* GPIO3 is different from the others */
-#define AXP209_GPIO3_OUTPUT_LOW 0x00 /* Drive pin low, Output mode */
-#define AXP209_GPIO3_OUTPUT_HIGH 0x02 /* Float pin, Output mode */
-#define AXP209_GPIO3_INPUT 0x06 /* Float pin, Input mode */
-
-#define AXP_GPIO
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS 0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_GPIO0_CTRL 0x90
+#define AXP_GPIO1_CTRL 0x92
+#define AXP_GPIO2_CTRL 0x93
+#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
+#define AXP_GPIO_STATE 0x94
+#define AXP_GPIO_STATE_OFFSET 4
extern int axp209_set_dcdc2(int mvolt);
extern int axp209_set_dcdc3(int mvolt);
extern int axp209_init(void);
extern int axp209_poweron_by_dc(void);
extern int axp209_power_button(void);
-
-extern int axp_gpio_direction_input(unsigned int pin);
-extern int axp_gpio_direction_output(unsigned int pin, unsigned int val);
-extern int axp_gpio_get_value(unsigned int pin);
-extern int axp_gpio_set_value(unsigned int pin, unsigned int val);
* SPDX-License-Identifier: GPL-2.0+
*/
-#define AXP221_CHIP_ADDR 0x68
-#define AXP221_CTRL_ADDR 0x3e
-#define AXP221_INIT_DATA 0x3e
-
-#define AXP223_DEVICE_ADDR 0x3a3
-#define AXP223_RUNTIME_ADDR 0x2d
-
/* Page 0 addresses */
-#define AXP221_POWER_STATUS 0x00
-#define AXP221_POWER_STATUS_VBUS_AVAIL (1 << 5)
-#define AXP221_POWER_STATUS_VBUS_USABLE (1 << 4)
#define AXP221_CHIP_ID 0x03
#define AXP221_OUTPUT_CTRL1 0x10
#define AXP221_OUTPUT_CTRL1_DCDC0_EN (1 << 0)
/* Page 1 addresses */
#define AXP221_SID 0x20
-#define AXP_GPIO
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS 0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
+#define AXP_GPIO0_CTRL 0x90
+#define AXP_GPIO1_CTRL 0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT 0x02 /* Input */
+#define AXP_GPIO_STATE 0x94
+#define AXP_GPIO_STATE_OFFSET 0
int axp221_set_dcdc1(unsigned int mvolt);
int axp221_set_dcdc2(unsigned int mvolt);
int axp221_set_eldo(int eldo_num, unsigned int mvolt);
int axp221_init(void);
int axp221_get_sid(unsigned int *sid);
-
-int axp_gpio_direction_input(unsigned int pin);
-int axp_gpio_direction_output(unsigned int pin, unsigned int val);
-int axp_gpio_get_value(unsigned int pin);
-int axp_gpio_set_value(unsigned int pin, unsigned int val);
/* */
phys_size_t initdram (int);
-int display_options (void);
-/**
- * print_size() - Print a size with a suffic
- *
- * print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
- * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
- * (like "\n")
- *
- * @size: Size to print
- * @suffix String to print after the size
- */
-void print_size(uint64_t size, const char *suffix);
-
-int print_buffer(ulong addr, const void *data, uint width, uint count,
- uint linelen);
+#include <display_options.h>
/* common/main.c */
void main_loop (void);
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
+#define CONFIG_ENV_SECT_SIZE 0x1000
+#define CONFIG_ENV_OFFSET 0x003f8000
+
#endif /* __CONFIG_H */
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
#define CONFIG_NR_DRAM_BANKS 1
#undef CONFIG_CFB_CONSOLE
/* Environment configuration */
-#undef CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
--- /dev/null
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_88F6820_GP_H
+#define _CONFIG_DB_88F6820_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_ARMADA_XP /* SOC Family Name */
+#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */
+
+#define CONFIG_SYS_L2_PL310
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE 0x04000000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 1000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define CONFIG_PHY_ADDR { 1, 0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_88F6820_GP_H */
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR 0x10
+#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_PHYLIB
/* Environment configuration */
-#undef CONFIG_ENV_IS_NOWHERE
-#undef CONFIG_ENV_SIZE
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR 0x0
+#define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
#define CONFIG_RESET_PHY_R
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds"
/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}
-#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MMC
#define CONFIG_SDHCI
/* Avoid a warning in the Realtek Ethernet driver */
#define CONFIG_SYS_CACHELINE_SIZE 16
+/* Environment in SPI flash is unsupported for now */
+#undef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+
#endif /* __CONFIG_H */
115200,230400, 460800, 921600 }
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+#define CONFIG_PREBOOT
/*
* For booting Linux, the board info and command line data
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
+#define CONFIG_SUNXI_USB_PHYS 3
+
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
+#define CONFIG_SUNXI_USB_PHYS 2
+
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
+#define CONFIG_SUNXI_USB_PHYS 3
+
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#endif
+#define CONFIG_SUNXI_USB_PHYS 3
+
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_TIMER_CLK_FREQ 24000000
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
+#define CONFIG_SUNXI_USB_PHYS 2
+
/*
* Include common sunxi configuration where most the settings are
*/
#define CONFIG_SYS_TEXT_BASE 0x4a000000
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
# define CONFIG_DW_SERIAL
#endif
#define CONFIG_SPL_I2C_SUPPORT
#endif
-#define CONFIG_SYS_I2C
#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
defined CONFIG_I2C4_ENABLE
+#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
-#endif
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_CMD_I2C
+#endif
#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */
#endif
-#define CONFIG_CMD_I2C
-
/* PMU */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
#define CONFIG_SPL_POWER_SUPPORT
/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
+#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
+#define CONFIG_PHYLIB
#endif
#ifdef CONFIG_SUNXI_GMAC
#define CONFIG_EXTRA_ENV_SETTINGS \
CONSOLE_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
- "fdtfile=" CONFIG_FDTFILE "\0" \
+ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"console=ttyS0,115200\0" \
BOOTENV
#define CONFIG_PHYSMEM
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_LAST_STAGE_INIT
#define CONFIG_LMB
#define CONFIG_OF_LIBFDT
/*-----------------------------------------------------------------------
* Environment configuration
*/
-#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE 0x01000
/*-----------------------------------------------------------------------
/* DCC driver */
#if defined(CONFIG_ZYNQ_DCC)
# define CONFIG_ARM_DCC
-# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
#else
# define CONFIG_ZYNQ_SERIAL
#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CPU_H
+#define __CPU_H
+
+/**
+ * struct cpu_platdata - platform data for a CPU
+ *
+ * This can be accessed with dev_get_parent_platdata() for any UCLASS_CPU
+ * device.
+ *
+ * @cpu_id: Platform-specific way of identifying the CPU.
+ */
+struct cpu_platdata {
+ int cpu_id;
+};
+
+/* CPU features - mostly just a placeholder for now */
+enum {
+ CPU_FEAT_L1_CACHE = 0, /* Supports level 1 cache */
+ CPU_FEAT_MMU = 1, /* Supports virtual memory */
+
+ CPU_FEAT_COUNT,
+};
+
+/**
+ * struct cpu_info - Information about a CPU
+ *
+ * @cpu_freq: Current CPU frequency in Hz
+ * @features: Flags for supported CPU features
+ */
+struct cpu_info {
+ ulong cpu_freq;
+ ulong features;
+};
+
+struct cpu_ops {
+ /**
+ * get_desc() - Get a description string for a CPU
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @buf: Buffer to place string
+ * @size: Size of string space
+ * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+ int (*get_desc)(struct udevice *dev, char *buf, int size);
+
+ /**
+ * get_info() - Get information about a CPU
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @info: Returns CPU info
+ * @return 0 if OK, -ve on error
+ */
+ int (*get_info)(struct udevice *dev, struct cpu_info *info);
+};
+
+#define cpu_get_ops(dev) ((struct cpu_ops *)(dev)->driver->ops)
+
+/**
+ * cpu_get_desc() - Get a description string for a CPU
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @buf: Buffer to place string
+ * @size: Size of string space
+ * @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_get_desc(struct udevice *dev, char *buf, int size);
+
+/**
+ * cpu_get_info() - Get information about a CPU
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @info: Returns CPU info
+ * @return 0 if OK, -ve on error
+ */
+int cpu_get_info(struct udevice *dev, struct cpu_info *info);
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DISPLAY_OPTIONS_H
+#define __DISPLAY_OPTIONS_H
+
+/**
+ * print_size() - Print a size with a suffix
+ *
+ * Print sizes as "xxx KiB", "xxx.y KiB", "xxx MiB", "xxx.y MiB",
+ * xxx GiB, xxx.y GiB, etc as needed; allow for optional trailing string
+ * (like "\n")
+ *
+ * @size: Size to print
+ * @suffix String to print after the size
+ */
+void print_size(uint64_t size, const char *suffix);
+
+/**
+ * print_freq() - Print a frequency with a suffix
+ *
+ * Print frequencies as "x.xx GHz", "xxx KHz", etc as needed; allow for
+ * optional trailing string (like "\n")
+ *
+ * @freq: Frequency to print in Hz
+ * @suffix String to print after the frequency
+ */
+void print_freq(uint64_t freq, const char *suffix);
+
+/**
+ * print_buffer() - Print data buffer in hex and ascii form
+ *
+ * Data reads are buffered so that each memory address is only read once.
+ * This is useful when displaying the contents of volatile registers.
+ *
+ * @addr: Starting address to display at start of line
+ * @data: pointer to data buffer
+ * @width: data value width. May be 1, 2, or 4.
+ * @count: number of values to display
+ * @linelen: Number of values to print per line; specify 0 for default length
+ */
+int print_buffer(ulong addr, const void *data, uint width, uint count,
+ uint linelen);
+
+/**
+ * display_options() - display the version string / build tag
+ *
+ * This displays the U-Boot version string. If a build tag is available this
+ * is displayed also.
+ */
+int display_options(void);
+
+#endif
int device_bind_driver(struct udevice *parent, const char *drv_name,
const char *dev_name, struct udevice **devp);
+/**
+ * device_bind_driver_to_node() - bind a device to a driver for a node
+ *
+ * This binds a new device to a driver for a given device tree node. This
+ * should only be needed if the node lacks a compatible strings.
+ *
+ * @parent: Parent device
+ * @drv_name: Name of driver to attach to this parent
+ * @dev_name: Name of the new device thus created
+ * @node: Device tree node
+ * @devp: Returns the newly bound device
+ */
+int device_bind_driver_to_node(struct udevice *parent, const char *drv_name,
+ const char *dev_name, int node,
+ struct udevice **devp);
+
#endif
UCLASS_USB_HUB, /* USB hub */
UCLASS_USB_DEV_GENERIC, /* USB generic device */
UCLASS_MASS_STORAGE, /* Mass storage device */
+ UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_COUNT,
UCLASS_INVALID = -1,
--- /dev/null
+/*
+ * Copyright 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_
+#define __DT_BINDINGS_DMA_SUN4I_A10_H_
+
+#define SUN4I_DMA_NORMAL 0
+#define SUN4I_DMA_DEDICATED 1
+
+#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */
--- /dev/null
+/*
+ * Copyright 2014 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
+#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_
+
+#define SUN4I_PINCTRL_10_MA 0
+#define SUN4I_PINCTRL_20_MA 1
+#define SUN4I_PINCTRL_30_MA 2
+#define SUN4I_PINCTRL_40_MA 3
+
+#define SUN4I_PINCTRL_NO_PULL 0
+#define SUN4I_PINCTRL_PULL_UP 1
+#define SUN4I_PINCTRL_PULL_DOWN 2
+
+#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */
--- /dev/null
+/*
+ * This header provides constants for most thermal bindings.
+ *
+ * Copyright (C) 2013 Texas Instruments
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef _DT_BINDINGS_THERMAL_THERMAL_H
+#define _DT_BINDINGS_THERMAL_THERMAL_H
+
+/* On cooling devices upper and lower limits */
+#define THERMAL_NO_LIMIT (~0)
+
+#endif
+
#define MMC_MODE_4BIT (1 << 2)
#define MMC_MODE_8BIT (1 << 3)
#define MMC_MODE_SPI (1 << 4)
-#define MMC_MODE_HC (1 << 5)
-#define MMC_MODE_DDR_52MHz (1 << 6)
+#define MMC_MODE_DDR_52MHz (1 << 5)
#define SD_DATA_4BIT 0x00040000
#define IS_SD(x) ((x)->version & SD_VERSION_SD)
-#define IS_MMC(x) ((x)->version & SD_VERSION_MMC)
+#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
#define MMC_DATA_READ 1
#define MMC_DATA_WRITE 2
#define UNUSABLE_ERR -17 /* Unusable Card */
#define COMM_ERR -18 /* Communications Error */
#define TIMEOUT -19
-#define IN_PROGRESS -20 /* operation is in progress */
-#define SWITCH_ERR -21 /* Card reports failure to switch mode */
+#define SWITCH_ERR -20 /* Card reports failure to switch mode */
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
char op_cond_pending; /* 1 if we are waiting on an op_cond command */
char init_in_progress; /* 1 if we have done mmc_start_init() */
char preinit; /* start init as early as possible */
- uint op_cond_response; /* the response byte from the last op_cond */
int ddr_mode;
};
int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
-int sunxi_emac_initialize(bd_t *bis);
-int sunxi_gmac_initialize(bd_t *bis);
int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
*
* @dev: High 8 bits = Super I/O port, low 8 bits = logical device number.
* @iobase: Processor I/O port address to assign to this serial device.
+ * @irq: Processor IRQ number to assign to this serial device.
*/
-void lpc47m_enable_serial(u16 dev, u16 iobase);
+void lpc47m_enable_serial(u16 dev, u16 iobase, u8 irq);
#endif /* _SMSC_LPC47M_H_ */
#include <config.h>
#include <common.h>
+#include <div64.h>
#include <inttypes.h>
#include <version.h>
#include <linux/ctype.h>
return 0;
}
+void print_freq(uint64_t freq, const char *s)
+{
+ unsigned long m = 0, n;
+ uint32_t f;
+ static const char names[] = {'G', 'M', 'K'};
+ unsigned long d = 1e9;
+ char c = 0;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(names); i++, d /= 1000) {
+ if (freq >= d) {
+ c = names[i];
+ break;
+ }
+ }
+
+ if (!c) {
+ printf("%" PRIu64 " Hz%s", freq, s);
+ return;
+ }
+
+ f = do_div(freq, d);
+ n = freq;
+
+ /* If there's a remainder, show the first few digits */
+ if (f) {
+ m = f;
+ while (m > 1000)
+ m /= 10;
+ while (m && !(m % 10))
+ m /= 10;
+ if (m >= 100)
+ m = (m / 10) + (m % 100 >= 50);
+ }
+
+ printf("%lu", n);
+ if (m)
+ printf(".%ld", m);
+ printf(" %cHz%s", c, s);
+}
+
void print_size(uint64_t size, const char *s)
{
unsigned long m = 0, n;
printf (" %ciB%s", c, s);
}
-/*
- * Print data buffer in hex and ascii form to the terminal.
- *
- * data reads are buffered so that each memory address is only read once.
- * Useful when displaying the contents of volatile registers.
- *
- * parameters:
- * addr: Starting address to display at start of line
- * data: pointer to data buffer
- * width: data value width. May be 1, 2, or 4.
- * count: number of values to display
- * linelen: Number of values to print per line; specify 0 for default length
- */
#define MAX_LINE_LENGTH_BYTES (64)
#define DEFAULT_LINE_LENGTH_BYTES (16)
int print_buffer(ulong addr, const void *data, uint width, uint count,
projects / oweals / u-boot.git / commitdiff