This provides an SPL_SIZE_LIMIT that makes the build check that the SPL
binary loaded from flash fits into the SRAM (64 KiB) and leaves enough
room for global data, heap and stack (512 bytes assumed stack usage).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
config NR_DRAM_BANKS
default 1
+config SPL_SIZE_LIMIT
+ default 65536 if TARGET_SOCFPGA_GEN5
+
+config SPL_SIZE_LIMIT_PROVIDE_STACK
+ default 0x200 if TARGET_SOCFPGA_GEN5
+
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
bool
select SPL_ALTERA_SDRAM
imply FPGA_SOCFPGA
+ imply SPL_SIZE_LIMIT_SUBTRACT_GD
+ imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
imply SPL_STACK_R
imply SPL_SYS_MALLOC_SIMPLE
imply USE_TINY_PRINTF