arm: vf610: add NAND support for vf610twr
authorStefan Agner <stefan@agner.ch>
Fri, 12 Sep 2014 11:06:36 +0000 (13:06 +0200)
committerStefano Babic <sbabic@denx.de>
Tue, 16 Sep 2014 11:25:45 +0000 (13:25 +0200)
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).

Signed-off-by: Stefan Agner <stefan@agner.ch>
board/freescale/vf610twr/vf610twr.c
configs/vf610twr_defconfig
configs/vf610twr_nand_defconfig [new file with mode: 0644]
include/configs/vf610twr.h

index 54a9f2c7c35d122a050e3f67b41be7dd4b052b24..4d0979632a0b90f7ccef5e671dab5a6dfaaf74c7 100644 (file)
@@ -278,6 +278,39 @@ static void setup_iomux_i2c(void)
        imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 }
 
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+       static const iomux_v3_cfg_t nfc_pads[] = {
+               VF610_PAD_PTD31__NF_IO15,
+               VF610_PAD_PTD30__NF_IO14,
+               VF610_PAD_PTD29__NF_IO13,
+               VF610_PAD_PTD28__NF_IO12,
+               VF610_PAD_PTD27__NF_IO11,
+               VF610_PAD_PTD26__NF_IO10,
+               VF610_PAD_PTD25__NF_IO9,
+               VF610_PAD_PTD24__NF_IO8,
+               VF610_PAD_PTD23__NF_IO7,
+               VF610_PAD_PTD22__NF_IO6,
+               VF610_PAD_PTD21__NF_IO5,
+               VF610_PAD_PTD20__NF_IO4,
+               VF610_PAD_PTD19__NF_IO3,
+               VF610_PAD_PTD18__NF_IO2,
+               VF610_PAD_PTD17__NF_IO1,
+               VF610_PAD_PTD16__NF_IO0,
+               VF610_PAD_PTB24__NF_WE_B,
+               VF610_PAD_PTB25__NF_CE0_B,
+               VF610_PAD_PTB27__NF_RE_B,
+               VF610_PAD_PTC26__NF_RB_B,
+               VF610_PAD_PTC27__NF_ALE,
+               VF610_PAD_PTC28__NF_CLE
+       };
+
+       imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+
 static void setup_iomux_qspi(void)
 {
        static const iomux_v3_cfg_t qspi0_pads[] = {
@@ -354,6 +387,8 @@ static void clock_init(void)
                CCM_CCGR7_SDHC1_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
                CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+               CCM_CCGR10_NFC_CTRL_MASK);
 
        clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
                ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
@@ -373,14 +408,17 @@ static void clock_init(void)
                CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
                CCM_CACRR_ARM_CLK_DIV(0));
        clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
-               CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
+               CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+               CCM_CSCMR1_NFC_CLK_SEL(0));
        clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
                CCM_CSCDR1_RMII_CLK_EN);
        clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
-               CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+               CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+               CCM_CSCDR2_NFC_EN);
        clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
                CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
-               CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
+               CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
+               CCM_CSCDR3_NFC_PRE_DIV(5));
        clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
                CCM_CSCMR2_RMII_CLK_SEL(0));
 }
@@ -411,6 +449,9 @@ int board_early_init_f(void)
        setup_iomux_enet();
        setup_iomux_i2c();
        setup_iomux_qspi();
+#ifdef CONFIG_NAND_VF610_NFC
+       setup_iomux_nfc();
+#endif
 
        return 0;
 }
index 10e6432bb4a7ad923ba917c0ac9e960bd799cec1..7de374a406405725071158faf7ef7b67c9cb42bb 100644 (file)
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
 CONFIG_ARM=y
 CONFIG_TARGET_VF610TWR=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
new file mode 100644 (file)
index 0000000..e78db26
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_ARM=y
+CONFIG_TARGET_VF610TWR=y
index 034255041226079f5078e6f2d16d6f502c08eab0..6fd0b173ebb9a1a45f2a514bdb9b6eff3eee8b45 100644 (file)
@@ -14,6 +14,7 @@
 
 #define CONFIG_VF610
 
+#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 
 #undef CONFIG_CMD_IMLS
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_VF610_NFC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+
+/* UBI */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT                 "nand0=fsl_nfc"
+#define MTDPARTS_DEFAULT               "mtdparts=fsl_nfc:"             \
+                                       "128k(vf-bcb)ro,"               \
+                                       "1408k(u-boot)ro,"              \
+                                       "512k(u-boot-env),"             \
+                                       "4m(kernel),"                   \
+                                       "512k(fdt),"            \
+                                       "-(rootfs)"
+#endif
+
 #define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#ifdef CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_SIZE                        (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
 
 #define CONFIG_ENV_OFFSET              (12 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV         0
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                        (64 * 2048)
+#define CONFIG_ENV_SECT_SIZE           (64 * 2048)
+#define CONFIG_ENV_RANGE               (512 * 1024)
+#define CONFIG_ENV_OFFSET              0x180000
+#endif
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ