rockchip: sdram: move cap structure and debug function to sdram_common.h
authorKever Yang <kever.yang@rock-chips.com>
Fri, 15 Nov 2019 03:04:34 +0000 (11:04 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Sun, 17 Nov 2019 08:23:56 +0000 (16:23 +0800)
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/include/asm/arch-rockchip/sdram.h
arch/arm/include/asm/arch-rockchip/sdram_common.h [new file with mode: 0644]
arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h

index f3933f35982a622150dd65c05b12b2a12e24119c..01fc353d819e9e408022cd4e402e030a75d8afbc 100644 (file)
@@ -15,34 +15,6 @@ enum {
        UNUSED = 0xFF
 };
 
-struct sdram_cap_info {
-       unsigned int rank;
-       /* dram column number, 0 means this channel is invalid */
-       unsigned int col;
-       /* dram bank number, 3:8bank, 2:4bank */
-       unsigned int bk;
-       /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
-       unsigned int bw;
-       /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
-       unsigned int dbw;
-       /*
-        * row_3_4 = 1: 6Gb or 12Gb die
-        * row_3_4 = 0: normal die, power of 2
-        */
-       unsigned int row_3_4;
-       unsigned int cs0_row;
-       unsigned int cs1_row;
-       unsigned int ddrconfig;
-};
-
-struct sdram_base_params {
-       unsigned int ddr_freq;
-       unsigned int dramtype;
-       unsigned int num_channels;
-       unsigned int stride;
-       unsigned int odt;
-};
-
 /*
  * sys_reg bitfield struct
  * [31]                row_3_4_ch1
@@ -124,24 +96,4 @@ size_t rockchip_sdram_size(phys_addr_t reg);
 /* Called by U-Boot board_init_r for Rockchip SoCs */
 int dram_init(void);
 
-#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
-inline void sdram_print_dram_type(unsigned char dramtype)
-{
-}
-
-inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
-                                struct sdram_base_params *base)
-{
-}
-
-inline void sdram_print_stride(unsigned int stride)
-{
-}
-#else
-void sdram_print_dram_type(unsigned char dramtype);
-void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
-                         struct sdram_base_params *base);
-void sdram_print_stride(unsigned int stride);
-#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
-
 #endif
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
new file mode 100644 (file)
index 0000000..8d771ce
--- /dev/null
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef _ASM_ARCH_SDRAM_COMMON_H
+#define _ASM_ARCH_SDRAM_COMMON_H
+
+struct sdram_cap_info {
+       unsigned int rank;
+       /* dram column number, 0 means this channel is invalid */
+       unsigned int col;
+       /* dram bank number, 3:8bank, 2:4bank */
+       unsigned int bk;
+       /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+       unsigned int bw;
+       /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+       unsigned int dbw;
+       /*
+        * row_3_4 = 1: 6Gb or 12Gb die
+        * row_3_4 = 0: normal die, power of 2
+        */
+       unsigned int row_3_4;
+       unsigned int cs0_row;
+       unsigned int cs1_row;
+       unsigned int cs0_high16bit_row;
+       unsigned int cs1_high16bit_row;
+       unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+       unsigned int ddr_freq;
+       unsigned int dramtype;
+       unsigned int num_channels;
+       unsigned int stride;
+       unsigned int odt;
+};
+
+#if !defined(CONFIG_RAM_ROCKCHIP_DEBUG)
+inline void sdram_print_dram_type(unsigned char dramtype)
+{
+}
+
+inline void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+                                struct sdram_base_params *base)
+{
+}
+
+inline void sdram_print_stride(unsigned int stride)
+{
+}
+#else
+void sdram_print_dram_type(unsigned char dramtype);
+void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
+                         struct sdram_base_params *base);
+void sdram_print_stride(unsigned int stride);
+#endif /* CONFIG_RAM_ROCKCHIP_DEBUG */
+
+#endif
index 11411ead10bde5ce458023124e290e25e36e47db..c747b461a1515ed960a56a30fef04a394e1a85a9 100644 (file)
@@ -6,6 +6,7 @@
 
 #ifndef _ASM_ARCH_SDRAM_RK3328_H
 #define _ASM_ARCH_SDRAM_RK3328_H
+#include <asm/arch-rockchip/sdram_common.h>
 
 #define SR_IDLE                93
 #define PD_IDLE                13
index dc65ae792431c3ca0409740e176a919c9420e18a..485bb3d8896eb78ad102f8eaa01a3e58c545dea7 100644 (file)
@@ -5,6 +5,7 @@
 
 #ifndef _ASM_ARCH_SDRAM_RK3399_H
 #define _ASM_ARCH_SDRAM_RK3399_H
+#include <asm/arch-rockchip/sdram_common.h>
 
 struct rk3399_ddr_pctl_regs {
        u32 denali_ctl[332];