Reset also DDR controller in AR9331 during first boot

diff --git a/u-boot/cpu/mips/ar7240/qca_gpio_init.S b/u-boot/cpu/mips/ar7240/qca_gpio_init.S
index 9009928411cccd7602dfd279eb5a86a36621cc88..41af0060653894f718d1aab9b02ed736d8b894cb 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_gpio_init.S
+++ b/u-boot/cpu/mips/ar7240/qca_gpio_init.S
@@ -467,9 +467,13 @@ first_boot:
 full_reset:
        li t8, QCA_RST_RESET_REG
        lw t9, 0(t8)
-       or t9, t9, QCA_RST_RESET_FULL_CHIP_RST_MASK
+       or t9, t9, (QCA_RST_RESET_FULL_CHIP_RST_MASK | \
+                               QCA_RST_RESET_DDR_RST_MASK)
        sw t9, 0(t8)
        nop
+       nop
+       nop
+       nop
 
        /*
         * GPIO configuration, using GPIO_FUNCTION_1 register: