#include <asm/io.h>
#include <asm/sdram.h>
+#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
.trcd = 2,
.tras = 5,
.txsr = 5,
+ /* 7.81 us */
+ .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};
int board_early_init_f(void)
#include <asm/io.h>
#include <asm/sdram.h>
+#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
.trcd = 2,
.tras = 5,
.txsr = 5,
+ /* 15.6 us */
+ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)
unsigned long bus_hz;
unsigned int i;
+ if (!info->refresh_period)
+ panic("ERROR: SDRAM refresh period == 0. "
+ "Please update the board code\n");
+
tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
| HSDRAMC1_BF(NR, info->row_bits - 11)
| HSDRAMC1_BF(NB, info->bank_bits - 1)
* 15.6 us is a typical value for a burst of length one
*/
bus_hz = get_sdram_clk_rate();
- hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000);
+ hsdramc1_writel(TR, info->refresh_period);
printf("SDRAM: %u MB at address 0x%08lx\n",
sdram_size >> 20, info->phys_addr);
}
#endif
+/* Board code may need the SDRAM base clock as a compile-time constant */
+#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
+
#endif /* __ASM_AVR32_ARCH_CLK_H__ */
unsigned long phys_addr;
unsigned int row_bits, col_bits, bank_bits;
unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+
+ /* SDRAM refresh period in cycles */
+ unsigned long refresh_period;
};
extern unsigned long sdram_init(const struct sdram_info *info);