E: ricardo.ribalda@uam.es
D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
D: Virtex ppc440 generic architecture
+D: Virtex ppc405 generic architecture
W: http://www.ii.uam.es/~rribalda
N: Stefan Roese
ml507 PPC440x5
v5fx30teval PPC440x5
xilinx-pp440-generic PPC440x5
+ xilinx-pp405-generic PPC405
Stefan Roese <sr@denx.de>
METROBOX PPC440GX
XPEDITE1K PPC440GX
+Georg Schardt <schardt@team-ctech.de>
+
+ fx12mm PPC405
+
Heiko Schocher <hs@denx.de>
ids8247 MPC8247
ebony \
ERIC \
EXBITGEN \
+ fx12mm \
G2000 \
glacier \
haleakala \
EXBITGEN_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx exbitgen
+fx12mm_flash_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+ @mkdir -p $(obj)include $(obj)board/avnet/fx12mm
+ @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
+ > $(obj)board/avnet/fx12mm/config.tmp
+ @echo "TEXT_BASE := 0xFFCB0000" \
+ >> $(obj)board/avnet/fx12mm/config.tmp
+ @$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+
+fx12mm_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+ @mkdir -p $(obj)include $(obj)board/avnet/fx12mm
+ @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
+ > $(obj)board/avnet/fx12mm/config.tmp
+ @echo "TEXT_BASE := 0x03000000" \
+ >> $(obj)board/avnet/fx12mm/config.tmp
+ @$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+
G2000_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
WUH405_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
+xilinx-ppc405-generic_flash_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+ @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds"\
+ > $(obj)board/xilinx/ppc405-generic/config.tmp
+ @echo "TEXT_BASE := 0xFE360000" \
+ >> $(obj)board/xilinx/ppc405-generic/config.tmp
+ @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+
+xilinx-ppc405-generic_config: unconfig
+ @mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
+ @echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds"\
+ > $(obj)board/xilinx/ppc405-generic/config.tmp
+ @echo "TEXT_BASE := 0x04000000" \
+ >> $(obj)board/xilinx/ppc405-generic/config.tmp
+ @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+
xilinx-ppc440-generic_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
@echo "LDSCRIPT:=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds"\
int first_free_busno=0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void
pci_init_board(void)
{
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = io_sel & 6;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to slot as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_agent = (host_agent == 6);
uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
+ struct pci_region *r = hose->regions;
if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
}
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
- }
}
#endif
--- /dev/null
+config.tmp
--- /dev/null
+#
+# (C) Copyright 2008
+# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es
+# This work has been supported by: Qtechnology http://qtec.com/
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+COBJS += $(BOARD).o
+
+include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile
--- /dev/null
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#
+
+sinclude $(SRCTREE)/board/xilinx/ppc405-generic/config.mk
--- /dev/null
+/*
+ * (C) Copyright 2008
+ *
+ * Author: Xilinx Inc.
+ *
+ * Modified by:
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+int checkboard(void)
+{
+ char tmp[64];
+ char *s, *e;
+ int i = getenv_r("serial", tmp, sizeof(tmp));
+
+ if (i < 0) {
+ printf("Avnet Virtex4 FX12 with no serial #");
+ } else {
+ for (e = tmp; *e; ++e) {
+ if (*e == ' ')
+ break;
+ }
+ printf("Avnet Virtex4 FX12 Minimodul # ");
+ for (s = tmp; s < e; ++s)
+ putc(*s);
+ }
+ putc('\n');
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2008
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * CAUTION: This file is based on the xparameters.h automatically
+ * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
+ */
+
+#ifndef __XPARAMETER_H__
+#define __XPARAMETER_H__
+
+/* RS232 */
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
+
+
+/* INT_C */
+#define XPAR_XPS_INTC_0_DEVICE_ID 0
+#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
+
+/* CPU core clock */
+#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+
+/* RAM */
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+
+/* FLASH */
+#define XPAR_FLASH_2MX16_MEM0_BASEADDR 0xFFC00000
+
+#endif
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
void
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
int pcie_configured = (io_sel == 7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = (io_sel == 2 || io_sel == 3
|| io_sel == 5 || io_sel == 7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
int pcie_configured = (io_sel == 5 || io_sel == 7);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_agent = (host_agent == 6);
uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+
#ifdef CONFIG_SYS_PCI1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE2,
CONFIG_SYS_PCI1_MEM_PHYS2,
CONFIG_SYS_PCI1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
- const char *path;
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+void ft_board_setup(void *blob, bd_t *bd)
+{
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
-#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+#ifdef CONFIG_PCIE2
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
-#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci3", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+#ifdef CONFIG_PCIE1
+ ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
#endif
- }
}
#endif
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
void
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
int pcie_configured = io_sel >= 1;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
int pcie_configured = io_sel & 6;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE2,
CONFIG_SYS_PCIE1_MEM_PHYS2,
CONFIG_SYS_PCIE1_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
int pcie_configured = io_sel & 4;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE2,
CONFIG_SYS_PCIE2_MEM_PHYS2,
CONFIG_SYS_PCIE2_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_agent = (host_agent == 6);
uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+
#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE2,
CONFIG_SYS_PCIE3_MEM_PHYS2,
CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
#endif
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
}
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
+
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci3", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
#endif
- }
}
#endif
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
void
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
+ struct pci_region *r = hose->regions;
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
/* relocate config table pointers */
hose->config_table = \
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
- const char *path;
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
+void ft_pci_setup(void *blob, bd_t *bd)
+{
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
- }
}
#endif
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno = 0;
/*
pib_init();
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
uint pci_32 = 1; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
- const char *path;
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+void ft_board_setup(void *blob, bd_t *bd)
+{
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
- }
}
#endif
static struct pci_controller pcie3_hose;
#endif
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
#ifdef CONFIG_PCIE3
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
(host_agent == 5) || (host_agent == 6);
int pcie_configured = io_sel >= 1;
+ struct pci_region *r = hose->regions;
u32 temp32;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
(host_agent == 6) || (host_agent == 0);
int pcie_configured = io_sel & 4;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
int pcie_configured = io_sel & 6;
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
ulong base, size;
ft_cpu_setup(blob, bd);
fdt_fixup_memory(blob, (u64)base, (u64)size);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
#endif
- }
}
#endif
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
(host_agent == 5);
+ struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
pci->pme_msg_det = 0xffffffff;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
+ struct pci_region *r = hose->regions;
int pcie_configured = (io_sel == 0) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
pci->pme_msg_det = 0xffffffff;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+ struct pci_region *r = hose->regions;
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
printf(" PCI connected to PCI slots as %s" \
(uint)pci);
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr,
}
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
-
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno
- - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno
- - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
#endif
- }
}
#endif
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
+
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
debug("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
-
+ struct pci_region *r = hose->regions;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
- }
}
#endif
int first_free_busno=0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void
pci_init_board(void)
{
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_config_table *table;
+ struct pci_region *r = hose->regions;
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
/* relocate config table pointers */
hose->config_table = \
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
printf ("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
+ pci_set_region(r++,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
}
#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- int node, tmp[2];
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
- const char *path;
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
- const char *path;
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
- }
-}
-#endif
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
}
#endif
int first_free_busno = 0;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
debug("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
+ struct pci_region *r = hose->regions;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
+ pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
-void
-ft_board_setup (void *blob, bd_t *bd)
+void ft_board_setup (void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
- }
}
#endif
jmp *%ebp /* return to caller */
-.globl show_boot_progress
-show_boot_progress:
+.globl show_boot_progress_asm
+show_boot_progress_asm:
out %al, $0x80
xchg %al, %ah
movw $0x680, %dx
jmp *%ebp /* return to caller */
-.globl show_boot_progress
-show_boot_progress:
+.globl show_boot_progress_asm
+show_boot_progress_asm:
movl $0xfffefc32,%edx
xorw $0xffff, %ax
movw %ax,(%edx)
*/
static int first_free_busno;
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI || CONFIG_PCI1 */
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
/* PORDEVSR[15] */
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
/* inbound */
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region (hose->regions + 1,
+ pci_set_region (r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region (hose->regions + 2,
+ pci_set_region (r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect (hose, (int)&pci->cfg_addr,
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) ||
(host_agent == 3);
+ struct pci_region *r = hose->regions;
int pcie_configured = io_sel >= 1;
puts ("\n");
/* inbound */
- pci_set_region (hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region (hose->regions + 1,
+ pci_set_region (r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region (hose->regions + 2,
+ pci_set_region (r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
}
#ifdef CONFIG_OF_BOARD_SETUP
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
void ft_board_setup (void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup (blob, bd);
- node = fdt_path_offset (blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
- path = fdt_getprop (blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif /* CONFIG_PCI || CONFIG_PCI1 */
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
+#endif
#ifdef CONFIG_PCIE1
- path = fdt_getprop (blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif /* CONFIG_PCIE1 */
- }
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+#endif
}
#endif /* CONFIG_OF_BOARD_SETUP */
--- /dev/null
+config.tmp
--- /dev/null
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+endif
+
+INCS :=
+CFLAGS += $(INCS)
+HOST_CFLAGS += $(INCS)
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2008
+# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+# Work supported by Qtechnology http://www.qtec.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/ppc4xx/start.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+
+ ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <config.h>
+#include <common.h>
+#include <asm/processor.h>
+
+ulong __get_PCI_freq(void)
+{
+ return 0;
+}
+
+ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq")));
+
+int __board_pre_init(void)
+{
+ return 0;
+}
+int board_pre_init(void) __attribute__((weak, alias("__board_pre_init")));
+
+int __checkboard(void)
+{
+ puts("Xilinx PPC405 Generic Board\n");
+ return 0;
+}
+int checkboard(void) __attribute__((weak, alias("__checkboard")));
+
+phys_size_t __initdram(int board_type)
+{
+ return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
+ CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
+}
+phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
+
+void __get_sys_info(sys_info_t *sysInfo)
+{
+ sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ;
+ sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ;
+ sysInfo->freqPCI = 0;
+
+ return;
+}
+void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ * based on xparameters-ml507.h by Xilinx
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef XPARAMETER_H
+#define XPARAMETER_H
+
+#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_SPI_0_BASEADDR 0x83400000
+#define XPAR_UARTLITE_0_BASEADDR 0x84000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
+#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
+
+#endif
*/
DECLARE_GLOBAL_DATA_PTR;
+/**
+ * fdt_getprop_u32_default - Find a node and return it's property or a default
+ *
+ * @fdt: ptr to device tree
+ * @path: path of node
+ * @prop: property name
+ * @dflt: default value if the property isn't found
+ *
+ * Convenience function to find a node and return it's property or a
+ * default value if it doesn't exist.
+ */
+u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
+ const u32 dflt)
+{
+ const u32 *val;
+ int off;
+
+ off = fdt_path_offset(fdt, path);
+ if (off < 0)
+ return dflt;
+
+ val = fdt_getprop(fdt, off, prop, NULL);
+ if (val)
+ return *val;
+ else
+ return dflt;
+}
/**
* fdt_find_and_setprop: Find a node and set it's property
return actualsize;
}
+
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_PCI_NR_INBOUND_WIN 3
+
+#define FDT_PCI_PREFETCH (0x40000000)
+#define FDT_PCI_MEM32 (0x02000000)
+#define FDT_PCI_IO (0x01000000)
+#define FDT_PCI_MEM64 (0x03000000)
+
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
+
+ int addrcell, sizecell, len, r;
+ u32 *dma_range;
+ /* sized based on pci addr cells, size-cells, & address-cells */
+ u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN];
+
+ addrcell = fdt_getprop_u32_default(blob, "/", "#address-cells", 1);
+ sizecell = fdt_getprop_u32_default(blob, "/", "#size-cells", 1);
+
+ dma_range = &dma_ranges[0];
+ for (r = 0; r < hose->region_count; r++) {
+ u64 bus_start, phys_start, size;
+
+ /* skip if !PCI_REGION_MEMORY */
+ if (!(hose->regions[r].flags & PCI_REGION_MEMORY))
+ continue;
+
+ bus_start = (u64)hose->regions[r].bus_start;
+ phys_start = (u64)hose->regions[r].phys_start;
+ size = (u64)hose->regions[r].size;
+
+ dma_range[0] = 0;
+ if (size > 0x100000000ull)
+ dma_range[0] |= FDT_PCI_MEM64;
+ else
+ dma_range[0] |= FDT_PCI_MEM32;
+ if (hose->regions[r].flags & PCI_REGION_PREFETCH)
+ dma_range[0] |= FDT_PCI_PREFETCH;
+#ifdef CONFIG_SYS_PCI_64BIT
+ dma_range[1] = bus_start >> 32;
+#else
+ dma_range[1] = 0;
+#endif
+ dma_range[2] = bus_start & 0xffffffff;
+
+ if (addrcell == 2) {
+ dma_range[3] = phys_start >> 32;
+ dma_range[4] = phys_start & 0xffffffff;
+ } else {
+ dma_range[3] = phys_start & 0xffffffff;
+ }
+
+ if (sizecell == 2) {
+ dma_range[3 + addrcell + 0] = size >> 32;
+ dma_range[3 + addrcell + 1] = size & 0xffffffff;
+ } else {
+ dma_range[3 + addrcell + 0] = size & 0xffffffff;
+ }
+
+ dma_range += (3 + addrcell + sizecell);
+ }
+
+ len = dma_range - &dma_ranges[0];
+ if (len)
+ fdt_setprop(blob, phb_off, "dma-ranges", &dma_ranges[0], len*4);
+
+ return 0;
+}
+#endif
/* so we try to indicate progress */
movw $0x01, %ax
movl $.progress0, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress0:
/* size memory */
/* indicate (lack of) progress */
movw $0x81, %ax
movl $.progress0a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress0a:
jmp die
mem_ok:
/* indicate progress */
movw $0x02, %ax
movl $.progress1, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress1:
/* create a stack after the bss */
/* indicate (lack of) progress */
movw $0x82, %ax
movl $.progress1a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress1a:
jmp die
/* indicate progress */
movw $0x03, %ax
movl $.progress2, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress2:
/* copy data section to ram, size must be 4-byte aligned */
/* indicate (lack of) progress */
movw $0x83, %ax
movl $.progress2a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress2a:
jmp die
/* indicate progress */
movw $0x04, %ax
movl $.progress3, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
/* indicate (lack of) progress */
movw $0x84, %ax
movl $.progress3a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress3a:
jmp die
/* indicate progress */
movw $0x05, %ax
movl $.progress4, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress4:
call start_i386boot /* Enter, U-boot! */
/* indicate (lack of) progress */
movw $0x85, %ax
movl $.progress4a, %ebp
- jmp show_boot_progress
+ jmp show_boot_progress_asm
.progress4a:
die: hlt
puts("Unknown");
break;
}
+
+ if (PVR_MEM(pvr) == 0x03)
+ puts("MC");
+
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
get_sys_info(&sysinfo);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
/*
- * 32-bit workaround for DDR2
- * 32_BE
+ * For 8572 DDR1 erratum - DDR controller may enter illegal state
+ * when operatiing in 32-bit bus mode with 4-beat bursts,
+ * This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
+#ifdef CONFIG_MPC8572
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
- && in_be32(&ddr->sdram_cfg_2) & 0x80000) {
+ && in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
u32 temp = in_be32(&ddr->debug_1);
out_be32(&ddr->debug_1, temp | 1);
}
+#endif
/*
* 200 painful micro-seconds must elapse between
__secondary_start_page:
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
+#ifndef CONFIG_E500MC
ori r3,r3,HID0_TBEN@l /* enable Timebase */
+#endif
#ifdef CONFIG_PHYS_64BIT
ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
#endif
mtspr SPRN_HID0,r3
+#ifndef CONFIG_E500MC
li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr SPRN_HID1,r3
+#endif
/* Enable branch prediction */
li r3,0x201
/* r10 has the base address for the entry */
mfspr r0,SPRN_PIR
+#ifdef CONFIG_E500MC
+ rlwinm r4,r0,27,27,31
+#else
mr r4,r0
+#endif
slwi r8,r4,5
add r10,r3,r8
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
mtspr HID0,r0
+#ifndef CONFIG_E500MC
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
+#endif
/* Enable Branch Prediction */
#if defined(CONFIG_BTB)
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
- ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
+ lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
+ ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
mfspr r4,L1CFG0
andi. r4,r4,0x1ff
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
mtdccr r4
-#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
+#if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
+ && !defined (CONFIG_XILINX_405)
/*----------------------------------------------------------------------- */
/* Tune the speed and size for flash CS0 */
/*----------------------------------------------------------------------- */
#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
*
pci_dev_t dev, int sub_bus);
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
-
void pciauto_config_init(struct pci_controller *hose);
-void
-fsl_pci_init(struct pci_controller *hose)
+
+#ifndef CONFIG_SYS_PCI_MEMORY_BUS
+#define CONFIG_SYS_PCI_MEMORY_BUS 0
+#endif
+
+#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
+#define CONFIG_SYS_PCI_MEMORY_PHYS 0
+#endif
+
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
+#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
+#endif
+
+int fsl_pci_setup_inbound_windows(struct pci_region *r)
+{
+ struct pci_region *rgn_base = r;
+ u64 sz = min((u64)gd->ram_size, 1ull << 32);
+
+ phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
+ pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+ pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
+
+ debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)bus_start, (u64)phys_start, (u64)pci_sz);
+ pci_set_region(r++, bus_start, phys_start, pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_PREFETCH);
+
+ sz -= pci_sz;
+ bus_start += pci_sz;
+ phys_start += pci_sz;
+
+ pci_sz = 1ull << __ilog2_u64(sz);
+ if (sz) {
+ debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)bus_start, (u64)phys_start, (u64)pci_sz);
+ pci_set_region(r++, bus_start, phys_start, pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_PREFETCH);
+ sz -= pci_sz;
+ bus_start += pci_sz;
+ phys_start += pci_sz;
+ }
+
+#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
+ /*
+ * On 64-bit capable systems, set up a mapping for all of DRAM
+ * in high pci address space.
+ */
+ pci_sz = 1ull << __ilog2_u64(gd->ram_size);
+ /* round up to the next largest power of two */
+ if (gd->ram_size > pci_sz)
+ pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
+ debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
+ (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
+ (u64)pci_sz);
+ pci_set_region(r++,
+ CONFIG_SYS_PCI64_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_PREFETCH);
+#else
+ pci_sz = 1ull << __ilog2_u64(sz);
+ if (sz) {
+ debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
+ (u64)bus_start, (u64)phys_start, (u64)pci_sz);
+ pci_set_region(r++, bus_start, phys_start, pci_sz,
+ PCI_REGION_MEM | PCI_REGION_MEMORY |
+ PCI_REGION_PREFETCH);
+ sz -= pci_sz;
+ bus_start += pci_sz;
+ phys_start += pci_sz;
+ }
+#endif
+
+ if (sz && (((u64)gd->ram_size) < (1ull << 32)))
+ printf("Was not able to map all of memory via "
+ "inbound windows -- %lld remaining\n", sz);
+
+ return r - rgn_base;
+}
+
+void fsl_pci_init(struct pci_controller *hose)
{
u16 temp16;
u32 temp32;
#endif
for (r=0; r<hose->region_count; r++) {
+ u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
- pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
- pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
+ u32 flag = PIWAR_EN | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+ pi->pitar = (hose->regions[r].phys_start >> 12);
+ pi->piwbar = (hose->regions[r].bus_start >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+ pi->piwbear = (hose->regions[r].bus_start >> 44);
+#else
pi->piwbear = 0;
- pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
- PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
- (__ilog2(hose->regions[r].size) - 1);
+#endif
+ if (hose->regions[r].flags & PCI_REGION_PREFETCH)
+ flag |= PIWAR_PF;
+ pi->piwar = flag | sz;
pi++;
inbound = hose->regions[r].size > 0;
} else { /* Outbound */
- po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
- po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
+ po->powbar = (hose->regions[r].phys_start >> 12);
+ po->potar = (hose->regions[r].bus_start >> 12);
+#ifdef CONFIG_SYS_PCI_64BIT
+ po->potear = (hose->regions[r].bus_start >> 44);
+#else
po->potear = 0;
+#endif
if (hose->regions[r].flags & PCI_REGION_IO)
- po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE |
- (__ilog2(hose->regions[r].size) - 1);
+ po->powar = POWAR_EN | sz |
+ POWAR_IO_READ | POWAR_IO_WRITE;
else
- po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE |
- (__ilog2(hose->regions[r].size) - 1);
+ po->powar = POWAR_EN | sz |
+ POWAR_MEM_READ | POWAR_MEM_WRITE;
po++;
}
}
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose)
+{
+ int off = fdt_path_offset(blob, pci_alias);
+
+ if (off >= 0) {
+ u32 bus_range[2];
+
+ bus_range[0] = 0;
+ bus_range[1] = hose->last_busno - hose->first_busno;
+ fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
+ fdt_pci_dma_ranges(blob, off, hose);
+ }
+}
+#endif
*
*/
-unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
+pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags)
{
struct pci_region *res;
- unsigned long bus_addr;
+ pci_addr_t bus_addr;
int i;
if (!hose) {
}
phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
- unsigned long bus_addr,
+ pci_addr_t bus_addr,
unsigned long flags)
{
struct pci_region *res;
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
- unsigned long mem,
+ pci_addr_t mem,
unsigned long command)
{
- unsigned int bar_response, bar_size, bar_value, old_command;
+ unsigned int bar_response, old_command;
+ pci_addr_t bar_value;
+ pci_size_t bar_size;
unsigned char pin;
int bar, found_mem64;
- debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
- io, mem, command);
+ debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
+ io, (u64)mem, command);
pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
io = io + bar_size;
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64)
- found_mem64 = 1;
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+ pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ bar64 = ((u64)bar_response_upper << 32) | bar_response;
+
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
/* round up region base address to multiple of size */
mem = ((mem - 1) | (bar_size - 1)) + 1;
}
/* Write it out and update our limit */
- pci_hose_write_config_dword (hose, dev, bar, bar_value);
+ pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+#else
pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
+#endif
}
}
res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
}
-void pciauto_region_align(struct pci_region *res, unsigned long size)
+void pciauto_region_align(struct pci_region *res, pci_size_t size)
{
res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}
-int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
+int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
{
- unsigned long addr;
+ pci_addr_t addr;
if (!res) {
DEBUGF("No resource");
res->bus_lower = addr + size;
- DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);
+ DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
*bar = addr;
return 0;
error:
- *bar = 0xffffffff;
+ *bar = (pci_addr_t)-1;
return -1;
}
struct pci_region *prefetch,
struct pci_region *io)
{
- unsigned int bar_value, bar_response, bar_size;
+ unsigned int bar_response;
+ pci_addr_t bar_value;
+ pci_size_t bar_size;
unsigned int cmdstat = 0;
struct pci_region *bar_res;
int bar, bar_nr = 0;
& 0xffff) + 1;
bar_res = io;
- DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
+ DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
- PCI_BASE_ADDRESS_MEM_TYPE_64)
- found_mem64 = 1;
+ PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ u32 bar_response_upper;
+ u64 bar64;
+ pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
+ pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
+
+ bar64 = ((u64)bar_response_upper << 32) | bar_response;
- bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
+ found_mem64 = 1;
+ } else {
+ bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
+ }
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
- DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
+ DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
- pci_hose_write_config_dword(hose, dev, bar, bar_value);
+ pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
- /*
- * If we are a 64-bit decoder then increment to the
- * upper 32 bits of the bar and force it to locate
- * in the lower 4GB of memory.
- */
if (found_mem64) {
bar += 4;
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
+#else
+ /*
+ * If we are a 64-bit decoder then increment to the
+ * upper 32 bits of the bar and force it to locate
+ * in the lower 4GB of memory.
+ */
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
+#endif
}
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
if (hose->pci_mem) {
pciauto_region_init(hose->pci_mem);
- DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
- "\t\tPhysical Memory [%x-%x]\n",
- hose->pci_mem->bus_start,
- hose->pci_mem->bus_start + hose->pci_mem->size - 1,
- hose->pci_mem->phys_start,
- hose->pci_mem->phys_start + hose->pci_mem->size - 1);
+ DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory [%llx-%llxx]\n",
+ (u64)hose->pci_mem->bus_start,
+ (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
+ (u64)hose->pci_mem->phys_start,
+ (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
}
if (hose->pci_prefetch) {
pciauto_region_init(hose->pci_prefetch);
- DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
- "\t\tPhysical Memory [%x-%x]\n",
- hose->pci_prefetch->bus_start,
- hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
- hose->pci_prefetch->phys_start,
- hose->pci_prefetch->phys_start +
- hose->pci_prefetch->size - 1);
+ DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory [%llx-%llx]\n",
+ (u64)hose->pci_prefetch->bus_start,
+ (u64)(hose->pci_prefetch->bus_start +
+ hose->pci_prefetch->size - 1),
+ (u64)hose->pci_prefetch->phys_start,
+ (u64)(hose->pci_prefetch->phys_start +
+ hose->pci_prefetch->size - 1));
}
if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
- DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
- "\t\tPhysical Memory: [%x-%x]\n",
- hose->pci_io->bus_start,
- hose->pci_io->bus_start + hose->pci_io->size - 1,
- hose->pci_io->phys_start,
- hose->pci_io->phys_start + hose->pci_io->size - 1);
+ DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
+ "\t\tPhysical Memory: [%llx-%llx]\n",
+ (u64)hose->pci_io->bus_start,
+ (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
+ (u64)hose->pci_io->phys_start,
+ (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
}
}
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
+#elif defined(CONFIG_E500MC)
+#define L1_CACHE_SHIFT 6
#else
#define L1_CACHE_SHIFT 5
#endif
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
-#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00010000
-/* FIXME: Not used in fixed_sdram function */
-#define CONFIG_SYS_DDR_MODE 0x00000022
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */
-#define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */
-#define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */
-#define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */
-
/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
#endif
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_MPC8560 1
#define CONFIG_PCI
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
#define CONFIG_SYS_DDR_SBE 0x00010000
-/*
- * FIXME: Not used in fixed_sdram function
- */
-#define CONFIG_SYS_DDR_MODE 0x00000022
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */
-#define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */
-#define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */
-#define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */
-
/*
* Make sure required options are set
*/
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
#define _IO_BASE 0x00000000
#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#ifdef CONFIG_PCIE1
/*
* General PCI express
--- /dev/null
+/*
+ * (C) Copyright 2008
+ *
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+/*
+ Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
+ see http://www.em.avnet.com
+*/
+
+#ifndef __CONFIG_FX12_H
+#define __CONFIG_FX12_H
+
+#include "../board/avnet/fx12mm/xparameters.h"
+
+/* cmd config */
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_NET
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB 64
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_SYS_ENV_OFFSET 0xA0000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE 1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_2MX16_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE (4*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 71
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define MTDIDS_DEFAULT "nor0=fx12mm-flash"
+#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)"
+
+
+#include "configs/xilinx-ppc405.h"
+
+#endif /* __CONFIG_H */
+
*
* DDR Autocalibration Method_B is the default.
*/
+#if 0
+/*
+ * Needs FIX!!!
+ * Disable autocalibration for now, because of the unresolved problem
+ * with kilauea board using 200MHz PLB/DDR2 frequency
+ */
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
+#endif
#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#endif /* CONFIG_PCI */
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
-
#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
--- /dev/null
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_GEN_H
+#define __CONFIG_GEN_H
+
+#include "../board/xilinx/ppc405-generic/xparameters.h"
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB 256
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_SYS_ENV_OFFSET 0x3F0000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE 1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 71
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define MTDIDS_DEFAULT "nor0=ppc405-flash"
+#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)"
+
+#include <configs/xilinx-ppc405.h>
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* cpu parameter */
+#define CONFIG_4xx 1
+#define CONFIG_405 1
+#define CONFIG_XILINX_405 1
+
+/* memory map */
+#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (192 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/* u-boot commands configuration */
+#include <config_cmd_default.h>
+
+/*Misc*/
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* default load address */
+#define CONFIG_SYS_EXTBDINFO 1 /* Extended board_into (bd_t) */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_LOOPW /* enable loopw command */
+#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE /* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+ /* Initial Memory map for Linux */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_CACHELINE_SHIFT 2
+
+/* stack */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_FLASH_CF 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/* serial communication */
+#ifdef XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_XILINX_UARTLITE
+#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
+#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
+#else
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 4
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 }
+#endif
+#endif
+
+/* cmd config */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMLS
+
+#endif
#include <fdt.h>
+u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
+ const u32 dflt);
int fdt_chosen(void *fdt, int force);
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
#endif
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
-#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
-#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
+#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
+#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
-#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
+#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
#include <pci_ids.h>
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
struct pci_region {
- unsigned long bus_start; /* Start on the bus */
- phys_addr_t phys_start; /* Start in physical address space */
- unsigned long size; /* Size */
- unsigned long flags; /* Resource flags */
+ pci_addr_t bus_start; /* Start on the bus */
+ phys_addr_t phys_start; /* Start in physical address space */
+ pci_size_t size; /* Size */
+ unsigned long flags; /* Resource flags */
- unsigned long bus_lower;
+ pci_addr_t bus_lower;
};
#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
extern __inline__ void pci_set_region(struct pci_region *reg,
- unsigned long bus_start,
+ pci_addr_t bus_start,
phys_addr_t phys_start,
- unsigned long size,
+ pci_size_t size,
unsigned long flags) {
reg->bus_start = bus_start;
reg->phys_start = phys_start;
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
- unsigned long addr, unsigned long flags);
-extern unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
- phys_addr_t addr, unsigned long flags);
+ pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+ phys_addr_t addr, unsigned long flags);
#define pci_phys_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
extern void pciauto_region_init(struct pci_region* res);
-extern void pciauto_region_align(struct pci_region *res, unsigned long size);
-extern int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
+extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
+extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
extern int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
- unsigned long mem,
+ pci_addr_t mem,
unsigned long command);
#ifdef CONFIG_MPC824X
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