dts: mtmips: move uart property clock-frequency into mt7628an.dtsi
authorWeijie Gao <weijie.gao@mediatek.com>
Wed, 25 Sep 2019 09:45:19 +0000 (17:45 +0800)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Fri, 25 Oct 2019 15:20:44 +0000 (17:20 +0200)
The UART of MT7628 has fixed 40MHz input clock so there is no need to put
clock-frequency in every dts files. Just put it into the common dtsi file.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
arch/mips/dts/gardena-smart-gateway-mt7688.dts
arch/mips/dts/linkit-smart-7688.dts
arch/mips/dts/mt7628a.dtsi

index eedde89dfd8a719cf3647ef0e1c7704c66ec0822..95675a39475d4e8fc557ea40cac9c8f8bb4d80e5 100644 (file)
@@ -87,7 +87,6 @@
 
 &uart0 {
        status = "okay";
-       clock-frequency = <40000000>;
 };
 
 &spi0 {
index bb104021747a55a7c13aaa35f6e8a2eb3b7658db..935315743c132803c1a3be8ebe0dd4fef5173d62 100644 (file)
@@ -28,7 +28,6 @@
 
 &uart2 {
        status = "okay";
-       clock-frequency = <40000000>;
 };
 
 &spi0 {
index 1e7d0a6ec5a02eb0fb23bee1a9dbc20be6af8fca..6bc0722b074b08d0fbe9f06a83cd470f0dd0bf48 100644 (file)
                        compatible = "ns16550a";
                        reg = <0xc00 0x100>;
 
+                       clock-frequency = <40000000>;
+
                        resets = <&resetc 12>;
                        reset-names = "uart0";
 
                        compatible = "ns16550a";
                        reg = <0xd00 0x100>;
 
+                       clock-frequency = <40000000>;
+
                        resets = <&resetc 19>;
                        reset-names = "uart1";
 
                        compatible = "ns16550a";
                        reg = <0xe00 0x100>;
 
+                       clock-frequency = <40000000>;
+
                        resets = <&resetc 20>;
                        reset-names = "uart2";