powerpc/mpc85xx: Add Differential SYSCLK config support T1040
authorNikhil Badola <nikhil.badola@freescale.com>
Tue, 15 Apr 2014 09:14:52 +0000 (14:44 +0530)
committerYork Sun <yorksun@freescale.com>
Wed, 23 Apr 2014 00:58:52 +0000 (17:58 -0700)
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/powerpc/cpu/mpc85xx/cpu_init.c
include/fsl_usb.h

index a2b79cc7cc0fd153ea7c5e319b357d7d1c1721a8..36ef23232ed044db5cf3316067b445d213c0f87a 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+       sys_info_t sysinfo;
+
+       get_sys_info(&sysinfo);
+       if (sysinfo.diff_sysclk == 1) {
+               clrbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+               setbits_be32(&usb_phy->pllprg[1],
+                            CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+                            CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+               }
+}
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 {
@@ -815,6 +838,9 @@ skip_l2:
                             CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
                             CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
                             CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+               usb_single_source_clk_configure(usb_phy);
+#endif
                setbits_be32(&usb_phy->port1.ctrl,
                             CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
                setbits_be32(&usb_phy->port1.drvvbuscfg,
index 8b63cdd88c03416d043521a758d8f983a4eb63c2..1a6c9c1636638f3977db5f3dfbc77bc01392f03a 100644 (file)
@@ -48,6 +48,11 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
+#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
+#endif
 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)