arch: arm: fsl: Add XHCI support for LS1021A
authorRamneek Mehresh <ramneek.mehresh@freescale.com>
Fri, 29 May 2015 09:17:20 +0000 (14:47 +0530)
committerMarek Vasut <marex@denx.de>
Wed, 22 Jul 2015 06:55:45 +0000 (08:55 +0200)
Add base register address information for USB
XHCI controller on LS1021A

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

index 4dc528bc810974be4f19f2612ebb1a4ae82ff3dd..c55cdef4c76a5751a2976148b56451f2ab7fb0a7 100644 (file)
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR                    (CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR      (CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_LS102XA_USB1_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
index 6a330cc2affe15d05918b6434191bc498c54b1f7..e759b52d606be84f50823f5a7e67887c531a47f2 100644 (file)
@@ -396,4 +396,14 @@ struct ccsr_cci400 {
        } pcounter[4];                  /* Performance Counter */
        u8 res_e004[0x10000 - 0xe004];
 };
+
+/* USB-XHCI */
+#define FSL_XHCI_BASE  0x3100000
+#define FSL_OCP1_SCP_BASE      0x4a084c00
+#define FSL_OTG_WRAPPER_BASE   0x4A020000
+
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR  CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR  0
+#define FSL_USB_XHCI_ADDR      {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
+                                       CONFIG_SYS_FSL_XHCI_USB2_ADDR}
 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */