MX31: Add NAND SPL boot support to i.MX31 PDK board.
authorMagnus Lilja <lilja.magnus@gmail.com>
Sat, 4 Jul 2009 08:31:24 +0000 (10:31 +0200)
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Mon, 6 Jul 2009 19:53:18 +0000 (21:53 +0200)
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
MAKEALL
Makefile
board/freescale/mx31pdk/config.mk
board/freescale/mx31pdk/lowlevel_init.S [new file with mode: 0644]
include/asm-arm/arch-mx31/mx31-regs.h
include/configs/mx31pdk.h
nand_spl/board/freescale/mx31pdk/Makefile [new file with mode: 0644]
nand_spl/board/freescale/mx31pdk/config.mk [new file with mode: 0644]
nand_spl/board/freescale/mx31pdk/u-boot.lds [new file with mode: 0644]

diff --git a/MAKEALL b/MAKEALL
index e6f6c147de0d4a6b277138a25626755a54daddde..f2d3b6fad593d6ff425e6373adb158316783ffac 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -555,6 +555,7 @@ LIST_ARM11="                        \
        imx31_phycore_eet       \
        mx31ads                 \
        mx31pdk                 \
+       mx31pdk_nand            \
        qong                    \
        smdk6400                \
 "
index d486b55422c3d18c3bf78cf19dce6138822c39cd..763a202b361caece0855ecda411cb632c4f96a1f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3143,8 +3143,16 @@ imx31_phycore_config     : unconfig
 mx31ads_config         : unconfig
        @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
 
-mx31pdk_config         : unconfig
-       @$(MKCONFIG) $(@:_config=) arm arm1136 mx31pdk freescale mx31
+mx31pdk_config \
+mx31pdk_nand_config    : unconfig
+       @mkdir -p $(obj)include
+       @if [ -n "$(findstring _nand_,$@)" ]; then                                      \
+               echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h;            \
+       else                                                                            \
+               echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h;     \
+               echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h;    \
+       fi
+       @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
 
 omap2420h4_config      : unconfig
        @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
index d34dc02d96a681110a9ae6e7b753516ed6249dde..dcaa09ff8372797eddccca0867ea2265bb6a775c 100644 (file)
@@ -1 +1,5 @@
+ifdef CONFIG_NAND_SPL
+TEXT_BASE = 0x87ec0000
+else
 TEXT_BASE = 0x87f00000
+endif
diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S
new file mode 100644 (file)
index 0000000..cd0503e
--- /dev/null
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+       /* Also setup the Peripheral Port Remap register inside the core */
+       ldr     r0, =ARM_PPMRR      /* start from AIPS 2GB region */
+       mcr     p15, 0, r0, c15, c2, 4
+
+       write32 IPU_CONF, IPU_CONF_DI_EN
+       write32 CCM_CCMR, CCM_CCMR_SETUP
+
+       wait_timer      0x40000
+
+       write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
+       write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
+
+       /* Set up clock to 532MHz */
+       write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
+       write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
+
+       write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+       /* Set up MX31 DDR pins */
+       write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
+       write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
+       write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
+       write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
+       write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
+       write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
+       write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
+       write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
+       write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
+       write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
+       write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
+       write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
+       write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
+       write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
+       write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
+       write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
+       write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
+       write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
+       write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
+       write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
+       write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
+       write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
+       write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
+       write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
+       write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
+       write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
+       write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
+
+       /* Set up MX31 DDR Memory Controller */
+       write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
+       write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
+
+       /* Perform DDR init sequence */
+       write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
+       write32 CSD0_BASE | 0x0f00, 0x12344321
+       write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
+       write32 CSD0_BASE, 0x12344321
+       write32 CSD0_BASE, 0x12344321
+       write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
+       write8  CSD0_BASE | 0x00000033, 0xda
+       write8  CSD0_BASE | 0x01000000, 0xff
+       write32 WEIM_ESDCTL0, ESDCTL_RW
+       write32 CSD0_BASE, 0xDEADBEEF
+       write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
+
+       mov     pc, lr
index 76f4d53a32e4a572c6b21671e68a3f6588b6ffb4..51b02a2a2604e335e9c4af3ca7cad2eab4e2aac3 100644 (file)
 #define PLL_MFI(x)             (((x) & 0xf) << 10)
 #define PLL_MFN(x)             (((x) & 0x3ff) << 0)
 
+#define WEIM_ESDCTL0   0xB8001000
+#define WEIM_ESDCFG0   0xB8001004
+#define WEIM_ESDCTL1   0xB8001008
+#define WEIM_ESDCFG1   0xB800100C
+#define WEIM_ESDMISC   0xB8001010
+
+#define ESDCTL_SDE                     (1 << 31)
+#define ESDCTL_CMD_RW                  (0 << 28)
+#define ESDCTL_CMD_PRECHARGE           (1 << 28)
+#define ESDCTL_CMD_AUTOREFRESH         (2 << 28)
+#define ESDCTL_CMD_LOADMODEREG         (3 << 28)
+#define ESDCTL_CMD_MANUALREFRESH       (4 << 28)
+#define ESDCTL_ROW_13                  (2 << 24)
+#define ESDCTL_ROW(x)                  ((x) << 24)
+#define ESDCTL_COL_9                   (1 << 20)
+#define ESDCTL_COL(x)                  ((x) << 20)
+#define ESDCTL_DSIZ(x)                 ((x) << 16)
+#define ESDCTL_SREFR(x)                        ((x) << 13)
+#define ESDCTL_PWDT(x)                 ((x) << 10)
+#define ESDCTL_FP(x)                   ((x) << 8)
+#define ESDCTL_BL(x)                   ((x) << 7)
+#define ESDCTL_PRCT(x)                 ((x) << 0)
+
 #define WEIM_BASE      0xb8002000
 #define CSCR_U(x)      (WEIM_BASE + (x) * 0x10)
 #define CSCR_L(x)      (WEIM_BASE + 4 + (x) * 0x10)
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
+/* PAD control registers for SDR/DDR */
+#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
+#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0      (IOMUXC_BASE + 0x270)
+#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS          (IOMUXC_BASE + 0x274)
+#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA          (IOMUXC_BASE + 0x278)
+#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4          (IOMUXC_BASE + 0x27C)
+#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1           (IOMUXC_BASE + 0x280)
+#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1         (IOMUXC_BASE + 0x284)
+#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2       (IOMUXC_BASE + 0x288)
+#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31       (IOMUXC_BASE + 0x28C)
+#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28       (IOMUXC_BASE + 0x290)
+#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25       (IOMUXC_BASE + 0x294)
+#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22       (IOMUXC_BASE + 0x298)
+#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19       (IOMUXC_BASE + 0x29C)
+#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16       (IOMUXC_BASE + 0x2A0)
+#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13       (IOMUXC_BASE + 0x2A4)
+#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10         (IOMUXC_BASE + 0x2A8)
+#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7          (IOMUXC_BASE + 0x2AC)
+#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4          (IOMUXC_BASE + 0x2B0)
+#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1                (IOMUXC_BASE + 0x2B4)
+#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1                (IOMUXC_BASE + 0x2B8)
+#define IOMUXC_SW_PAD_CTL_A21_A22_A23          (IOMUXC_BASE + 0x2BC)
+#define IOMUXC_SW_PAD_CTL_A18_A19_A20          (IOMUXC_BASE + 0x2C0)
+#define IOMUXC_SW_PAD_CTL_A15_A16_A17          (IOMUXC_BASE + 0x2C4)
+#define IOMUXC_SW_PAD_CTL_A12_A13_A14          (IOMUXC_BASE + 0x2C8)
+#define IOMUXC_SW_PAD_CTL_A10_MA10_A11         (IOMUXC_BASE + 0x2CC)
+#define IOMUXC_SW_PAD_CTL_A7_A8_A9             (IOMUXC_BASE + 0x2D0)
+#define IOMUXC_SW_PAD_CTL_A4_A5_A6             (IOMUXC_BASE + 0x2D4)
+#define IOMUXC_SW_PAD_CTL_A1_A2_A3             (IOMUXC_BASE + 0x2D8)
+#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0         (IOMUXC_BASE + 0x2DC)
+
 /*
  * Memory regions and CS
  */
index 7167e9d0db213c3de3dd8989b0b6f4d0043704b8..a4862c6fc5a204b325a0da6c7ef2e32dd634d63c 100644 (file)
 #define CONFIG_SETUP_MEMORY_TAGS       1
 #define CONFIG_INITRD_TAG              1
 
-/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other
- * program to initialize the SDRAM.
- */
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#endif
 
 /*
  * Size of malloc() pool
 
 #define CONFIG_ENV_SIZE                (128 * 1024)
 
+/* NAND configuration for the NAND_SPL */
+
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x800
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    0x30000
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST     0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE      0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT     64
+#define CONFIG_SYS_NAND_SIZE           (256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
+
+
+/* Configuration of lowlevel_init.S (clocks and SDRAM) */
+#define CCM_CCMR_SETUP         0x074B0BF5
+#define CCM_PDR0_SETUP_532MHZ  (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
+                                PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
+                                PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
+                                PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+                                PLL_MFN(12))
+
+#define ESDMISC_MDDR_SETUP     0x00000004
+#define ESDMISC_MDDR_RESET_DL  0x0000000c
+#define ESDCFG0_MDDR_SETUP     0x006ac73a
+
+#define ESDCTL_ROW_COL         (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS                (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+                                ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE       (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH     (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG     (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW              ESDCTL_SETTINGS
+
 #endif /* __CONFIG_H */
diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile
new file mode 100644 (file)
index 0000000..a9572ba
--- /dev/null
@@ -0,0 +1,54 @@
+CONFIG_NAND_SPL        = y
+
+include $(TOPDIR)/config.mk
+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS        = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL
+
+SOBJS  = start.o lowlevel_init.o
+COBJS  = nand_boot_fsl_nfc.o
+
+SRCS   := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
+SRCS   += $(SRCTREE)/cpu/arm1136/start.S
+SRCS   += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS := $(SOBJS) $(COBJS)
+LNDIR  := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj        := $(OBJTREE)/nand_spl/
+
+ALL    = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:   $(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:      $(nandobj)u-boot-spl
+       $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:  $(OBJS)
+       cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
+               -Map $(nandobj)u-boot-spl.map \
+               -o $@
+
+#########################################################################
+
+$(obj)%.o:     $(SRCTREE)/cpu/arm1136/%.S
+       $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:     $(SRCTREE)/board/freescale/mx31pdk/%.S
+       $(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:     $(SRCTREE)/nand_spl/%.c
+       $(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/mx31pdk/config.mk b/nand_spl/board/freescale/mx31pdk/config.mk
new file mode 100644 (file)
index 0000000..68afbf1
--- /dev/null
@@ -0,0 +1 @@
+PAD_TO := 2048
diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds
new file mode 100644 (file)
index 0000000..edd8430
--- /dev/null
@@ -0,0 +1,36 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text :
+       {
+               start.o                 (.text)
+               lowlevel_init.o         (.text)
+               nand_boot_fsl_nfc.o     (.text)
+               *(.text)
+               . = 2K;
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(.rodata) }
+
+       . = ALIGN(4);
+       .data : { *(.data) }
+
+       . = ALIGN(4);
+       .got : { *(.got) }
+
+       . = .;
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       __bss_start = .;
+       .bss : { *(.bss) }
+       _end = .;
+}