config TARGET_P5020DS
bool "Support P5020DS"
select PHYS_64BIT
+ select ARCH_P5020
config TARGET_P5040DS
bool "Support P5040DS"
config ARCH_P4080
bool
+config ARCH_P5020
+ bool
+
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
obj-$(CONFIG_ARCH_P2041) += p2041_ids.o
obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
-obj-$(CONFIG_PPC_P5020) += p5020_ids.o
+obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
obj-$(CONFIG_ARCH_P2041) += p2041_serdes.o
obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
-obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
+obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
-#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#if defined(CONFIG_ARCH_P3041) || \
defined(CONFIG_ARCH_P4080) || \
- defined(CONFIG_PPC_P5020) || \
+ defined(CONFIG_ARCH_P5020) || \
defined(CONFIG_PPC_P5040) || \
defined(CONFIG_ARCH_P2041)
#define CONFIG_FSL_TRUST_ARCH_v1
#define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
#endif
#if defined(CONFIG_ARCH_P2041) || \
- defined(CONFIG_ARCH_P3041) || defined(CONFIG_PPC_P5020)
+ defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,ARCH_P5020"
CONFIG_BOOTDELAY=10
CONFIG_CONSOLE_MUX=y
CONFIG_HUSH_PARSER=y
obj-$(CONFIG_ARCH_P2041) += p5020.o
obj-$(CONFIG_ARCH_P3041) += p5020.o
obj-$(CONFIG_ARCH_P4080) += p4080.o
-obj-$(CONFIG_PPC_P5020) += p5020.o
+obj-$(CONFIG_ARCH_P5020) += p5020.o
obj-$(CONFIG_PPC_P5040) += p5040.o
obj-$(CONFIG_PPC_T1040) += t1040.o
obj-$(CONFIG_PPC_T1042) += t1040.o
* Also supports P5010 DS
*/
#define CONFIG_P5020DS
-#define CONFIG_PPC_P5020
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_CYRUS
-#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
+#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_PPC_P5040)
#error Must call Cyrus CONFIG with a specific CPU enabled.
#endif
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
-#ifdef CONFIG_PPC_P5020
+#ifdef CONFIG_ARCH_P5020
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN
#endif
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
-#if defined(CONFIG_PPC_P5020)
+#if defined(CONFIG_ARCH_P5020)
#define CONFIG_SYS_CLK_FREQ 133000000
#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
#elif defined(CONFIG_PPC_P5040)
CONFIG_PPC_B4420
CONFIG_PPC_B4860
CONFIG_PPC_CLUSTER_START
-CONFIG_PPC_P5020
CONFIG_PPC_P5040
CONFIG_PPC_SPINTABLE_COMPATIBLE
CONFIG_PPC_T1023