[MIPS] Implement flush_cache()

We do Hit_Writeback_Inv_D and Hit_Invalidate_I. You might think that you
don't need to do Hit_Invalidate_I, but flush_cache() needs it since this
function is used not only in U-Boot specfic programs but also at loading
target binaries.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index 7559ac657f40384dded344006b8a7076e5b68c0e..de70c4d6142a430e9fce4d83ce0453abbcded218 100644 (file)
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -25,6 +25,17 @@
 #include <command.h>
 #include <asm/inca-ip.h>
 #include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+
+#define cache_op(op,addr)                                              \
+       __asm__ __volatile__(                                           \
+       "       .set    push                                    \n"     \
+       "       .set    noreorder                               \n"     \
+       "       .set    mips3\n\t                               \n"     \
+       "       cache   %0, %1                                  \n"     \
+       "       .set    pop                                     \n"     \
+       :                                                               \
+       : "i" (op), "R" (*(unsigned char *)(addr)))
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -41,6 +52,17 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 void flush_cache(ulong start_addr, ulong size)
 {
+       unsigned long lsize = CFG_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(Hit_Writeback_Inv_D, start_addr);
+               cache_op(Hit_Invalidate_I, start_addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
 }
 
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)