Add DDR3 support for IGEP COM AQUILA/CYGNUS.
authorEnric Balletbo i Serra <eballetbo@iseebcn.com>
Thu, 4 Apr 2013 22:27:57 +0000 (22:27 +0000)
committerTom Rini <trini@ti.com>
Fri, 10 May 2013 12:25:55 +0000 (08:25 -0400)
These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
arch/arm/include/asm/arch-am33xx/ddr_defs.h

index fb4e78edfed1d69b08b7c4991cafb7f8f7587811..bb53a6a14edc976d9e1a5e3236f1fac41eef7caa 100644 (file)
 #define MT41J512M8RH125_PHY_WR_DATA            0x74
 #define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x06
+#define K4B2G1646EBIH9_EMIF_TIM1               0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2               0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3               0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG              0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF              0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG                  0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF           0x1
+#define K4B2G1646EBIH9_RATIO                   0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT           0x1
+#define K4B2G1646EBIH9_RD_DQS                  0x3B
+#define K4B2G1646EBIH9_WR_DQS                  0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE             0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA             0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE            0x18B
+
 /**
  * Configure DMM
  */