Merge branch 'master' of git://git.denx.de/u-boot-blackfin

diff --combined include/configs/bf537-pnav.h
index 73ad95efe2b7395d3598bfefe4e60f5d31956052,8daebc884672aba73a5cc9f5cf6cbb50f1b046da..39bbb41fb3e0ee2719fafbbb57599efe6f34bbfe
--- 1/include/configs/bf537-pnav.h
--- 2/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@@ -132,6 -132,7 +132,6 @@@
  
  #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
  #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 -#define BFIN_NAND_READY     PF12
  #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@@ -140,7 -141,13 +140,7 @@@
  
  #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
  #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 -#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTHIO() & BFIN_NAND_READY)
 -#define NAND_PLAT_INIT() \
 -      do { \
 -              bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
 -              bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
 -              bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
 -      } while (0)
 +#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
  
  
  /*
@@@ -148,8 -155,6 +148,6 @@@
   */
  #define CONFIG_BFIN_TWI_I2C   1
  #define CONFIG_HARD_I2C               1
- #define CONFIG_SYS_I2C_SPEED          50000
- #define CONFIG_SYS_I2C_SLAVE          0
  
  
  /*

diff --combined include/configs/bf537-stamp.h
index 64e86d64ff26f68c04b8086bd8ac6f65d28926bd,35928627d830597fb6d0330d0ccee304a54ab484..96704d77b060a538df3943ca0a431babec484514
--- 1/include/configs/bf537-stamp.h
--- 2/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@@ -137,8 -137,6 +137,6 @@@
   */
  #define CONFIG_BFIN_TWI_I2C   1
  #define CONFIG_HARD_I2C               1
- #define CONFIG_SYS_I2C_SPEED  50000
- #define CONFIG_SYS_I2C_SLAVE  0
  
  
  /*
@@@ -157,6 -155,7 +155,6 @@@
  
  #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
  #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
 -#define BFIN_NAND_READY     PF3
  #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@@ -165,7 -164,13 +163,7 @@@
  
  #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
  #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 -#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTFIO() & BFIN_NAND_READY)
 -#define NAND_PLAT_INIT() \
 -      do { \
 -              bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
 -              bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
 -              bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
 -      } while (0)
 +#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
  
  
  /*
@@@ -261,8 -266,6 +259,6 @@@
  #define CONFIG_RTC_BFIN
  #define CONFIG_UART_CONSOLE   0
  
- /* #define CONFIG_BF537_STAMP_LEDCMD  1 */
- 
  /* Define if want to do post memory test */
  #undef CONFIG_POST
  #ifdef CONFIG_POST

diff --combined include/configs/bf561-acvilon.h
index ed8d9443b3d44cba74e4cc88e7a7d1a5ba488464,44854c79a273bc5bac4e6c019850bd0617bccac9..0c0204fbd79c76ce51c2e751c71b1c520befae8e
--- 1/include/configs/bf561-acvilon.h
--- 2/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@@ -131,7 -131,6 +131,6 @@@
  #define CONFIG_ENV_SECT_SIZE          (1056 * 8)
  #define CONFIG_ENV_OFFSET                     ((16 + 256) * 1056)
  #define CONFIG_ENV_SIZE                               (8 * 1056)
- #define CONFIG_ENV_OFFSET_REDUND      (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  
  
  /*
@@@ -145,6 -144,7 +144,6 @@@
  
  #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
  #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
 -#define BFIN_NAND_READY     PF10
  #define BFIN_NAND_WRITE(addr, cmd) \
        do { \
                bfin_write8(addr, cmd); \
@@@ -153,7 -153,12 +152,7 @@@
  
  #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
  #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
 -#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
 -#define NAND_PLAT_INIT() \
 -      do { \
 -              bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
 -              bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
 -      } while (0)
 +#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
  
  
  /*