Blackfin: bf537-pnav: new board port
authorMike Frysinger <vapier@gentoo.org>
Mon, 13 Oct 2008 03:08:03 +0000 (23:08 -0400)
committerMike Frysinger <vapier@gentoo.org>
Mon, 15 Jun 2009 00:01:08 +0000 (20:01 -0400)
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
MAINTAINERS
MAKEALL
Makefile
board/bf537-pnav/.gitignore [new file with mode: 0644]
board/bf537-pnav/Makefile [new file with mode: 0644]
board/bf537-pnav/bf537-pnav.c [new file with mode: 0644]
board/bf537-pnav/config.mk [new file with mode: 0644]
board/bf537-pnav/u-boot.lds.S [new file with mode: 0644]
include/configs/bf537-pnav.h [new file with mode: 0644]

index 8d39ffbd19d79b75e64677da85b30c1c06d531f3..1fb55b61520ba521480b56326197c938f0b5c270 100644 (file)
@@ -866,6 +866,7 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
        BF527-EZKIT     BF527
        BF533-EZKIT     BF533
        BF533-STAMP     BF533
+       BF537-PNAV      BF537
        BF537-STAMP     BF537
        BF538F-EZKIT    BF538
        BF548-EZKIT     BF548
diff --git a/MAKEALL b/MAKEALL
index acf5b3ad9d645ced32fdbee3943419fd65c73d59..f0dffe600f2bd281d2b5462b31d5dee613da43bb 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -802,6 +802,7 @@ LIST_blackfin="             \
        bf527-ezkit     \
        bf533-ezkit     \
        bf533-stamp     \
+       bf537-pnav      \
        bf537-stamp     \
        bf538f-ezkit    \
        bf548-ezkit     \
index ee637839c312cbcba89021f8fe96c204de927300..cdda7a34b29bdc2cef5ed4ccf5cb07da50c121d7 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3388,7 +3388,7 @@ suzaku_config:    unconfig
 
 # Analog Devices boards
 BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \
-       bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
+       bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
 
 # Bluetechnix tinyboards
 BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
@@ -3567,6 +3567,7 @@ clean:
               $(obj)board/armltd/{integratorap,integratorcp}/u-boot.lds  \
               $(obj)board/bf5{18f,26,27,33,38f,48,61}-ez{brd,kit}/u-boot.lds \
               $(obj)board/bf5{33,37}-stamp/u-boot.lds                    \
+              $(obj)board/bf537-pnav/u-boot.lds                          \
               $(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds         \
               $(obj)cpu/blackfin/bootrom-asm-offsets.[chs]
        @rm -f $(obj)include/bmp_logo.h
diff --git a/board/bf537-pnav/.gitignore b/board/bf537-pnav/.gitignore
new file mode 100644 (file)
index 0000000..945f324
--- /dev/null
@@ -0,0 +1 @@
+/u-boot.lds
diff --git a/board/bf537-pnav/Makefile b/board/bf537-pnav/Makefile
new file mode 100644 (file)
index 0000000..1b21728
--- /dev/null
@@ -0,0 +1,57 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y        := $(BOARD).o
+
+SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+$(obj)u-boot.lds: u-boot.lds.S
+       $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c
new file mode 100644 (file)
index 0000000..12cfefa
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <netdev.h>
+#include <net.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+       printf("Board: ADI BF537 PNAV board\n");
+       printf("       Support: http://blackfin.uclinux.org/\n");
+       return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+       gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+       return gd->bd->bi_memsize;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+       puts("Warning: Generating 'random' MAC address\n");
+       bfin_gen_rand_mac(mac_addr);
+       eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+       return bfin_EMAC_initialize(bis);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+       uchar enetaddr[6];
+       if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+               board_init_enetaddr(enetaddr);
+#endif
+
+       return 0;
+}
diff --git a/board/bf537-pnav/config.mk b/board/bf537-pnav/config.mk
new file mode 100644 (file)
index 0000000..f4a5a80
--- /dev/null
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/board/bf537-pnav/u-boot.lds.S b/board/bf537-pnav/u-boot.lds.S
new file mode 100644 (file)
index 0000000..8ddfa81
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * U-boot - u-boot.lds.S
+ *
+ * Copyright (c) 2005-2008 Analog Device Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/blackfin.h>
+#undef ALIGN
+#undef ENTRY
+#undef bfin
+
+/* If we don't actually load anything into L1 data, this will avoid
+ * a syntax error.  If we do actually load something into L1 data,
+ * we'll get a linker memory load error (which is what we'd want).
+ * This is here in the first place so we can quickly test building
+ * for different CPU's which may lack non-cache L1 data.
+ */
+#ifndef L1_DATA_B_SRAM
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
+# define L1_DATA_B_SRAM_SIZE 0
+#endif
+
+OUTPUT_ARCH(bfin)
+
+MEMORY
+{
+       ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
+       l1_code : ORIGIN = L1_INST_SRAM,            LENGTH = L1_INST_SRAM_SIZE
+       l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
+}
+
+ENTRY(_start)
+SECTIONS
+{
+       .text :
+       {
+               cpu/blackfin/start.o (.text .text.*)
+
+#ifdef ENV_IS_EMBEDDED
+               /* WARNING - the following is hand-optimized to fit within
+                * the sector before the environment sector. If it throws
+                * an error during compilation remove an object here to get
+                * it linked after the configuration sector.
+                */
+
+               cpu/blackfin/traps.o            (.text .text.*)
+               cpu/blackfin/interrupt.o        (.text .text.*)
+               cpu/blackfin/serial.o           (.text .text.*)
+               common/dlmalloc.o               (.text .text.*)
+               lib_generic/crc32.o             (.text .text.*)
+
+               . = DEFINED(env_offset) ? env_offset : .;
+               common/env_embedded.o   (.text .text.*)
+#endif
+
+               __initcode_start = .;
+               cpu/blackfin/initcode.o (.text .text.*)
+               __initcode_end = .;
+
+               *(.text .text.*)
+       } >ram
+
+       .rodata :
+       {
+               . = ALIGN(4);
+               *(.rodata .rodata.*)
+               *(.rodata1)
+               *(.eh_frame)
+               . = ALIGN(4);
+       } >ram
+
+       .data :
+       {
+               . = ALIGN(256);
+               *(.data .data.*)
+               *(.data1)
+               *(.sdata)
+               *(.sdata2)
+               *(.dynamic)
+               CONSTRUCTORS
+       } >ram
+
+       .u_boot_cmd :
+       {
+               ___u_boot_cmd_start = .;
+               *(.u_boot_cmd)
+               ___u_boot_cmd_end = .;
+       } >ram
+
+       .text_l1 :
+       {
+               . = ALIGN(4);
+               __stext_l1 = .;
+               *(.l1.text)
+               . = ALIGN(4);
+               __etext_l1 = .;
+       } >l1_code AT>ram
+       __stext_l1_lma = LOADADDR(.text_l1);
+
+       .data_l1 :
+       {
+               . = ALIGN(4);
+               __sdata_l1 = .;
+               *(.l1.data)
+               *(.l1.bss)
+               . = ALIGN(4);
+               __edata_l1 = .;
+       } >l1_data AT>ram
+       __sdata_l1_lma = LOADADDR(.data_l1);
+
+       .bss :
+       {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.sbss) *(.scommon)
+               *(.dynbss)
+               *(.bss .bss.*)
+               *(COMMON)
+               __bss_end = .;
+       } >ram
+}
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
new file mode 100644 (file)
index 0000000..11baec8
--- /dev/null
@@ -0,0 +1,172 @@
+/*
+ * U-boot - Configuration file for BF537 PNAV board
+ */
+
+#ifndef __CONFIG_BF537_PNAV_H__
+#define __CONFIG_BF537_PNAV_H__
+
+#include <asm/blackfin-config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *     CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *     SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz                                  */
+#define CONFIG_CLKIN_HZ                        24576000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN            */
+/*                                                1 = CLKIN / 2                */
+#define CONFIG_CLKIN_HALF              0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass    */
+/*                                                1 = bypass PLL       */
+#define CONFIG_PLL_BYPASS              0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL             */
+/* Values can range from 0-63 (where 0 means 64)                       */
+#define CONFIG_VCO_MULT                        20
+/* CCLK_DIV controls the core clock divider                            */
+/* Values can be 1, 2, 4, or 8 ONLY                                    */
+#define CONFIG_CCLK_DIV                        1
+/* SCLK_DIV controls the system clock divider                          */
+/* Values can range from 1-15                                          */
+#define CONFIG_SCLK_DIV                        4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH    10
+#define CONFIG_MEM_SIZE                64
+
+#define CONFIG_EBIU_SDRRC_VAL  0x3b7
+#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL 0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL        0x7BB033B0
+#define CONFIG_EBIU_AMBCTL1_VAL        0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK       1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI       1
+#endif
+#define CONFIG_HOSTNAME                bf537-pnav
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR      02:80:ad:24:21:18 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE          0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      71
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ  30000000
+#define CONFIG_SF_DEFAULT_HZ   30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define ENV_IS_EMBEDDED_CUSTOM
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET      0x4000
+#else
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR                0x20004000
+#define CONFIG_ENV_OFFSET      0x4000
+#endif
+#define CONFIG_ENV_SIZE                0x1000
+#define CONFIG_ENV_SECT_SIZE   0x2000
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+
+#define CONFIG_SYS_NAND_BASE           0x20100000
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_READY     PF12
+#define BFIN_NAND_WRITE(addr, cmd) \
+       do { \
+               bfin_write8(addr, cmd); \
+               SSYNC(); \
+       } while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTHIO() & BFIN_NAND_READY)
+#define NAND_PLAT_INIT() \
+       do { \
+               bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
+               bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
+               bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
+       } while (0)
+
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C    1
+#define CONFIG_HARD_I2C                1
+#define CONFIG_SYS_I2C_SPEED           50000
+#define CONFIG_SYS_I2C_SLAVE           0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE                115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE    0
+
+/* JFFS Partition offset set  */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  15
+
+#define CONFIG_BOOTCOMMAND     "run nandboot"
+#define CONFIG_BOOTARGS_ROOT   "/dev/mtdblock1 rw rootfstype=yaffs"
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#include <asm/blackfin-config-post.h>
+
+#endif