fec_mxc: cleanup and factor out MX27 dependencies
authorJohn Rigby <jcrigby@gmail.com>
Tue, 26 Jan 2010 06:12:55 +0000 (23:12 -0700)
committerTom Rix <Tom.Rix@windriver.com>
Sun, 7 Mar 2010 18:36:36 +0000 (12:36 -0600)
general cleanup
move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c
make MX27 specific phy init conditional on CONFIG_MX27
replace call to imx_get_ahbclk with one to imx_get_fecclk
and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
cpu/arm926ejs/mx27/generic.c
drivers/net/fec_mxc.c
include/asm-arm/arch-mx27/clock.h

index da05c55fb534deffff30b588c638bd26af7355d8..30cf54471212adea3865fcd7e6d61d8557873ba9 100644 (file)
@@ -166,6 +166,11 @@ int print_cpuinfo (void)
 int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
+       struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+       /* enable FEC clock */
+       writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+       writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
        return fecmxc_initialize(bis);
 #else
        return 0;
index 446076fea117a39b71fa8ceded99e7f7dd441065..e027894cffe317b249d9ef751e3145a7fc795c86 100644 (file)
@@ -162,7 +162,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
         * Wake up from sleep if necessary
         * Reset PHY, then delay 300ns
         */
+#ifdef CONFIG_MX27
        miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+#endif
        miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
                        PHY_BMCR_RESET);
        udelay(1000);
@@ -363,7 +365,8 @@ static int fec_open(struct eth_device *edev)
        /*
         * Enable FEC-Lite controller
         */
-       writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+       writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
+               &fec->eth->ecntrl);
 
        miiphy_wait_aneg(edev);
        miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
@@ -490,7 +493,7 @@ static void fec_halt(struct eth_device *dev)
        /*
         * issue graceful stop command to the FEC transmitter if necessary
         */
-       writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+       writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
                        &fec->eth->x_cntrl);
 
        debug("eth_halt: wait for stop regs\n");
@@ -498,7 +501,7 @@ static void fec_halt(struct eth_device *dev)
         * wait for graceful stop to register
         */
        while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
-               ;       /* FIXME ensure time */
+               udelay(1);
 
        /*
         * Disable SmartDMA tasks
@@ -510,7 +513,7 @@ static void fec_halt(struct eth_device *dev)
         * Disable the Ethernet Controller
         * Note: this will also reset the BD index counter!
         */
-       writel(0, &fec->eth->ecntrl);
+       writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
        fec->rbd_index = 0;
        fec->tbd_index = 0;
        debug("eth_halt: done\n");
@@ -569,7 +572,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
         * wait until frame is sent .
         */
        while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
-               /* FIXME: Timeout */
+               udelay(1);
        }
        debug("fec_send: status 0x%x index %d\n",
                        readw(&fec->tbd_base[fec->tbd_index].status),
@@ -688,7 +691,7 @@ static int fec_probe(bd_t *bd)
        fec->xcv_type = MII100;
 
        /* Reset chip. */
-       writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
+       writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
        while (readl(&fec->eth->ecntrl) & 1)
                udelay(10);
 
index 472e8f2427e9a62e8e3cf446f87d90e42c8eade6..7e9c7aabb00cc71554eeb40a91e068d058886b21 100644 (file)
@@ -37,5 +37,6 @@ ulong imx_get_perclk3(void);
 ulong imx_get_ahbclk(void);
 
 #define imx_get_uartclk imx_get_perclk1
+#define imx_get_fecclk imx_get_ahbclk
 
 #endif /* __ASM_ARCH_CLOCK_H */