spi0 = &qspi;
spi1 = &spi0;
spi2 = &spi1;
- mmc = &mmc;
};
cpus {
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
+ bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
arm,data-latency = <2 1 1>;
};
- mmc: dwmmc0@ff704000 {
+ mmc0: dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
interrupts = <0 139 4>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
};
&gmac1 {
&mmc0 {
vmmc-supply = <®ulator_3_3v>;
vqmmc-supply = <®ulator_3_3v>;
+ bus-width = <4>;
+ u-boot,dm-pre-reloc;
};
&usb1 {
cap-sd-highspeed;
};
- ethernet@ff702000 {
- phy-mode = "rgmii";
- phy-addr = <0xffffffff>; /* probe for phy addr */
- status = "okay";
- };
-
sysmgr@ffd08000 {
cpu1-start-addr = <0xffd080c4>;
};
&gmac1 {
status = "okay";
+ phy-mode = "rgmii";
};
&i2c0 {
};
};
-&mmc {
+&mmc0 {
status = "okay";
};
if ARCH_SOCFPGA
+config TARGET_SOCFPGA_ARRIA5
+ bool
+
+config TARGET_SOCFPGA_CYCLONE5
+ bool
+
choice
prompt "Altera SOCFPGA board select"
optional
-config TARGET_SOCFPGA_ARRIA5
- bool "Altera SOCFPGA Arria V"
+config TARGET_SOCFPGA_ARRIA5_SOCDK
+ bool "Altera SOCFPGA SoCDK (Arria V)"
+ select TARGET_SOCFPGA_ARRIA5
-config TARGET_SOCFPGA_CYCLONE5
- bool "Altera SOCFPGA Cyclone V"
+config TARGET_SOCFPGA_CYCLONE5_SOCDK
+ bool "Altera SOCFPGA SoCDK (Cyclone V)"
+ select TARGET_SOCFPGA_CYCLONE5
endchoice
config SYS_BOARD
- default "socfpga"
+ default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
config SYS_VENDOR
- default "altera"
+ default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
- default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5
- default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5
+ default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
endif
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
fpga_manager.o scan_manager.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+
+# QTS-generated config file wrappers
+obj-y += wrap_pll_config.o
+obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
+ wrap_sdram_config.o
+CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
+CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
+CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
+CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
void cm_basic_init(const struct cm_config * const cfg)
{
- uint32_t start, timeout;
+ unsigned long end;
/* Start by being paranoid and gate all sw managed clocks */
writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
/*
- * Time starts here
- * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
+ * Time starts here. Must wait 7 us from
+ * BGPWRDN_SET(0) to VCO_ENABLE_SET(1).
*/
- start = get_timer(0);
- /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
- timeout = 7;
+ end = timer_get_us() + 7;
/* main mpu */
writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
/* 7 us must have elapsed before we can enable the VCO */
- while (get_timer(start) < timeout)
+ while (timer_get_us() < end)
;
/* Enable vco */
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
#include <asm/arch/freeze_controller.h>
-#include <asm/arch/timer.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
u32 reg_cfg_mask;
u32 reg_value;
u32 channel_id;
+ unsigned long eosc1_freq;
/* select software FSM */
writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
setbits_le32(&freeze_controller_base->hioctrl,
SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
- /*
- * Delay 1000 intosc. intosc is based on eosc1
- * Use worst case which is fatest eosc1=50MHz, delay required
- * is 1/50MHz * 1000 = 20us
- */
- udelay(20);
+ /* Delay 1000 intosc cycles. The intosc is based on eosc1. */
+ eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */
+ udelay(DIV_ROUND_UP(1000000, eosc1_freq));
/*
* de-assert active low bhniotri signals,
void sysmgr_pinmux_init(void);
void sysmgr_config_warmrstcfgio(int enable);
-void sysmgr_get_pinmux_table(const unsigned long **table,
- unsigned int *table_len);
+void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
#endif
struct socfpga_system_manager {
--- /dev/null
+#!/bin/sh
+
+#
+# Process iocsr_config_*.[ch]
+# $1: SoC type
+# $2: Input directory
+# $3: Output directory
+#
+process_iocsr_config() {
+ soc="$1"
+ in_dir="$2"
+ out_dir="$3"
+
+ (
+ cat << EOF
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+EOF
+
+ # Retrieve the scan chain lengths
+ grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \
+ ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()"
+
+ echo ""
+
+ # Retrieve the scan chain config and zap the ad-hoc length encoding
+ sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \
+ ${in_dir}/generated/iocsr_config_${soc}.c
+
+ cat << EOF
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
+EOF
+ ) > "${out_dir}/iocsr_config.h"
+}
+
+#
+# Process pinmux_config_*.c (and ignore pinmux_config.h)
+# $1: SoC type
+# $2: Input directory
+# $3: Output directory
+#
+process_pinmux_config() {
+ soc="$1"
+ in_dir="$2"
+ out_dir="$3"
+
+ (
+ cat << EOF
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+EOF
+
+ # Retrieve the pinmux config and zap the ad-hoc length encoding
+ sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \
+ ${in_dir}/generated/pinmux_config_${soc}.c
+
+ cat << EOF
+
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
+EOF
+ ) > "${out_dir}/pinmux_config.h"
+}
+
+#
+# Process pll_config.h
+# $1: SoC type (not used)
+# $2: Input directory
+# $3: Output directory
+#
+process_pll_config() {
+ soc="$1"
+ in_dir="$2"
+ out_dir="$3"
+
+ (
+ cat << EOF
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+EOF
+
+ # Retrieve the pll config and zap parenthesis
+ sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \
+ ${in_dir}/generated/pll_config.h
+
+ cat << EOF
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
+EOF
+ ) > "${out_dir}/pll_config.h"
+}
+
+#
+# Filter out only the macros which are actually used by the code
+#
+grep_sdram_config() {
+ egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]"
+}
+
+#
+# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
+# $1: SoC type (not used)
+# $2: Input directory
+# $3: Output directory
+#
+process_sdram_config() {
+ soc="$1"
+ in_dir="$2"
+ out_dir="$3"
+
+ (
+ cat << EOF
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+EOF
+
+ echo "/* SDRAM configuration */"
+ # Retrieve the sdram config, zap broken lines and zap parenthesis
+ sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h |
+ sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
+ sort -u | grep_sdram_config
+
+ echo ""
+ echo "/* Sequencer auto configuration */"
+ sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
+ ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config
+
+ echo ""
+ echo "/* Sequencer defines configuration */"
+ sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \
+ ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config
+
+ echo ""
+ echo "/* Sequencer ac_rom_init configuration */"
+ sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
+ ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c
+
+ echo ""
+ echo "/* Sequencer inst_rom_init configuration */"
+ sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\
+ ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c
+
+ cat << EOF
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
+EOF
+ ) > "${out_dir}/sdram_config.h"
+}
+
+usage() {
+ echo "$0 [soc_type] [input_dir] [output_dir]"
+ echo "Process QTS-generated headers into U-Boot compatible ones."
+ echo ""
+ echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5',"
+ echo " input_dir\t\tDirectory with the QTS project."
+ echo " output_dir\t\tDirectory to store the U-Boot compatible headers."
+ echo ""
+}
+
+soc="$1"
+in_dir="$2"
+out_dir="$3"
+
+if [ "$#" -ne 3 ] ; then
+ usage
+ exit 1
+fi
+
+if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then
+ usage
+ exit 3
+fi
+
+process_iocsr_config "${soc}" "${in_dir}" "${out_dir}"
+process_pinmux_config "${soc}" "${in_dir}" "${out_dir}"
+process_pll_config "${soc}" "${in_dir}" "${out_dir}"
+process_sdram_config "${soc}" "${in_dir}" "${out_dir}"
void sysmgr_pinmux_init(void)
{
uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
- const unsigned long *sys_mgr_init_table;
+ const u8 *sys_mgr_init_table;
unsigned int len;
int i;
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/clock_manager.h>
+
+/* Board-specific header. */
+#include <qts/iocsr_config.h>
+
+int iocsr_get_config_table(const unsigned int chain_id,
+ const unsigned long **table,
+ unsigned int *table_len)
+{
+ switch (chain_id) {
+ case 0:
+ *table = iocsr_scan_chain0_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+ break;
+ case 1:
+ *table = iocsr_scan_chain1_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+ break;
+ case 2:
+ *table = iocsr_scan_chain2_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+ break;
+ case 3:
+ *table = iocsr_scan_chain3_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+
+/* Board-specific header. */
+#include <qts/pinmux_config.h>
+
+void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len)
+{
+ *table = sys_mgr_init_table;
+ *table_len = ARRAY_SIZE(sys_mgr_init_table);
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <qts/pll_config.h>
+
+#define MAIN_VCO_BASE ( \
+ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+#define PERI_VCO_BASE ( \
+ (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
+ CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
+ (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+#define SDR_VCO_BASE ( \
+ (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
+ (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+static const struct cm_config cm_default_cfg = {
+ /* main group */
+ MAIN_VCO_BASE,
+ (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+ CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+ CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+ CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+ CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+ CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+ CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+ CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
+
+ /* peripheral group */
+ PERI_VCO_BASE,
+ (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+ CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+ CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+ CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+ CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+ CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+ CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+ CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+ CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+ CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+ CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+ CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
+
+ /* sdram pll group */
+ SDR_VCO_BASE,
+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+};
+
+const struct cm_config * const cm_get_default_config(void)
+{
+ return &cm_default_cfg;
+}
+
+const unsigned int cm_get_osc_clk_hz(const int osc)
+{
+ if (osc == 1)
+ return CONFIG_HPS_CLK_OSC1_HZ;
+ else if (osc == 2)
+ return CONFIG_HPS_CLK_OSC2_HZ;
+ else
+ return 0;
+}
+
+const unsigned int cm_get_f2s_per_ref_clk_hz(void)
+{
+ return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+}
+
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
+{
+ return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+}
--- /dev/null
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/sdram.h>
+
+/* Board-specific header. */
+#include <qts/sdram_config.h>
+
+static const struct socfpga_sdram_config sdram_config = {
+ .ctrl_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+ SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
+ .dram_timing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
+ .dram_timing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
+ .dram_timing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
+ .dram_timing4 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
+ .lowpwr_timing =
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
+ .dram_odt =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+ SDR_CTRLGRP_DRAMODT_READ_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+ SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+ .dram_addrw =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
+ ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
+ .dram_if_width =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+ SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
+ .dram_dev_width =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+ SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
+ .dram_intr =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+ SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
+ .lowpwr_eq =
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+ SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
+ .static_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
+ .ctrl_width =
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+ SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
+ .cport_width =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+ SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
+ .cport_wmap =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+ SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
+ .cport_rmap =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+ SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
+ .rfifo_cmap =
+ (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+ SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
+ .wfifo_cmap =
+ (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+ SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
+ .cport_rdwr =
+ (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+ SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
+ .port_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+ SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
+ .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+ .fifo_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
+ .mp_priority =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+ SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
+ .mp_weight0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
+ .mp_weight1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
+ .mp_weight2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
+ .mp_weight3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
+ .mp_pacing0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
+ .mp_pacing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
+ .mp_pacing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
+ .mp_pacing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
+ .mp_threshold0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
+ .mp_threshold1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
+ .mp_threshold2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
+ .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+};
+
+static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
+ .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
+ .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ .activate_1 = RW_MGR_ACTIVATE_1,
+ .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
+ .guaranteed_read = RW_MGR_GUARANTEED_READ,
+ .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
+ .guaranteed_write = RW_MGR_GUARANTEED_WRITE,
+ .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
+ .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
+ .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
+ .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
+ .idle = RW_MGR_IDLE,
+ .idle_loop1 = RW_MGR_IDLE_LOOP1,
+ .idle_loop2 = RW_MGR_IDLE_LOOP2,
+ .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
+ .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
+ .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
+ .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
+ .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
+ .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
+ .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
+ .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
+ .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
+ .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
+ .mrs0_user = RW_MGR_MRS0_USER,
+ .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
+ .mrs1 = RW_MGR_MRS1,
+ .mrs1_mirr = RW_MGR_MRS1_MIRR,
+ .mrs2 = RW_MGR_MRS2,
+ .mrs2_mirr = RW_MGR_MRS2_MIRR,
+ .mrs3 = RW_MGR_MRS3,
+ .mrs3_mirr = RW_MGR_MRS3_MIRR,
+ .precharge_all = RW_MGR_PRECHARGE_ALL,
+ .read_b2b = RW_MGR_READ_B2B,
+ .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
+ .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
+ .refresh_all = RW_MGR_REFRESH_ALL,
+ .rreturn = RW_MGR_RETURN,
+ .sgle_read = RW_MGR_SGLE_READ,
+ .zqcl = RW_MGR_ZQCL,
+
+ .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
+ .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
+ .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
+ .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
+ .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
+ .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
+ .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
+ .mem_virtual_groups_per_read_dqs =
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
+ .mem_virtual_groups_per_write_dqs =
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
+};
+
+struct socfpga_sdram_io_config io_config = {
+ .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
+ .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
+ .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
+ .dll_chain_length = IO_DLL_CHAIN_LENGTH,
+ .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
+ .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
+ .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
+ .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
+ .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
+ .dqs_in_reserve = IO_DQS_IN_RESERVE,
+ .dqs_out_reserve = IO_DQS_OUT_RESERVE,
+ .io_in_delay_max = IO_IO_IN_DELAY_MAX,
+ .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
+ .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
+ .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
+};
+
+struct socfpga_sdram_misc_config misc_config = {
+ .afi_rate_ratio = AFI_RATE_RATIO,
+ .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
+ .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
+ .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
+ .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
+ .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
+ .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
+ .tinit_cntr0_val = TINIT_CNTR0_VAL,
+ .tinit_cntr1_val = TINIT_CNTR1_VAL,
+ .tinit_cntr2_val = TINIT_CNTR2_VAL,
+ .treset_cntr0_val = TRESET_CNTR0_VAL,
+ .treset_cntr1_val = TRESET_CNTR1_VAL,
+ .treset_cntr2_val = TRESET_CNTR2_VAL,
+};
+
+const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
+{
+ return &sdram_config;
+}
+
+void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
+{
+ *init = ac_rom_init;
+ *nelem = ARRAY_SIZE(ac_rom_init);
+}
+
+void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
+{
+ *init = inst_rom_init;
+ *nelem = ARRAY_SIZE(inst_rom_init);
+}
+
+const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
+{
+ return &rw_mgr_config;
+}
+
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
+{
+ return &io_config;
+}
+
+const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
+{
+ return &misc_config;
+}
--- /dev/null
+SOCFPGA BOARD
+M: Dinh Nguyen <dinguyen@altera.com>
+M: Chin-Liang See <clsee@altera.com>
+S: Maintained
+F: board/altera/arria5-socdk/
+F: include/configs/socfpga_arria5.h
+F: configs/socfpga_arria5_defconfig
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
--- /dev/null
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000060,
+ 0x00018060,
+ 0x06018060,
+ 0x00004000,
+ 0x0C0300C0,
+ 0x0C030000,
+ 0x00000030,
+ 0x00000000,
+ 0x00000000,
+ 0x00002000,
+ 0x00000000,
+ 0x00000000,
+ 0x06000000,
+ 0x00006018,
+ 0x01806018,
+ 0x00001000,
+ 0x0000C030,
+ 0x04000000,
+ 0x03000000,
+ 0x0000300C,
+ 0x00000000,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x01800000,
+ 0x00000006,
+ 0x00001806,
+ 0x00000400,
+ 0x0000300C,
+ 0x00C03000,
+ 0x00C00000,
+ 0x00000003,
+ 0x00000C03,
+ 0x00000200,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x00100000,
+ 0x300C0000,
+ 0x300000C0,
+ 0x000000C0,
+ 0x000300C0,
+ 0x00008000,
+ 0x00060180,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x000300C0,
+ 0x10000000,
+ 0x0C000000,
+ 0x00000030,
+ 0x0000C030,
+ 0x00002000,
+ 0x06018060,
+ 0x06018000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x0000C030,
+ 0x0300C000,
+ 0x03000000,
+ 0x0000300C,
+ 0x0000300C,
+ 0x00000800,
+ 0x00006018,
+ 0x01806000,
+ 0x01800000,
+ 0x00000006,
+ 0x00002000,
+ 0x00000400,
+ 0x0000300C,
+ 0x01000000,
+ 0x00000000,
+ 0x00000004,
+ 0x00000C03,
+ 0x00000200,
+ 0x00001806,
+ 0x00800000,
+ 0x00000000,
+ 0x00000002,
+ 0x00000800,
+ 0x00000100,
+ 0x00001000,
+ 0x00400000,
+ 0xC0300000,
+ 0x00000000,
+ 0x00000400,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x00100000,
+ 0x40000000,
+ 0x00000000,
+ 0x00000100,
+ 0x00040000,
+ 0x00008000,
+ 0x18060180,
+ 0x20000000,
+ 0x00000000,
+ 0x00000080,
+ 0x00020000,
+ 0x00004000,
+ 0x00040000,
+ 0x10000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00002000,
+ 0x10038060,
+ 0x00000000,
+ 0x00000000,
+ 0x00000020,
+ 0x01806018,
+ 0x00001000,
+ 0x00010000,
+ 0x04000000,
+ 0x03000000,
+ 0x0000801C,
+ 0x00004000,
+ 0x00000800,
+ 0x01806018,
+ 0x02000000,
+ 0x00000000,
+ 0x00000008,
+ 0x00002000,
+ 0x00000400,
+ 0x00C0300C,
+ 0x00C03000,
+ 0x00C00003,
+ 0x00000C03,
+ 0x00300C03,
+ 0x00000200,
+ 0x00601806,
+ 0x80601800,
+ 0x80600001,
+ 0x80000601,
+ 0x00180601,
+ 0x00000100,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x2C820D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D0000,
+ 0x24906808,
+ 0x00A28340,
+ 0xD000001A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000050,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00040,
+ 0xA20D0002,
+ 0x24906808,
+ 0x00A28340,
+ 0xD005141A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x01000000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x04510680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x8341D348,
+ 0x821A0124,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00400000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC055F80,
+ 0xFFFFFFFF,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00481800,
+ 0x001A1A1A,
+ 0x085506A0,
+ 0x0000E1D4,
+ 0x045506A0,
+ 0x0000E1D4,
+ 0x085506A0,
+ 0x8000E1D4,
+ 0x00000200,
+ 0x00000004,
+ 0x04000000,
+ 0x00000009,
+ 0x00002410,
+ 0x00000040,
+ 0x41000000,
+ 0x00002082,
+ 0x00000350,
+ 0x000000DA,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x022A8350,
+ 0x000070EA,
+ 0x86000000,
+ 0x08000004,
+ 0x00000000,
+ 0x00482000,
+ 0x21800000,
+ 0x00101061,
+ 0x021541A8,
+ 0x00003875,
+ 0x011541A8,
+ 0x00003875,
+ 0x021541A8,
+ 0x20003875,
+ 0x00000080,
+ 0x00000001,
+ 0x41000000,
+ 0x00000002,
+ 0x00FF0904,
+ 0x00000000,
+ 0x90400000,
+ 0x00000820,
+ 0xC0000001,
+ 0xFFD602AF,
+ 0x86FFFFFF,
+ 0x0A0A78B4,
+ 0x000D020A,
+ 0x00006800,
+ 0x028A4320,
+ 0xEC2CB23D,
+ 0x8F5D1451,
+ 0xA47A88A2,
+ 0x0001A0E9,
+ 0x00410D00,
+ 0x40000068,
+ 0x3D000003,
+ 0x51EC2CB2,
+ 0xA28F5D14,
+ 0xE9A47A88,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000540,
+ 0x000003A8,
+ 0x08AA0D40,
+ 0x8001C3A8,
+ 0x0000007F,
+ 0x00000000,
+ 0x00004060,
+ 0xE1208000,
+ 0x0000001F,
+ 0x00004100,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 3, /* EMACIO14 */
+ 3, /* EMACIO15 */
+ 3, /* EMACIO16 */
+ 3, /* EMACIO17 */
+ 3, /* EMACIO18 */
+ 3, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 3, /* GENERALIO0 */
+ 3, /* GENERALIO1 */
+ 3, /* GENERALIO2 */
+ 3, /* GENERALIO3 */
+ 3, /* GENERALIO4 */
+ 3, /* GENERALIO5 */
+ 3, /* GENERALIO6 */
+ 3, /* GENERALIO7 */
+ 3, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 3, /* GENERALIO15 */
+ 3, /* GENERALIO16 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 3, /* GENERALIO23 */
+ 3, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 0, /* MIXED1IO1 */
+ 0, /* MIXED1IO2 */
+ 0, /* MIXED1IO3 */
+ 0, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 0, /* MIXED1IO8 */
+ 0, /* MIXED1IO9 */
+ 0, /* MIXED1IO10 */
+ 0, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 3, /* MIXED2IO0 */
+ 3, /* MIXED2IO1 */
+ 3, /* MIXED2IO2 */
+ 3, /* MIXED2IO3 */
+ 3, /* MIXED2IO4 */
+ 3, /* MIXED2IO5 */
+ 3, /* MIXED2IO6 */
+ 3, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 350000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 0
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 2
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x48
+#define RW_MGR_GUARANTEED_READ 0x4B
+#define RW_MGR_GUARANTEED_READ_CONT 0x53
+#define RW_MGR_GUARANTEED_WRITE 0x17
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7A
+#define RW_MGR_IDLE_LOOP2 0x79
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
+#define RW_MGR_INIT_RESET_1_CKE_0 0x73
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x58
+#define RW_MGR_READ_B2B_WAIT1 0x60
+#define RW_MGR_READ_B2B_WAIT2 0x6A
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7C
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 8
+#define CALIB_VFIFO_OFFSET 6
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 234
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 15
+#define IO_DQS_EN_DELAY_OFFSET 16
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 6
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 5
+#define RW_MGR_MEM_DATA_WIDTH 40
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
+#define TINIT_CNTR0_VAL 132
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 132
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] ={
+ 0x20700000,
+ 0x20780000,
+ 0x10080831,
+ 0x10080930,
+ 0x10090004,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080849,
+ 0x100808c8,
+ 0x100a0004,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] ={
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
--- /dev/null
+SOCFPGA BOARD
+M: Dinh Nguyen <dinguyen@altera.com>
+M: Chin-Liang See <clsee@altera.com>
+S: Maintained
+F: board/altera/cyclone5-socdk/
+F: include/configs/socfpga_cyclone5.h
+F: configs/socfpga_cyclone5_defconfig
+
+SOCRATES BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: configs/socfpga_socrates_defconfig
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := socfpga.o
--- /dev/null
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x0FF00000,
+ 0xC0000000,
+ 0x0000003F,
+ 0x00008000,
+ 0x00020080,
+ 0x08020000,
+ 0x08000000,
+ 0x00018020,
+ 0x00000000,
+ 0x00004000,
+ 0x00010040,
+ 0x04010000,
+ 0x04000000,
+ 0x00000010,
+ 0x00004010,
+ 0x00002000,
+ 0x00020000,
+ 0x02008000,
+ 0x02000000,
+ 0x00000008,
+ 0x00002008,
+ 0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+ 0x000C0300,
+ 0x10040000,
+ 0x100000C0,
+ 0x00000040,
+ 0x00010040,
+ 0x00008000,
+ 0x00080000,
+ 0x18060000,
+ 0x18000000,
+ 0x00000060,
+ 0x00018060,
+ 0x00004000,
+ 0x00010040,
+ 0x10000000,
+ 0x04000000,
+ 0x00000010,
+ 0x00004010,
+ 0x00002000,
+ 0x06008020,
+ 0x02008000,
+ 0x01FE0000,
+ 0xF8000000,
+ 0x00000007,
+ 0x00001000,
+ 0x00004010,
+ 0x01004000,
+ 0x01000000,
+ 0x00003004,
+ 0x00001004,
+ 0x00000800,
+ 0x00000000,
+ 0x00000000,
+ 0x00800000,
+ 0x00000002,
+ 0x00002000,
+ 0x00000400,
+ 0x00000000,
+ 0x00401000,
+ 0x00000003,
+ 0x00000000,
+ 0x00000000,
+ 0x00000200,
+ 0x00600802,
+ 0x00000000,
+ 0x80200000,
+ 0x80000600,
+ 0x00000200,
+ 0x00000100,
+ 0x00300401,
+ 0xC0100400,
+ 0x40100000,
+ 0x40000300,
+ 0x000C0100,
+ 0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+ 0x80040100,
+ 0x00000000,
+ 0x0FF00000,
+ 0x00000000,
+ 0x0C010040,
+ 0x00008000,
+ 0x18020080,
+ 0x00000000,
+ 0x08000000,
+ 0x00040020,
+ 0x06018060,
+ 0x00004000,
+ 0x0C010040,
+ 0x04010000,
+ 0x00000030,
+ 0x00000000,
+ 0x03004010,
+ 0x00002000,
+ 0x06008020,
+ 0x02008000,
+ 0x02000018,
+ 0x00006008,
+ 0x01802008,
+ 0x00001000,
+ 0x03004010,
+ 0x01004000,
+ 0x0100000C,
+ 0x00003004,
+ 0x00C01004,
+ 0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+ 0x2C420D80,
+ 0x082000FF,
+ 0x0A804001,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000000,
+ 0x00000021,
+ 0x82000004,
+ 0x05400000,
+ 0x03C80000,
+ 0x04010000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0xE4400000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x00000001,
+ 0x40000002,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000070,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00A28,
+ 0xA20D0000,
+ 0x24906808,
+ 0x00A28340,
+ 0xD000001A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x0A800001,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x0A800000,
+ 0x07900000,
+ 0x08020000,
+ 0x00100000,
+ 0xC8800000,
+ 0x00003001,
+ 0x00C00722,
+ 0x00000FF0,
+ 0x72200000,
+ 0x80000C00,
+ 0x05400000,
+ 0x02480000,
+ 0x04000000,
+ 0x00080000,
+ 0x05400000,
+ 0x03C80000,
+ 0x05400000,
+ 0x03C80000,
+ 0x6A1C0000,
+ 0x00001800,
+ 0x00600391,
+ 0x800E4400,
+ 0x1A870001,
+ 0x40000600,
+ 0x02A00040,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x02A00000,
+ 0x01E40000,
+ 0x72200000,
+ 0x80000C00,
+ 0x003001C8,
+ 0xC0072200,
+ 0x1C880000,
+ 0x20000300,
+ 0x00040000,
+ 0x50670000,
+ 0x00000070,
+ 0x24590000,
+ 0x00001000,
+ 0xA0000034,
+ 0x0D000001,
+ 0x906808A2,
+ 0xA2834024,
+ 0x05141A00,
+ 0x808A20D0,
+ 0x34024906,
+ 0x01A00040,
+ 0xA20D0002,
+ 0x24906808,
+ 0x00A28340,
+ 0xD005141A,
+ 0x06808A20,
+ 0x10040000,
+ 0x00200000,
+ 0x10040000,
+ 0x00200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x15000000,
+ 0x0F200000,
+ 0x01FE0000,
+ 0x00000000,
+ 0x01800E44,
+ 0x00391000,
+ 0x007F8006,
+ 0x00000000,
+ 0x99300001,
+ 0x34343400,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x000001C1,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x04510680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x00003FC2,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00015000,
+ 0x0000F200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00600391,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x8341D348,
+ 0x821A0124,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x0002A000,
+ 0x0001E400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0xC880090C,
+ 0x00003001,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x00120800,
+ 0x00002000,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F3690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0xAA0D4000,
+ 0x01C3A808,
+ 0xAA0D4000,
+ 0x01C3A810,
+ 0x00040100,
+ 0x00000800,
+ 0x00000000,
+ 0x00001208,
+ 0x00482000,
+ 0x00008000,
+ 0x00000000,
+ 0x00410482,
+ 0x0006A000,
+ 0x0001B400,
+ 0x00020000,
+ 0x00000400,
+ 0x00020080,
+ 0x00000400,
+ 0x5506A000,
+ 0x00E1D404,
+ 0x00000000,
+ 0x0000090C,
+ 0x00000010,
+ 0x90400000,
+ 0x00000000,
+ 0x2020C243,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x2A835000,
+ 0x0070EA02,
+ 0x2A835000,
+ 0x0070EA04,
+ 0x00010040,
+ 0x00000200,
+ 0x00000000,
+ 0x00000482,
+ 0x40120800,
+ 0x00000070,
+ 0x80000000,
+ 0x00104120,
+ 0x00000200,
+ 0xAC255F80,
+ 0xF1C71C71,
+ 0x14F1690D,
+ 0x1A041414,
+ 0x00D00000,
+ 0x14864000,
+ 0x59647A05,
+ 0xBA28A3D8,
+ 0xF511451E,
+ 0x0341D348,
+ 0x821A0000,
+ 0x0000D000,
+ 0x00000680,
+ 0xD859647A,
+ 0x1EBA28A3,
+ 0x48F51145,
+ 0x000341D3,
+ 0x00080200,
+ 0x00001000,
+ 0x00080200,
+ 0x00001000,
+ 0x000A8000,
+ 0x00075000,
+ 0x541A8000,
+ 0x03875011,
+ 0x10000000,
+ 0x00000000,
+ 0x0080C000,
+ 0x41000000,
+ 0x04000002,
+ 0x00820000,
+ 0x00489800,
+ 0x001A1A1A,
+ 0x085506A0,
+ 0x0000E1D4,
+ 0x045506A0,
+ 0x0000E1D4,
+ 0x085506A0,
+ 0x8000E1D4,
+ 0x00000200,
+ 0x00000004,
+ 0x04000000,
+ 0x00000009,
+ 0x00002410,
+ 0x00000040,
+ 0x41000000,
+ 0x00002082,
+ 0x00000350,
+ 0x000000DA,
+ 0x00000100,
+ 0x40000002,
+ 0x00000100,
+ 0x00000002,
+ 0x022A8350,
+ 0x000070EA,
+ 0x86000000,
+ 0x08000004,
+ 0x00000000,
+ 0x00482000,
+ 0x21800000,
+ 0x00101061,
+ 0x021541A8,
+ 0x00003875,
+ 0x011541A8,
+ 0x00003875,
+ 0x021541A8,
+ 0x20003875,
+ 0x00000080,
+ 0x00000001,
+ 0x41000000,
+ 0x00000002,
+ 0x00FF0904,
+ 0x00000000,
+ 0x90400000,
+ 0x00000820,
+ 0xC0000001,
+ 0x38D612AF,
+ 0x86F8E38E,
+ 0x0A0A78B4,
+ 0x000D020A,
+ 0x00006800,
+ 0x028A4320,
+ 0xEC2CB23D,
+ 0x8F5D1451,
+ 0xA47A88A2,
+ 0x0001A0E9,
+ 0x00410D00,
+ 0x40000068,
+ 0x3D000003,
+ 0x51EC2CB2,
+ 0xA28F5D14,
+ 0xE9A47A88,
+ 0x000001A0,
+ 0x00000401,
+ 0x00000008,
+ 0x00000401,
+ 0x00000008,
+ 0x00000540,
+ 0x000003A8,
+ 0x08AA0D40,
+ 0x8001C3A8,
+ 0x0000007F,
+ 0x00000000,
+ 0x00004060,
+ 0xE1208000,
+ 0x0000001F,
+ 0x00004100,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+ 3, /* EMACIO0 */
+ 3, /* EMACIO1 */
+ 3, /* EMACIO2 */
+ 3, /* EMACIO3 */
+ 3, /* EMACIO4 */
+ 3, /* EMACIO5 */
+ 3, /* EMACIO6 */
+ 3, /* EMACIO7 */
+ 3, /* EMACIO8 */
+ 3, /* EMACIO9 */
+ 3, /* EMACIO10 */
+ 3, /* EMACIO11 */
+ 3, /* EMACIO12 */
+ 3, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 3, /* FLASHIO4 */
+ 3, /* FLASHIO5 */
+ 3, /* FLASHIO6 */
+ 3, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 0, /* GENERALIO3 */
+ 0, /* GENERALIO4 */
+ 1, /* GENERALIO5 */
+ 1, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 0, /* GENERALIO9 */
+ 0, /* GENERALIO10 */
+ 0, /* GENERALIO11 */
+ 0, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 0, /* GENERALIO15 */
+ 0, /* GENERALIO16 */
+ 2, /* GENERALIO17 */
+ 2, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 0, /* MIXED1IO0 */
+ 1, /* MIXED1IO1 */
+ 1, /* MIXED1IO2 */
+ 1, /* MIXED1IO3 */
+ 1, /* MIXED1IO4 */
+ 0, /* MIXED1IO5 */
+ 0, /* MIXED1IO6 */
+ 0, /* MIXED1IO7 */
+ 1, /* MIXED1IO8 */
+ 1, /* MIXED1IO9 */
+ 1, /* MIXED1IO10 */
+ 1, /* MIXED1IO11 */
+ 0, /* MIXED1IO12 */
+ 0, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 1, /* MIXED1IO15 */
+ 1, /* MIXED1IO16 */
+ 1, /* MIXED1IO17 */
+ 1, /* MIXED1IO18 */
+ 0, /* MIXED1IO19 */
+ 0, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 100000000
+#define CONFIG_HPS_CLK_CAN1_HZ 100000000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
--- /dev/null
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE 0x48
+#define RW_MGR_GUARANTEED_READ 0x4B
+#define RW_MGR_GUARANTEED_READ_CONT 0x53
+#define RW_MGR_GUARANTEED_WRITE 0x17
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_IDLE_LOOP1 0x7C
+#define RW_MGR_IDLE_LOOP2 0x7B
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
+#define RW_MGR_INIT_RESET_1_CKE_0 0x73
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_MRS1 0x03
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_MRS3 0x05
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_READ_B2B 0x58
+#define RW_MGR_READ_B2B_WAIT1 0x60
+#define RW_MGR_READ_B2B_WAIT2 0x6A
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_SGLE_READ 0x7E
+#define RW_MGR_ZQCL 0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO 1
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 6
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_DATA_MASK_WIDTH 5
+#define RW_MGR_MEM_DATA_WIDTH 40
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
+#define TINIT_CNTR0_VAL 132
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TRESET_CNTR0_VAL 132
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] ={
+ 0x20700000,
+ 0x20780000,
+ 0x10080431,
+ 0x10080530,
+ 0x10090004,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080449,
+ 0x100804c8,
+ 0x100a0004,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] ={
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x0,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xa080,
+ 0x8080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
+#include <micrel.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+/*
+ * PHY configuration
+ */
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+int board_phy_config(struct phy_device *phydev)
+{
+ int ret;
+ /*
+ * These skew settings for the KSZ9021 ethernet phy is required for ethernet
+ * to work reliably on most flavors of cyclone5 boards.
+ */
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
+ 0x0);
+ if (ret)
+ return ret;
+
+ ret = ksz9021_phy_extended_write(phydev,
+ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
+ 0xf0f0);
+ if (ret)
+ return ret;
+
+ if (phydev->drv->config)
+ return phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
+++ /dev/null
-SOCFPGA BOARD
-M: Dinh Nguyen <dinguyen@altera.com>
-M: Chin-Liang See <clsee@altera.com>
-S: Maintained
-F: board/altera/socfpga/
-F: include/configs/socfpga_cyclone5.h
-F: configs/socfpga_cyclone5_defconfig
-
-SOCRATES BOARD
-M: Stefan Roese <sr@denx.de>
-S: Maintained
-F: configs/socfpga_socrates_defconfig
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := socfpga.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
- wrap_sdram_config.o
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* This file is generated by Preloader Generator */
-
-#include "iocsr_config.h"
-
-#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
-const unsigned long iocsr_scan_chain0_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
- 0x00000000,
- 0x00000000,
- 0x0FF00000,
- 0xC0000000,
- 0x0000003F,
- 0x00008000,
- 0x00020080,
- 0x08020000,
- 0x08000000,
- 0x00018020,
- 0x00000000,
- 0x00004000,
- 0x00010040,
- 0x04010000,
- 0x04000000,
- 0x00000010,
- 0x00004010,
- 0x00002000,
- 0x00020000,
- 0x02008000,
- 0x02000000,
- 0x00000008,
- 0x00002008,
- 0x00001000,
-};
-
-const unsigned long iocsr_scan_chain1_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
- 0x000C0300,
- 0x10040000,
- 0x100000C0,
- 0x00000040,
- 0x00010040,
- 0x00008000,
- 0x00080000,
- 0x18060000,
- 0x18000000,
- 0x00000060,
- 0x00018060,
- 0x00004000,
- 0x00010040,
- 0x10000000,
- 0x04000000,
- 0x00000010,
- 0x00004010,
- 0x00002000,
- 0x06008020,
- 0x02008000,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x00001000,
- 0x00004010,
- 0x01004000,
- 0x01000000,
- 0x00003004,
- 0x00001004,
- 0x00000800,
- 0x00000000,
- 0x00000000,
- 0x00800000,
- 0x00000002,
- 0x00002000,
- 0x00000400,
- 0x00000000,
- 0x00401000,
- 0x00000003,
- 0x00000000,
- 0x00000000,
- 0x00000200,
- 0x00600802,
- 0x00000000,
- 0x80200000,
- 0x80000600,
- 0x00000200,
- 0x00000100,
- 0x00300401,
- 0xC0100400,
- 0x40100000,
- 0x40000300,
- 0x000C0100,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
- 0x80040100,
- 0x00000000,
- 0x0FF00000,
- 0x00000000,
- 0x0C010040,
- 0x00008000,
- 0x18020080,
- 0x00000000,
- 0x08000000,
- 0x00040020,
- 0x06018060,
- 0x00004000,
- 0x0C010040,
- 0x04010000,
- 0x00000030,
- 0x00000000,
- 0x03004010,
- 0x00002000,
- 0x06008020,
- 0x02008000,
- 0x02000018,
- 0x00006008,
- 0x01802008,
- 0x00001000,
- 0x03004010,
- 0x01004000,
- 0x0100000C,
- 0x00003004,
- 0x00C01004,
- 0x00000800,
-};
-
-const unsigned long iocsr_scan_chain3_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
- 0x2C420D80,
- 0x082000FF,
- 0x0A804001,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0xE4400000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000070,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00A28,
- 0xA20D0000,
- 0x24906808,
- 0x00A28340,
- 0xD000001A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000FF0,
- 0x72200000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x6A1C0000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x1A870001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000070,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00040,
- 0xA20D0002,
- 0x24906808,
- 0x00A28340,
- 0xD005141A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x000001C1,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x04510680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00600391,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x8341D348,
- 0x821A0124,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x40120800,
- 0x00000070,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC255F80,
- 0xF1C71C71,
- 0x14F1690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0x00489800,
- 0x001A1A1A,
- 0x085506A0,
- 0x0000E1D4,
- 0x045506A0,
- 0x0000E1D4,
- 0x085506A0,
- 0x8000E1D4,
- 0x00000200,
- 0x00000004,
- 0x04000000,
- 0x00000009,
- 0x00002410,
- 0x00000040,
- 0x41000000,
- 0x00002082,
- 0x00000350,
- 0x000000DA,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x022A8350,
- 0x000070EA,
- 0x86000000,
- 0x08000004,
- 0x00000000,
- 0x00482000,
- 0x21800000,
- 0x00101061,
- 0x021541A8,
- 0x00003875,
- 0x011541A8,
- 0x00003875,
- 0x021541A8,
- 0x20003875,
- 0x00000080,
- 0x00000001,
- 0x41000000,
- 0x00000002,
- 0x00FF0904,
- 0x00000000,
- 0x90400000,
- 0x00000820,
- 0xC0000001,
- 0x38D612AF,
- 0x86F8E38E,
- 0x0A0A78B4,
- 0x000D020A,
- 0x00006800,
- 0x028A4320,
- 0xEC2CB23D,
- 0x8F5D1451,
- 0xA47A88A2,
- 0x0001A0E9,
- 0x00410D00,
- 0x40000068,
- 0x3D000003,
- 0x51EC2CB2,
- 0xA28F5D14,
- 0xE9A47A88,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000540,
- 0x000003A8,
- 0x08AA0D40,
- 0x8001C3A8,
- 0x0000007F,
- 0x00000000,
- 0x00004060,
- 0xE1208000,
- 0x0000001F,
- 0x00004100,
-};
-#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
-
-#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
-const unsigned long iocsr_scan_chain0_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000060,
- 0x00018060,
- 0x06018060,
- 0x00004000,
- 0x0C0300C0,
- 0x0C030000,
- 0x00000030,
- 0x00000000,
- 0x00000000,
- 0x00002000,
- 0x00000000,
- 0x00000000,
- 0x06000000,
- 0x00006018,
- 0x01806018,
- 0x00001000,
- 0x0000C030,
- 0x04000000,
- 0x03000000,
- 0x0000300C,
- 0x00000000,
- 0x00000800,
- 0x00006018,
- 0x01806000,
- 0x01800000,
- 0x00000006,
- 0x00001806,
- 0x00000400,
- 0x0000300C,
- 0x00C03000,
- 0x00C00000,
- 0x00000003,
- 0x00000C03,
- 0x00000200,
-};
-
-const unsigned long iocsr_scan_chain1_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
- 0x00100000,
- 0x300C0000,
- 0x300000C0,
- 0x000000C0,
- 0x000300C0,
- 0x00008000,
- 0x00060180,
- 0x18060000,
- 0x18000000,
- 0x00000060,
- 0x00018060,
- 0x00004000,
- 0x000300C0,
- 0x10000000,
- 0x0C000000,
- 0x00000030,
- 0x0000C030,
- 0x00002000,
- 0x06018060,
- 0x06018000,
- 0x01FE0000,
- 0xF8000000,
- 0x00000007,
- 0x00001000,
- 0x0000C030,
- 0x0300C000,
- 0x03000000,
- 0x0000300C,
- 0x0000300C,
- 0x00000800,
- 0x00006018,
- 0x01806000,
- 0x01800000,
- 0x00000006,
- 0x00002000,
- 0x00000400,
- 0x0000300C,
- 0x01000000,
- 0x00000000,
- 0x00000004,
- 0x00000C03,
- 0x00000200,
- 0x00001806,
- 0x00800000,
- 0x00000000,
- 0x00000002,
- 0x00000800,
- 0x00000100,
- 0x00001000,
- 0x00400000,
- 0xC0300000,
- 0x00000000,
- 0x00000400,
- 0x00000080,
-};
-
-const unsigned long iocsr_scan_chain2_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
- 0x00100000,
- 0x40000000,
- 0x00000000,
- 0x00000100,
- 0x00040000,
- 0x00008000,
- 0x18060180,
- 0x20000000,
- 0x00000000,
- 0x00000080,
- 0x00020000,
- 0x00004000,
- 0x00040000,
- 0x10000000,
- 0x00000000,
- 0x00000000,
- 0x00010000,
- 0x00002000,
- 0x10038060,
- 0x00000000,
- 0x00000000,
- 0x00000020,
- 0x01806018,
- 0x00001000,
- 0x00010000,
- 0x04000000,
- 0x03000000,
- 0x0000801C,
- 0x00004000,
- 0x00000800,
- 0x01806018,
- 0x02000000,
- 0x00000000,
- 0x00000008,
- 0x00002000,
- 0x00000400,
- 0x00C0300C,
- 0x00C03000,
- 0x00C00003,
- 0x00000C03,
- 0x00300C03,
- 0x00000200,
- 0x00601806,
- 0x80601800,
- 0x80600001,
- 0x80000601,
- 0x00180601,
- 0x00000100,
-};
-
-const unsigned long iocsr_scan_chain3_table[((
- CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
- 0x2C820D80,
- 0x082000FF,
- 0x0A804001,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000000,
- 0x00000021,
- 0x82000004,
- 0x05400000,
- 0x03C80000,
- 0x04010000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0xE4400000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x00000001,
- 0x40000002,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000050,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00A28,
- 0xA20D0000,
- 0x24906808,
- 0x00A28340,
- 0xD000001A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x0A800001,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x0A800000,
- 0x07900000,
- 0x08020000,
- 0x00100000,
- 0xC8800000,
- 0x00003001,
- 0x00C00722,
- 0x00000FF0,
- 0x72200000,
- 0x80000C00,
- 0x05400000,
- 0x02480000,
- 0x04000000,
- 0x00080000,
- 0x05400000,
- 0x03C80000,
- 0x05400000,
- 0x03C80000,
- 0x6A1C0000,
- 0x00001800,
- 0x00600391,
- 0x800E4400,
- 0x1A870001,
- 0x40000600,
- 0x02A00040,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x02A00000,
- 0x01E40000,
- 0x72200000,
- 0x80000C00,
- 0x003001C8,
- 0xC0072200,
- 0x1C880000,
- 0x20000300,
- 0x00040000,
- 0x50670000,
- 0x00000050,
- 0x24590000,
- 0x00001000,
- 0xA0000034,
- 0x0D000001,
- 0x906808A2,
- 0xA2834024,
- 0x05141A00,
- 0x808A20D0,
- 0x34024906,
- 0x01A00040,
- 0xA20D0002,
- 0x24906808,
- 0x00A28340,
- 0xD005141A,
- 0x06808A20,
- 0x10040000,
- 0x00200000,
- 0x10040000,
- 0x00200000,
- 0x15000000,
- 0x0F200000,
- 0x15000000,
- 0x0F200000,
- 0x01FE0000,
- 0x00000000,
- 0x01800E44,
- 0x00391000,
- 0x007F8006,
- 0x00000000,
- 0x99300001,
- 0x34343400,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x01000000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x04510680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x00003FC2,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00015000,
- 0x0000F200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00600391,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x8341D348,
- 0x821A0124,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x0002A000,
- 0x0001E400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0xC880090C,
- 0x00003001,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00002000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F3690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0xAA0D4000,
- 0x01C3A810,
- 0xAA0D4000,
- 0x01C3A808,
- 0xAA0D4000,
- 0x01C3A810,
- 0x00040100,
- 0x00000800,
- 0x00000000,
- 0x00001208,
- 0x00482000,
- 0x00008000,
- 0x00000000,
- 0x00410482,
- 0x0006A000,
- 0x0001B400,
- 0x00020000,
- 0x00000400,
- 0x00020080,
- 0x00000400,
- 0x5506A000,
- 0x00E1D404,
- 0x00000000,
- 0x0000090C,
- 0x00000010,
- 0x90400000,
- 0x00000000,
- 0x2020C243,
- 0x2A835000,
- 0x0070EA04,
- 0x2A835000,
- 0x0070EA02,
- 0x2A835000,
- 0x0070EA04,
- 0x00010040,
- 0x00000200,
- 0x00000000,
- 0x00000482,
- 0x00120800,
- 0x00400000,
- 0x80000000,
- 0x00104120,
- 0x00000200,
- 0xAC055F80,
- 0xFFFFFFFF,
- 0x14F1690D,
- 0x1A041414,
- 0x00D00000,
- 0x14864000,
- 0x59647A05,
- 0xBA28A3D8,
- 0xF511451E,
- 0x0341D348,
- 0x821A0000,
- 0x0000D000,
- 0x00000680,
- 0xD859647A,
- 0x1EBA28A3,
- 0x48F51145,
- 0x000341D3,
- 0x00080200,
- 0x00001000,
- 0x00080200,
- 0x00001000,
- 0x000A8000,
- 0x00075000,
- 0x541A8000,
- 0x03875011,
- 0x10000000,
- 0x00000000,
- 0x0080C000,
- 0x41000000,
- 0x04000002,
- 0x00820000,
- 0x00481800,
- 0x001A1A1A,
- 0x085506A0,
- 0x0000E1D4,
- 0x045506A0,
- 0x0000E1D4,
- 0x085506A0,
- 0x8000E1D4,
- 0x00000200,
- 0x00000004,
- 0x04000000,
- 0x00000009,
- 0x00002410,
- 0x00000040,
- 0x41000000,
- 0x00002082,
- 0x00000350,
- 0x000000DA,
- 0x00000100,
- 0x40000002,
- 0x00000100,
- 0x00000002,
- 0x022A8350,
- 0x000070EA,
- 0x86000000,
- 0x08000004,
- 0x00000000,
- 0x00482000,
- 0x21800000,
- 0x00101061,
- 0x021541A8,
- 0x00003875,
- 0x011541A8,
- 0x00003875,
- 0x021541A8,
- 0x20003875,
- 0x00000080,
- 0x00000001,
- 0x41000000,
- 0x00000002,
- 0x00FF0904,
- 0x00000000,
- 0x90400000,
- 0x00000820,
- 0xC0000001,
- 0xFFD602AF,
- 0x86FFFFFF,
- 0x0A0A78B4,
- 0x000D020A,
- 0x00006800,
- 0x028A4320,
- 0xEC2CB23D,
- 0x8F5D1451,
- 0xA47A88A2,
- 0x0001A0E9,
- 0x00410D00,
- 0x40000068,
- 0x3D000003,
- 0x51EC2CB2,
- 0xA28F5D14,
- 0xE9A47A88,
- 0x000001A0,
- 0x00000401,
- 0x00000008,
- 0x00000401,
- 0x00000008,
- 0x00000540,
- 0x000003A8,
- 0x08AA0D40,
- 0x8001C3A8,
- 0x0000007F,
- 0x00000000,
- 0x00004060,
- 0xE1208000,
- 0x0000001F,
- 0x00004100,
-};
-#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* This file is generated by Preloader Generator */
-
-#ifndef _PRELOADER_IOCSR_CONFIG_H_
-#define _PRELOADER_IOCSR_CONFIG_H_
-
-#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
-#endif
-
-#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337)
-#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
-#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528)
-#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
-#endif
-
-#endif /*_PRELOADER_IOCSR_CONFIG_H_*/
+++ /dev/null
-/* This file is generated by Preloader Generator */
-
-#include "pinmux_config.h"
-
-#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5
-/* pin mux configuration data */
-unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
- 3, /* EMACIO0 */
- 3, /* EMACIO1 */
- 3, /* EMACIO2 */
- 3, /* EMACIO3 */
- 3, /* EMACIO4 */
- 3, /* EMACIO5 */
- 3, /* EMACIO6 */
- 3, /* EMACIO7 */
- 3, /* EMACIO8 */
- 3, /* EMACIO9 */
- 3, /* EMACIO10 */
- 3, /* EMACIO11 */
- 3, /* EMACIO12 */
- 3, /* EMACIO13 */
- 0, /* EMACIO14 */
- 0, /* EMACIO15 */
- 0, /* EMACIO16 */
- 0, /* EMACIO17 */
- 0, /* EMACIO18 */
- 0, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 3, /* FLASHIO4 */
- 3, /* FLASHIO5 */
- 3, /* FLASHIO6 */
- 3, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 0, /* GENERALIO0 */
- 1, /* GENERALIO1 */
- 1, /* GENERALIO2 */
- 0, /* GENERALIO3 */
- 0, /* GENERALIO4 */
- 1, /* GENERALIO5 */
- 1, /* GENERALIO6 */
- 1, /* GENERALIO7 */
- 1, /* GENERALIO8 */
- 0, /* GENERALIO9 */
- 0, /* GENERALIO10 */
- 0, /* GENERALIO11 */
- 0, /* GENERALIO12 */
- 2, /* GENERALIO13 */
- 2, /* GENERALIO14 */
- 0, /* GENERALIO15 */
- 0, /* GENERALIO16 */
- 2, /* GENERALIO17 */
- 2, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 0, /* GENERALIO23 */
- 0, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 1, /* MIXED1IO1 */
- 1, /* MIXED1IO2 */
- 1, /* MIXED1IO3 */
- 1, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 1, /* MIXED1IO8 */
- 1, /* MIXED1IO9 */
- 1, /* MIXED1IO10 */
- 1, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 1, /* MIXED1IO15 */
- 1, /* MIXED1IO16 */
- 1, /* MIXED1IO17 */
- 1, /* MIXED1IO18 */
- 0, /* MIXED1IO19 */
- 0, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 0, /* MIXED2IO0 */
- 0, /* MIXED2IO1 */
- 0, /* MIXED2IO2 */
- 0, /* MIXED2IO3 */
- 0, /* MIXED2IO4 */
- 0, /* MIXED2IO5 */
- 0, /* MIXED2IO6 */
- 0, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 1, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 1, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 1, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 1, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 1, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 1, /* GPLMUX40 */
- 1, /* GPLMUX41 */
- 1, /* GPLMUX42 */
- 1, /* GPLMUX43 */
- 1, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 1, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 1, /* GPLMUX53 */
- 1, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 1, /* GPLMUX57 */
- 1, /* GPLMUX58 */
- 1, /* GPLMUX59 */
- 1, /* GPLMUX60 */
- 1, /* GPLMUX61 */
- 1, /* GPLMUX62 */
- 1, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 1, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 0, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */
-
-#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5
-/* pin mux configuration data */
-unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
- 0, /* EMACIO0 */
- 2, /* EMACIO1 */
- 2, /* EMACIO2 */
- 2, /* EMACIO3 */
- 2, /* EMACIO4 */
- 2, /* EMACIO5 */
- 2, /* EMACIO6 */
- 2, /* EMACIO7 */
- 2, /* EMACIO8 */
- 0, /* EMACIO9 */
- 2, /* EMACIO10 */
- 2, /* EMACIO11 */
- 2, /* EMACIO12 */
- 2, /* EMACIO13 */
- 3, /* EMACIO14 */
- 3, /* EMACIO15 */
- 3, /* EMACIO16 */
- 3, /* EMACIO17 */
- 3, /* EMACIO18 */
- 3, /* EMACIO19 */
- 3, /* FLASHIO0 */
- 0, /* FLASHIO1 */
- 3, /* FLASHIO2 */
- 3, /* FLASHIO3 */
- 0, /* FLASHIO4 */
- 0, /* FLASHIO5 */
- 0, /* FLASHIO6 */
- 0, /* FLASHIO7 */
- 0, /* FLASHIO8 */
- 3, /* FLASHIO9 */
- 3, /* FLASHIO10 */
- 3, /* FLASHIO11 */
- 3, /* GENERALIO0 */
- 3, /* GENERALIO1 */
- 3, /* GENERALIO2 */
- 3, /* GENERALIO3 */
- 3, /* GENERALIO4 */
- 3, /* GENERALIO5 */
- 3, /* GENERALIO6 */
- 3, /* GENERALIO7 */
- 3, /* GENERALIO8 */
- 0, /* GENERALIO9 */
- 0, /* GENERALIO10 */
- 0, /* GENERALIO11 */
- 0, /* GENERALIO12 */
- 0, /* GENERALIO13 */
- 0, /* GENERALIO14 */
- 3, /* GENERALIO15 */
- 3, /* GENERALIO16 */
- 2, /* GENERALIO17 */
- 2, /* GENERALIO18 */
- 0, /* GENERALIO19 */
- 0, /* GENERALIO20 */
- 0, /* GENERALIO21 */
- 0, /* GENERALIO22 */
- 3, /* GENERALIO23 */
- 3, /* GENERALIO24 */
- 0, /* GENERALIO25 */
- 0, /* GENERALIO26 */
- 0, /* GENERALIO27 */
- 0, /* GENERALIO28 */
- 0, /* GENERALIO29 */
- 0, /* GENERALIO30 */
- 0, /* GENERALIO31 */
- 0, /* MIXED1IO0 */
- 0, /* MIXED1IO1 */
- 0, /* MIXED1IO2 */
- 0, /* MIXED1IO3 */
- 0, /* MIXED1IO4 */
- 0, /* MIXED1IO5 */
- 0, /* MIXED1IO6 */
- 0, /* MIXED1IO7 */
- 0, /* MIXED1IO8 */
- 0, /* MIXED1IO9 */
- 0, /* MIXED1IO10 */
- 0, /* MIXED1IO11 */
- 0, /* MIXED1IO12 */
- 0, /* MIXED1IO13 */
- 0, /* MIXED1IO14 */
- 3, /* MIXED1IO15 */
- 3, /* MIXED1IO16 */
- 3, /* MIXED1IO17 */
- 3, /* MIXED1IO18 */
- 3, /* MIXED1IO19 */
- 3, /* MIXED1IO20 */
- 0, /* MIXED1IO21 */
- 3, /* MIXED2IO0 */
- 3, /* MIXED2IO1 */
- 3, /* MIXED2IO2 */
- 3, /* MIXED2IO3 */
- 3, /* MIXED2IO4 */
- 3, /* MIXED2IO5 */
- 3, /* MIXED2IO6 */
- 3, /* MIXED2IO7 */
- 0, /* GPLINMUX48 */
- 0, /* GPLINMUX49 */
- 0, /* GPLINMUX50 */
- 0, /* GPLINMUX51 */
- 0, /* GPLINMUX52 */
- 0, /* GPLINMUX53 */
- 0, /* GPLINMUX54 */
- 0, /* GPLINMUX55 */
- 0, /* GPLINMUX56 */
- 0, /* GPLINMUX57 */
- 0, /* GPLINMUX58 */
- 0, /* GPLINMUX59 */
- 0, /* GPLINMUX60 */
- 0, /* GPLINMUX61 */
- 0, /* GPLINMUX62 */
- 0, /* GPLINMUX63 */
- 0, /* GPLINMUX64 */
- 0, /* GPLINMUX65 */
- 0, /* GPLINMUX66 */
- 0, /* GPLINMUX67 */
- 0, /* GPLINMUX68 */
- 0, /* GPLINMUX69 */
- 0, /* GPLINMUX70 */
- 1, /* GPLMUX0 */
- 1, /* GPLMUX1 */
- 1, /* GPLMUX2 */
- 1, /* GPLMUX3 */
- 1, /* GPLMUX4 */
- 1, /* GPLMUX5 */
- 1, /* GPLMUX6 */
- 1, /* GPLMUX7 */
- 1, /* GPLMUX8 */
- 1, /* GPLMUX9 */
- 1, /* GPLMUX10 */
- 1, /* GPLMUX11 */
- 1, /* GPLMUX12 */
- 1, /* GPLMUX13 */
- 1, /* GPLMUX14 */
- 1, /* GPLMUX15 */
- 1, /* GPLMUX16 */
- 1, /* GPLMUX17 */
- 1, /* GPLMUX18 */
- 1, /* GPLMUX19 */
- 1, /* GPLMUX20 */
- 1, /* GPLMUX21 */
- 1, /* GPLMUX22 */
- 1, /* GPLMUX23 */
- 1, /* GPLMUX24 */
- 1, /* GPLMUX25 */
- 1, /* GPLMUX26 */
- 1, /* GPLMUX27 */
- 1, /* GPLMUX28 */
- 1, /* GPLMUX29 */
- 1, /* GPLMUX30 */
- 1, /* GPLMUX31 */
- 1, /* GPLMUX32 */
- 1, /* GPLMUX33 */
- 1, /* GPLMUX34 */
- 1, /* GPLMUX35 */
- 1, /* GPLMUX36 */
- 1, /* GPLMUX37 */
- 1, /* GPLMUX38 */
- 1, /* GPLMUX39 */
- 1, /* GPLMUX40 */
- 1, /* GPLMUX41 */
- 1, /* GPLMUX42 */
- 1, /* GPLMUX43 */
- 1, /* GPLMUX44 */
- 1, /* GPLMUX45 */
- 1, /* GPLMUX46 */
- 1, /* GPLMUX47 */
- 1, /* GPLMUX48 */
- 1, /* GPLMUX49 */
- 1, /* GPLMUX50 */
- 1, /* GPLMUX51 */
- 1, /* GPLMUX52 */
- 1, /* GPLMUX53 */
- 1, /* GPLMUX54 */
- 1, /* GPLMUX55 */
- 1, /* GPLMUX56 */
- 1, /* GPLMUX57 */
- 1, /* GPLMUX58 */
- 1, /* GPLMUX59 */
- 1, /* GPLMUX60 */
- 1, /* GPLMUX61 */
- 1, /* GPLMUX62 */
- 1, /* GPLMUX63 */
- 1, /* GPLMUX64 */
- 1, /* GPLMUX65 */
- 1, /* GPLMUX66 */
- 1, /* GPLMUX67 */
- 1, /* GPLMUX68 */
- 1, /* GPLMUX69 */
- 1, /* GPLMUX70 */
- 0, /* NANDUSEFPGA */
- 0, /* UART0USEFPGA */
- 0, /* RGMII1USEFPGA */
- 0, /* SPIS0USEFPGA */
- 0, /* CAN0USEFPGA */
- 0, /* I2C0USEFPGA */
- 0, /* SDMMCUSEFPGA */
- 0, /* QSPIUSEFPGA */
- 0, /* SPIS1USEFPGA */
- 0, /* RGMII0USEFPGA */
- 0, /* UART1USEFPGA */
- 0, /* CAN1USEFPGA */
- 0, /* USB1USEFPGA */
- 0, /* I2C3USEFPGA */
- 0, /* I2C2USEFPGA */
- 0, /* I2C1USEFPGA */
- 0, /* SPIM1USEFPGA */
- 0, /* USB0USEFPGA */
- 0 /* SPIM0USEFPGA */
-};
-#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */
+++ /dev/null
-/* This file is generated by Preloader Generator */
-
-#ifndef _PRELOADER_PINMUX_CONFIG_H_
-#define _PRELOADER_PINMUX_CONFIG_H_
-
-/*
- * State of enabling for which IP connected out through the muxing.
- * Value 1 mean the IP connection is muxed out
- */
-#define CONFIG_HPS_EMAC0 (1)
-#define CONFIG_HPS_EMAC1 (0)
-#define CONFIG_HPS_USB0 (0)
-#define CONFIG_HPS_USB1 (1)
-#define CONFIG_HPS_NAND (0)
-#define CONFIG_HPS_SDMMC (1)
-#define CONFIG_HPS_QSPI (0)
-#define CONFIG_HPS_UART0 (1)
-#define CONFIG_HPS_UART1 (0)
-#define CONFIG_HPS_TRACE (0)
-#define CONFIG_HPS_I2C0 (1)
-#define CONFIG_HPS_I2C1 (0)
-#define CONFIG_HPS_I2C2 (0)
-#define CONFIG_HPS_I2C3 (0)
-#define CONFIG_HPS_SPIM0 (0)
-#define CONFIG_HPS_SPIM1 (0)
-#define CONFIG_HPS_SPIS0 (0)
-#define CONFIG_HPS_SPIS1 (0)
-#define CONFIG_HPS_CAN0 (1)
-#define CONFIG_HPS_CAN1 (0)
-
-/* IP attribute value (which affected by pin muxing configuration) */
-#define CONFIG_HPS_SDMMC_BUSWIDTH (8)
-
-/* 1 if the pins are connected out */
-#define CONFIG_HPS_QSPI_CS0 (0)
-#define CONFIG_HPS_QSPI_CS1 (0)
-#define CONFIG_HPS_QSPI_CS2 (0)
-#define CONFIG_HPS_QSPI_CS3 (0)
-
-/* UART */
-/* 1 means the pin is mux out or available */
-#define CONFIG_HPS_UART0_TX (1)
-#define CONFIG_HPS_UART0_RX (1)
-#define CONFIG_HPS_UART0_CTS (0)
-#define CONFIG_HPS_UART0_RTS (0)
-#define CONFIG_HPS_UART1_TX (0)
-#define CONFIG_HPS_UART1_RX (0)
-#define CONFIG_HPS_UART1_CTS (0)
-#define CONFIG_HPS_UART1_RTS (0)
-
-/* Pin mux data */
-#define CONFIG_HPS_PINMUX_NUM (207)
-
-#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2014. All rights reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* This file is generated by Preloader Generator */
-
-#ifndef _PRELOADER_PLL_CONFIG_H_
-#define _PRELOADER_PLL_CONFIG_H_
-
-/* PLL configuration data */
-/* Main PLL */
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
-#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
-#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
-#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
-#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
-#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
-#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
-#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
-/*
- * To tell where is the clock source:
- * 0 = MAINPLL
- * 1 = PERIPHPLL
- */
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
-#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
-
-/* Peripheral PLL */
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
-#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
-#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
-#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
-#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
-#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
-#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
-#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
-#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
-#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
-#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
-/*
- * To tell where is the clock source:
- * 0 = F2S_PERIPH_REF_CLK
- * 1 = MAIN_CLK
- * 2 = PERIPH_CLK
- */
-#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
-#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
-#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
-
-/* SDRAM PLL */
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
-#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
-
-/*
- * To tell where is the VCOs source:
- * 0 = EOSC1
- * 1 = EOSC2
- * 2 = F2S
- */
-#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
-#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
-#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
-#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
-
-/* Info for driver */
-#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
-#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
-#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
-#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
-#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
-#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
-#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
-#define CONFIG_HPS_CLK_NAND_HZ (50000000)
-#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
-#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
-#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
-#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
-#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
-#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
-#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
-#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
-
-#endif /* _PRELOADER_PLL_CONFIG_H_ */
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* This file is autogenerated from tools provided by Altera.*/
-#ifndef __SDRAM_CONFIG_H
-#define __SDRAM_CONFIG_H
-
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#ifdef CONFIG_SOCFPGA_ARRIA5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
-#else
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
-0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-
-#endif /*#ifndef__SDRAM_CONFIG_H*/
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-
-#define RW_MGR_READ_B2B_WAIT2 0x6A
-#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
-#define RW_MGR_REFRESH_ALL 0x14
-#define RW_MGR_ZQCL 0x06
-#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
-#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
-#define RW_MGR_ACTIVATE_0_AND_1 0x0D
-#define RW_MGR_MRS2_MIRR 0x0A
-#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
-#define RW_MGR_ACTIVATE_1 0x0F
-#define RW_MGR_MRS2 0x04
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
-#define RW_MGR_MRS1 0x03
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_IDLE_LOOP1 0x7A
-#else
-#define RW_MGR_IDLE_LOOP1 0x7C
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
-#define RW_MGR_MRS3 0x05
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_IDLE_LOOP2 0x79
-#else
-#define RW_MGR_IDLE_LOOP2 0x7B
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
-#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
-#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_RDIMM_CMD 0x78
-#else
-#define RW_MGR_RDIMM_CMD 0x7A
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
-#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
-#define RW_MGR_GUARANTEED_READ_CONT 0x53
-#define RW_MGR_MRS3_MIRR 0x0B
-#define RW_MGR_IDLE 0x00
-#define RW_MGR_READ_B2B 0x58
-#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
-#define RW_MGR_GUARANTEED_WRITE 0x17
-#define RW_MGR_PRECHARGE_ALL 0x12
-#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define RW_MGR_SGLE_READ 0x7C
-#else
-#define RW_MGR_SGLE_READ 0x7E
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define RW_MGR_MRS0_USER_MIRR 0x0C
-#define RW_MGR_RETURN 0x01
-#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
-#define RW_MGR_MRS0_USER 0x07
-#define RW_MGR_GUARANTEED_READ 0x4B
-#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
-#define RW_MGR_INIT_RESET_1_CKE_0 0x73
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
-#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
-#define RW_MGR_MRS0_DLL_RESET 0x02
-#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
-#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
-#define RW_MGR_CLEAR_DQS_ENABLE 0x48
-#define RW_MGR_MRS1_MIRR 0x09
-#define RW_MGR_READ_B2B_WAIT1 0x60
-#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
-#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
-#define RW_MGR_CONTENT_ZQCL 0x008380
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
-#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
-#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
-#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
-#define RW_MGR_CONTENT_MRS2 0x008280
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
-#define RW_MGR_CONTENT_MRS1 0x008200
-#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
-#define RW_MGR_CONTENT_MRS3 0x008300
-#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
-#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
-#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
-#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
-#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
-#define RW_MGR_CONTENT_IDLE 0x080000
-#define RW_MGR_CONTENT_READ_B2B 0x040E88
-#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
-#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
-#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
-#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
-#define RW_MGR_CONTENT_SGLE_READ 0x040F08
-#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
-#define RW_MGR_CONTENT_RETURN 0x080680
-#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
-#define RW_MGR_CONTENT_MRS0_USER 0x008100
-#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
-#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
-#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
-#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
-#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
-#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
-#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
-#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
-#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
-
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-const uint32_t ac_rom_init[] = {
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
- 0x20700000,
- 0x20780000,
- 0x10080831,
- 0x10080930,
- 0x10090004,
- 0x100a0008,
- 0x100b0000,
- 0x10380400,
- 0x10080849,
- 0x100808c8,
- 0x100a0004,
- 0x10090010,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-#else
- 0x20700000,
- 0x20780000,
- 0x10080431,
- 0x10080530,
- 0x10090004,
- 0x100a0008,
- 0x100b0000,
- 0x10380400,
- 0x10080449,
- 0x100804c8,
- 0x100a0004,
- 0x10090010,
- 0x100b0000,
- 0x30780000,
- 0x38780000,
- 0x30780000,
- 0x10680000,
- 0x106b0000,
- 0x10280400,
- 0x10480000,
- 0x1c980000,
- 0x1c9b0000,
- 0x1c980008,
- 0x1c9b0008,
- 0x38f80000,
- 0x3cf80000,
- 0x38780000,
- 0x18180000,
- 0x18980000,
- 0x13580000,
- 0x135b0000,
- 0x13580008,
- 0x135b0008,
- 0x33780000,
- 0x10580008,
- 0x10780000
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-};
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-const u32 inst_rom_init[] = {
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x8000,
- 0xa000,
- 0xc000,
- 0x80000,
- 0x80,
- 0x8080,
- 0xa080,
- 0xc080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-#else
-const u32 inst_rom_init[] = {
- 0x80000,
- 0x80680,
- 0x8180,
- 0x8200,
- 0x8280,
- 0x8300,
- 0x8380,
- 0x8100,
- 0x8480,
- 0x8500,
- 0x8580,
- 0x8600,
- 0x8400,
- 0x800,
- 0x8680,
- 0x880,
- 0xa680,
- 0x80680,
- 0x900,
- 0x80680,
- 0x980,
- 0x8680,
- 0x80680,
- 0xb68,
- 0xcce8,
- 0xae8,
- 0x8ce8,
- 0xb88,
- 0xec88,
- 0xa08,
- 0xac88,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0x20ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x60e80,
- 0x61080,
- 0x61080,
- 0x61080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0xce00,
- 0xcd80,
- 0xe700,
- 0xc00,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0x30ce0,
- 0xd00,
- 0x680,
- 0x680,
- 0x680,
- 0x680,
- 0x70e80,
- 0x71080,
- 0x71080,
- 0x71080,
- 0xa680,
- 0x8680,
- 0x80680,
- 0x1158,
- 0x6d8,
- 0x80680,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0x87e8,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x1168,
- 0x7e8,
- 0x7e8,
- 0xa7e8,
- 0x80680,
- 0x40e88,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x40f68,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0xa680,
- 0x40fe8,
- 0x410e8,
- 0x410e8,
- 0x410e8,
- 0x41008,
- 0x41088,
- 0x41088,
- 0x41088,
- 0x1100,
- 0xc680,
- 0x8680,
- 0xe680,
- 0x80680,
- 0x0,
- 0x0,
- 0xa000,
- 0x8000,
- 0x80000,
- 0x80,
- 0x80,
- 0x80,
- 0x80,
- 0xa080,
- 0x8080,
- 0x80080,
- 0x9180,
- 0x8680,
- 0xa680,
- 0x80680,
- 0x40f08,
- 0x80680
-};
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
+++ /dev/null
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _SEQUENCER_DEFINES_H_
-#define _SEQUENCER_DEFINES_H_
-
-#define AC_ROM_MR1_MIRR 0000000000100
-#define AC_ROM_MR1_OCD_ENABLE
-#define AC_ROM_MR2_MIRR 0000000010000
-#define AC_ROM_MR3_MIRR 0000000000000
-#define AC_ROM_MR0_CALIB
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
-#define AC_ROM_MR0_DLL_RESET 0100100110000
-#define AC_ROM_MR0_MIRR 0100001001001
-#define AC_ROM_MR0 0100000110001
-#else
-#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
-#define AC_ROM_MR0_DLL_RESET 0010100110000
-#define AC_ROM_MR0_MIRR 0010001001001
-#define AC_ROM_MR0 0010000110001
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define AC_ROM_MR1 0000000000100
-#define AC_ROM_MR2 0000000001000
-#define AC_ROM_MR3 0000000000000
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define AFI_CLK_FREQ 534
-#else
-#define AFI_CLK_FREQ 401
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define AFI_RATE_RATIO 1
-#define AVL_CLK_FREQ 67
-#define BFM_MODE 0
-#define BURST2 0
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define CALIB_LFIFO_OFFSET 8
-#define CALIB_VFIFO_OFFSET 6
-#else
-#define CALIB_LFIFO_OFFSET 7
-#define CALIB_VFIFO_OFFSET 5
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
-#define ENABLE_SUPER_QUICK_CALIBRATION 0
-#define GUARANTEED_READ_BRINGUP_TEST 0
-#define HARD_PHY 1
-#define HARD_VFIFO 1
-#define HPS_HW 1
-#define HR_DDIO_OUT_HAS_THREE_REGS 0
-#define IO_DELAY_PER_DCHAIN_TAP 25
-#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define IO_DELAY_PER_OPA_TAP 234
-#else
-#define IO_DELAY_PER_OPA_TAP 312
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define IO_DLL_CHAIN_LENGTH 8
-#define IO_DM_OUT_RESERVE 0
-#define IO_DQDQS_OUT_PHASE_MAX 0
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define IO_DQS_EN_DELAY_MAX 15
-#define IO_DQS_EN_DELAY_OFFSET 16
-#else
-#define IO_DQS_EN_DELAY_MAX 31
-#define IO_DQS_EN_DELAY_OFFSET 0
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define IO_DQS_EN_PHASE_MAX 7
-#define IO_DQS_IN_DELAY_MAX 31
-#define IO_DQS_IN_RESERVE 4
-#define IO_DQS_OUT_RESERVE 6
-#define IO_DQ_OUT_RESERVE 0
-#define IO_IO_IN_DELAY_MAX 31
-#define IO_IO_OUT1_DELAY_MAX 31
-#define IO_IO_OUT2_DELAY_MAX 0
-#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
-#define MARGIN_VARIATION_TEST 0
-#define MAX_LATENCY_COUNT_WIDTH 5
-#define MEM_ADDR_WIDTH 13
-#define READ_VALID_FIFO_SIZE 16
-#ifdef CONFIG_SOCFPGA_ARRIA5
-/* The if..else... is not required if generated by tools */
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
-#else
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define RW_MGR_MEM_ADDRESS_MIRRORING 0
-#define RW_MGR_MEM_ADDRESS_WIDTH 15
-#define RW_MGR_MEM_BANK_WIDTH 3
-#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
-#define RW_MGR_MEM_CLK_EN_WIDTH 1
-#define RW_MGR_MEM_CONTROL_WIDTH 1
-#define RW_MGR_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_MEM_DATA_WIDTH 40
-#define RW_MGR_MEM_DQ_PER_READ_DQS 8
-#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
-#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
-#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
-#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
-#define RW_MGR_MEM_NUMBER_OF_RANKS 1
-#define RW_MGR_MEM_ODT_WIDTH 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
-#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
-#define RW_MGR_MR0_BL 1
-#define RW_MGR_MR0_CAS_LATENCY 3
-#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
-#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
-#define SKEW_CALIBRATION 0
-#define TINIT_CNTR1_VAL 32
-#define TINIT_CNTR2_VAL 32
-#define TINIT_CNTR0_VAL 132
-#define TRESET_CNTR1_VAL 99
-#define TRESET_CNTR2_VAL 10
-#define TRESET_CNTR0_VAL 132
-
-#endif /* _SEQUENCER_DEFINES_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/reset_manager.h>
-#include <asm/io.h>
-
-#include <usb.h>
-#include <usb/s3c_udc.h>
-#include <usb_mass_storage.h>
-
-#include <micrel.h>
-#include <netdev.h>
-#include <phy.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void) {}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
- return 0;
-}
-
-/*
- * PHY configuration
- */
-#ifdef CONFIG_PHY_MICREL_KSZ9021
-int board_phy_config(struct phy_device *phydev)
-{
- int ret;
- /*
- * These skew settings for the KSZ9021 ethernet phy is required for ethernet
- * to work reliably on most flavors of cyclone5 boards.
- */
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
- 0x0);
- if (ret)
- return ret;
-
- ret = ksz9021_phy_extended_write(phydev,
- MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
- 0xf0f0);
- if (ret)
- return ret;
-
- if (phydev->drv->config)
- return phydev->drv->config(phydev);
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
- .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
- .usb_gusbcfg = 0x1417,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return s3c_udc_probe(&socfpga_otg_data);
-}
-
-int g_dnl_board_usb_cable_connected(void)
-{
- return 1;
-}
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/arch/clock_manager.h>
-/*
- * Yes, dear reader, we're including a C file here, this is no mistake :-)
- */
-#include "qts/iocsr_config.c"
-
-int iocsr_get_config_table(const unsigned int chain_id,
- const unsigned long **table,
- unsigned int *table_len)
-{
- switch (chain_id) {
- case 0:
- *table = iocsr_scan_chain0_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
- break;
- case 1:
- *table = iocsr_scan_chain1_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
- break;
- case 2:
- *table = iocsr_scan_chain2_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
- break;
- case 3:
- *table = iocsr_scan_chain3_table;
- *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-/*
- * Yes, dear reader, we're including a C file here, this is no mistake.
- * But this time around, we do even more perverse hacking here to be
- * compatible with QTS headers and obtain reasonably nice results too.
- *
- * First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise
- * the pinmux_config.h inclusion in pinmux_config.c . Since we are
- * probing everything from DT, we do NOT want those macros from the
- * pinmux_config.h to ooze into our build system, anywhere, ever. So
- * we nip it at the bud.
- *
- * Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to
- * specify sized array explicitly. Instead, we want to use ARRAY_SIZE
- * to figure out the size of the array, so define this macro as an
- * empty one, so that the preprocessor optimizes things such that the
- * arrays are not sized by default.
- */
-#define _PRELOADER_PINMUX_CONFIG_H_
-#define CONFIG_HPS_PINMUX_NUM
-#include "qts/pinmux_config.c"
-
-void sysmgr_get_pinmux_table(const unsigned long **table,
- unsigned int *table_len)
-{
- *table = sys_mgr_init_table;
- *table_len = ARRAY_SIZE(sys_mgr_init_table);
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock_manager.h>
-#include "qts/pll_config.h"
-
-#define MAIN_VCO_BASE ( \
- (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
- CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
- CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define PERI_VCO_BASE ( \
- (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
- CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
- CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
- CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define SDR_VCO_BASE ( \
- (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
- CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
- CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
- CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-static const struct cm_config cm_default_cfg = {
- /* main group */
- MAIN_VCO_BASE,
- (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
- CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
- CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
- CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
- CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
- /* peripheral group */
- PERI_VCO_BASE,
- (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
- CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
- CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
- CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
- CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
- CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
- CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
- CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
- CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
- CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
- /* sdram pll group */
- SDR_VCO_BASE,
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-};
-
-const struct cm_config * const cm_get_default_config(void)
-{
- return &cm_default_cfg;
-}
-
-const unsigned int cm_get_osc_clk_hz(const int osc)
-{
- if (osc == 1)
- return CONFIG_HPS_CLK_OSC1_HZ;
- else if (osc == 2)
- return CONFIG_HPS_CLK_OSC2_HZ;
- else
- return 0;
-}
-
-const unsigned int cm_get_f2s_per_ref_clk_hz(void)
-{
- return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-}
-
-const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
-{
- return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
-}
+++ /dev/null
-/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <errno.h>
-#include <asm/arch/sdram.h>
-/* QTS output file. */
-#include "qts/sdram_config.h"
-
-#include "qts/sequencer_auto_ac_init.h"
-#include "qts/sequencer_auto_inst_init.h"
-#include "qts/sequencer_auto.h"
-#include "qts/sequencer_defines.h"
-
-static const struct socfpga_sdram_config sdram_config = {
- .ctrl_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
- SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
- SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
- SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
- SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
- SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
- SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
- SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
- SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
- SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
- .dram_timing1 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
- SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
- SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
- SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
- SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
- SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
- SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
- .dram_timing2 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
- SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
- SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
- SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
- SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
- SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
- .dram_timing3 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
- SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
- SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
- SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
- SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
- SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
- .dram_timing4 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
- SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
- SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
- .lowpwr_timing =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
- SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
- SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
- .dram_odt =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
- SDR_CTRLGRP_DRAMODT_READ_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
- SDR_CTRLGRP_DRAMODT_WRITE_LSB),
- .dram_addrw =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
- SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
- SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
- ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
- SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
- .dram_if_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
- SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
- .dram_dev_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
- SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
- .dram_intr =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
- SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
- .lowpwr_eq =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
- SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
- .static_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
- SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
- SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
- .ctrl_width =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
- SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
- .cport_width =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
- SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
- .cport_wmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
- SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
- .cport_rmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
- SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
- .rfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
- SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
- .wfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
- SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
- .cport_rdwr =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
- SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
- .port_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
- SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
- .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
- .fifo_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
- SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
- SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
- .mp_priority =
- (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
- SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
- .mp_weight0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
- .mp_weight1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
- .mp_weight2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
- .mp_weight3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
- .mp_pacing0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
- SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
- .mp_pacing1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
- .mp_pacing2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
- SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
- .mp_pacing3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
- SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
- .mp_threshold0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
- SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
- .mp_threshold1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
- SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
- .mp_threshold2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
- SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
- .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
-};
-
-static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
- .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
- .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
- .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
- .activate_1 = RW_MGR_ACTIVATE_1,
- .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
- .guaranteed_read = RW_MGR_GUARANTEED_READ,
- .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
- .guaranteed_write = RW_MGR_GUARANTEED_WRITE,
- .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
- .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
- .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
- .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
- .idle = RW_MGR_IDLE,
- .idle_loop1 = RW_MGR_IDLE_LOOP1,
- .idle_loop2 = RW_MGR_IDLE_LOOP2,
- .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
- .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
- .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
- .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
- .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
- .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
- .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
- .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
- .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
- .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
- .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
- .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
- .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
- .mrs0_user = RW_MGR_MRS0_USER,
- .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
- .mrs1 = RW_MGR_MRS1,
- .mrs1_mirr = RW_MGR_MRS1_MIRR,
- .mrs2 = RW_MGR_MRS2,
- .mrs2_mirr = RW_MGR_MRS2_MIRR,
- .mrs3 = RW_MGR_MRS3,
- .mrs3_mirr = RW_MGR_MRS3_MIRR,
- .precharge_all = RW_MGR_PRECHARGE_ALL,
- .read_b2b = RW_MGR_READ_B2B,
- .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
- .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
- .refresh_all = RW_MGR_REFRESH_ALL,
- .rreturn = RW_MGR_RETURN,
- .sgle_read = RW_MGR_SGLE_READ,
- .zqcl = RW_MGR_ZQCL,
-
- .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
- .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
- .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
- .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
- .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
- .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
- .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
- .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
- .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
- .mem_virtual_groups_per_read_dqs =
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
- .mem_virtual_groups_per_write_dqs =
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
-};
-
-struct socfpga_sdram_io_config io_config = {
- .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
- .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
- .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
- .dll_chain_length = IO_DLL_CHAIN_LENGTH,
- .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
- .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
- .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
- .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
- .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
- .dqs_in_reserve = IO_DQS_IN_RESERVE,
- .dqs_out_reserve = IO_DQS_OUT_RESERVE,
- .io_in_delay_max = IO_IO_IN_DELAY_MAX,
- .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
- .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
- .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
-};
-
-struct socfpga_sdram_misc_config misc_config = {
- .afi_rate_ratio = AFI_RATE_RATIO,
- .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
- .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
- .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
- .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
- .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
- .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
- .tinit_cntr0_val = TINIT_CNTR0_VAL,
- .tinit_cntr1_val = TINIT_CNTR1_VAL,
- .tinit_cntr2_val = TINIT_CNTR2_VAL,
- .treset_cntr0_val = TRESET_CNTR0_VAL,
- .treset_cntr1_val = TRESET_CNTR1_VAL,
- .treset_cntr2_val = TRESET_CNTR2_VAL,
-};
-
-const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
-{
- return &sdram_config;
-}
-
-void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
-{
- *init = ac_rom_init;
- *nelem = ARRAY_SIZE(ac_rom_init);
-}
-
-void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
-{
- *init = inst_rom_init;
- *nelem = ARRAY_SIZE(inst_rom_init);
-}
-
-const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
-{
- return &rw_mgr_config;
-}
-
-const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
-{
- return &io_config;
-}
-
-const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
-{
- return &misc_config;
-}
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_ARRIA5=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TARGET_SOCFPGA_CYCLONE5=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
CONFIG_SPI_FLASH=y
CONFIG_DM_ETH=y
-CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
-CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
u32 d, p, i;
u32 dtaps_per_ptap;
u32 work_bgn, work_end;
- u32 found_passing_read, found_failing_read, initial_failing_dtap;
+ u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
int ret;
debug("%s:%d %u\n", __func__, __LINE__, grp);
* (1.25 * iocfg->dll_chain_length - 2)
*/
scc_mgr_set_dqdqs_output_phase(i,
- 1.25 * iocfg->dll_chain_length - 2);
+ ((125 * iocfg->dll_chain_length) / 100) - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
particular GPIOs that they provide. The uclass interface
is defined in include/asm-generic/gpio.h.
+config DWAPB_GPIO
+ bool "DWAPB GPIO driver"
+ depends on DM && DM_GPIO
+ default n
+ help
+ Support for the Designware APB GPIO driver.
+
config LPC32XX_GPIO
bool "LPC32XX GPIO driver"
depends on DM
#
ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
endif
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
--- /dev/null
+/*
+ * (C) Copyright 2015 Marek Vasut <marex@denx.de>
+ *
+ * DesignWare APB GPIO driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_SWPORTA_DR 0x00
+#define GPIO_SWPORTA_DDR 0x04
+#define GPIO_INTEN 0x30
+#define GPIO_INTMASK 0x34
+#define GPIO_INTTYPE_LEVEL 0x38
+#define GPIO_INT_POLARITY 0x3c
+#define GPIO_INTSTATUS 0x40
+#define GPIO_PORTA_DEBOUNCE 0x48
+#define GPIO_PORTA_EOI 0x4c
+#define GPIO_EXT_PORTA 0x50
+
+struct gpio_dwapb_platdata {
+ const char *name;
+ int bank;
+ int pins;
+ fdt_addr_t base;
+};
+
+static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+
+ clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
+ return 0;
+}
+
+static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
+ int val)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+
+ setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin);
+
+ if (val)
+ setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+ else
+ clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+
+ return 0;
+}
+
+static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin));
+}
+
+
+static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+
+ if (val)
+ setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+ else
+ clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin);
+
+ return 0;
+}
+
+static const struct dm_gpio_ops gpio_dwapb_ops = {
+ .direction_input = dwapb_gpio_direction_input,
+ .direction_output = dwapb_gpio_direction_output,
+ .get_value = dwapb_gpio_get_value,
+ .set_value = dwapb_gpio_set_value,
+};
+
+static int gpio_dwapb_probe(struct udevice *dev)
+{
+ struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
+ struct gpio_dwapb_platdata *plat = dev->platdata;
+
+ if (!plat)
+ return 0;
+
+ priv->gpio_count = plat->pins;
+ priv->bank_name = plat->name;
+
+ return 0;
+}
+
+static int gpio_dwapb_bind(struct udevice *dev)
+{
+ struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
+ const void *blob = gd->fdt_blob;
+ struct udevice *subdev;
+ fdt_addr_t base;
+ int ret, node, bank = 0;
+
+ /* If this is a child device, there is nothing to do here */
+ if (plat)
+ return 0;
+
+ base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+ if (base == FDT_ADDR_T_NONE) {
+ debug("Can't get the GPIO register base address\n");
+ return -ENXIO;
+ }
+
+ for (node = fdt_first_subnode(blob, dev->of_offset);
+ node > 0;
+ node = fdt_next_subnode(blob, node)) {
+ if (!fdtdec_get_bool(blob, node, "gpio-controller"))
+ continue;
+
+ plat = NULL;
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+
+ plat->base = base;
+ plat->bank = bank;
+ plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
+ ret = fdt_get_string(blob, node, "bank-name", &plat->name);
+ if (ret)
+ goto err;
+
+ ret = device_bind(dev, dev->driver, plat->name,
+ plat, -1, &subdev);
+ if (ret)
+ goto err;
+
+ subdev->of_offset = node;
+ bank++;
+ }
+
+ return 0;
+
+err:
+ free(plat);
+ return ret;
+}
+
+static const struct udevice_id gpio_dwapb_ids[] = {
+ { .compatible = "snps,dw-apb-gpio" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_dwapb) = {
+ .name = "gpio-dwapb",
+ .id = UCLASS_GPIO,
+ .of_match = gpio_dwapb_ids,
+ .ops = &gpio_dwapb_ops,
+ .bind = gpio_dwapb_bind,
+ .probe = gpio_dwapb_probe,
+};
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#define CONFIG_CMD_USB_MASS_STORAGE
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_USB
#define CONFIG_CMD_USB_MASS_STORAGE
-
/* Memory configurations */
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
projects / oweals / u-boot.git / commitdiff