armv8/ls1043ardb: Add sd boot support
authorGong Qianyu <Qianyu.Gong@freescale.com>
Mon, 26 Oct 2015 11:47:56 +0000 (19:47 +0800)
committerYork Sun <yorksun@freescale.com>
Thu, 29 Oct 2015 17:34:02 +0000 (10:34 -0700)
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/ls1043ardb/README
board/freescale/ls1043ardb/cpld.c
board/freescale/ls1043ardb/cpld.h
board/freescale/ls1043ardb/ls1043ardb.c
board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg [new file with mode: 0644]
configs/ls1043ardb_sdcard_defconfig [new file with mode: 0644]
include/configs/ls1043a_common.h
include/configs/ls1043ardb.h

index 4f155573e8173f71ee3400c463e1c84c9277bc28..0556e73b3aeee5e947aca007e04e047e067302d6 100644 (file)
@@ -84,3 +84,4 @@ Booting Options
 ---------------
 a) NOR boot
 b) NAND boot
+c) SD boot
index f29383dc30149fb4c255025b24caa48664639d6d..78c28246a823d1ce4935e8e7757c78fb6f426c56 100644 (file)
@@ -61,6 +61,21 @@ void cpld_set_nand(void)
        CPLD_WRITE(system_rst, 1);
 }
 
+void cpld_set_sd(void)
+{
+       u16 reg = CPLD_CFG_RCW_SRC_SD;
+       u8 reg5 = (u8)(reg >> 1);
+       u8 reg6 = (u8)(reg & 1);
+
+       cpld_rev_bit(&reg5);
+
+       CPLD_WRITE(soft_mux_on, 1);
+
+       CPLD_WRITE(cfg_rcw_src1, reg5);
+       CPLD_WRITE(cfg_rcw_src2, reg6);
+
+       CPLD_WRITE(system_rst, 1);
+}
 #ifdef DEBUG
 static void cpld_dump_regs(void)
 {
@@ -109,6 +124,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
                        cpld_set_altbank();
                else if (strcmp(argv[2], "nand") == 0)
                        cpld_set_nand();
+               else if (strcmp(argv[2], "sd") == 0)
+                       cpld_set_sd();
                else
                        cpld_set_defbank();
 #ifdef DEBUG
@@ -128,6 +145,7 @@ U_BOOT_CMD(
        "reset: reset to default bank\n"
        "cpld reset altbank: reset to alternate bank\n"
        "cpld reset nand: reset to boot from NAND flash\n"
+       "cpld reset sd: reset to boot from SD card\n"
 #ifdef DEBUG
        "cpld dump - display the CPLD registers\n"
 #endif
index 5f43a8a3739fed9c61bb8499c1a9b4f78b97c392..bd59c0e5d58e19c6d24eee72f92d0e0d74862d46 100644 (file)
@@ -41,4 +41,5 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_BANK_SEL_MASK     0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
 #define CPLD_CFG_RCW_SRC_NAND  0x106
+#define CPLD_CFG_RCW_SRC_SD    0x040
 #endif
index 461a195416f65f5a45b093993097e3da278b50e8..9032ed36c852274fbf804ea7c361daa4cfefd9ae 100644 (file)
@@ -25,12 +25,17 @@ DECLARE_GLOBAL_DATA_PTR;
 int checkboard(void)
 {
        static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
        u8 cfg_rcw_src1, cfg_rcw_src2;
        u32 cfg_rcw_src;
+#endif
        u32 sd1refclk_sel;
 
        printf("Board: LS1043ARDB, boot from ");
 
+#ifdef CONFIG_SD_BOOT
+       puts("SD\n");
+#else
        cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
        cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
        cpld_rev_bit(&cfg_rcw_src1);
@@ -43,6 +48,7 @@ int checkboard(void)
                puts("NAND\n");
        else
                printf("Invalid setting of SW4\n");
+#endif
 
        printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
               CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644 (file)
index 0000000..28cd958
--- /dev/null
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
new file mode 100644 (file)
index 0000000..5fe0470
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
index 1f9af29550a25eca00591a0d96b7ed0b8a4334ed..c7705282e01eecd7448858df138b84d0a85c669a 100644 (file)
 #define CONFIG_BAUDRATE                        115200
 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT            "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR                0xf0
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS             0x500
+
+#define CONFIG_SPL_TEXT_BASE           0x10000000
+#define CONFIG_SPL_MAX_SIZE            0x1d000
+#define CONFIG_SPL_STACK               0x1001e000
+#define CONFIG_SPL_PAD_TO              0x1d000
+
+#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_TEXT_BASE + \
+                                       CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
+#define CONFIG_SPL_BSS_START_ADDR      0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE                0x80000
+#define CONFIG_SYS_MONITOR_LEN         0xa0000
+#endif
+
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PBL_PAD
index c77664029f1d3c295192b652de26384b4523674c..307d947405ce673a8fe8b29748bfbf1019000066 100644 (file)
@@ -12,7 +12,7 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#if defined(CONFIG_NAND_BOOT)
+#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE           0x82000000
 #else
 #define CONFIG_SYS_TEXT_BASE           0x60100000
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
 #endif
 
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+#endif
+
 /*
  * NOR Flash Definitions
  */
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_ENV_OFFSET              (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET              (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_SIZE                        0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x200000)