#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C1>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C1>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C3>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C3>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C4>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C4>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C6>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C6>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C7>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C7>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C9>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C9>;
reset-names = "i2c";
status = "disabled";
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03400000 0x0 0x200>;
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
- reset-names = "sdmmc";
+ reset-names = "sdhci";
clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
- clock-names = "sdmmc";
interrupts = <GIC_SPI 62 0x04>;
status = "disabled";
};
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x200>;
resets = <&bpmp TEGRA186_RESET_SDMMC4>;
- reset-names = "sdmmc";
+ reset-names = "sdhci";
clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
- clock-names = "sdmmc";
interrupts = <GIC_SPI 31 0x04>;
status = "disabled";
};
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C2>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C2>;
reset-names = "i2c";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&bpmp TEGRA186_CLK_I2C8>;
- clock-names = "i2c";
+ clock-names = "div-clk";
resets = <&bpmp TEGRA186_RESET_I2C8>;
reset-names = "i2c";
status = "disabled";
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
- nvidia,bpmp = <&bpmp>;
nvidia,bpmp-bus-id = <5>;
#address-cells = <1>;
#size-cells = <0>;
static int tegra186_bpmp_i2c_probe(struct udevice *dev)
{
struct tegra186_bpmp_i2c *priv = dev_get_priv(dev);
- int ret;
- struct fdtdec_phandle_args args;
-
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
- "nvidia,bpmp", NULL, 0, 0, &args);
- if (ret < 0) {
- debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
- __func__, ret);
- return ret;
- }
priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
"nvidia,bpmp-bus-id", U32_MAX);
error("reset_get_by_name() failed: %d\n", ret);
return ret;
}
- ret = clk_get_by_name(dev, "i2c", &i2c_bus->clk);
+ ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
if (ret) {
error("clk_get_by_name() failed: %d\n", ret);
return ret;
struct udevice dev;
int ret;
dev.of_offset = node;
- ret = reset_get_by_name(&dev, "sdmmc", &host->reset_ctl);
+ ret = reset_get_by_name(&dev, "sdhci", &host->reset_ctl);
if (ret) {
- debug("reset_get_by_index() failed: %d\n", ret);
+ debug("reset_get_by_name() failed: %d\n", ret);
return ret;
}
- ret = clk_get_by_name(&dev, "sdmmc", &host->clk);
+ ret = clk_get_by_index(&dev, 0, &host->clk);
if (ret) {
debug("clk_get_by_index() failed: %d\n", ret);
return ret;
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+
return 0;
}
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+ priv->freq);
+
return 0;
}
priv->freq = plat->frequency;
priv->periph_id = plat->periph_id;
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
+
return 0;
}