Add NAND FLASH support for AMCC Bamboo 440EP eval board
authorStefan Roese <sr@denx.de>
Thu, 11 Aug 2005 15:56:56 +0000 (17:56 +0200)
committerStefan Roese <sr@denx.de>
Thu, 11 Aug 2005 15:56:56 +0000 (17:56 +0200)
Patch by Stefan Roese, 11 Aug 2005

CHANGELOG
board/amcc/bamboo/bamboo.c
board/amcc/bamboo/flash.c
board/amcc/bamboo/init.S
cpu/ppc4xx/440gx_enet.c
include/configs/bamboo.h

index beff9875687d0503f95f1f9a1b849af0e1cecd8b..62d8a098fde30a1061ab639106749e8f4ae885ce 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Add NAND FLASH support for AMCC Bamboo 440EP eval board
+  Patch by Stefan Roese, 11 Aug 2005
+
 * Fix CompactFlash problem on HMI1001 board
 
 * Make new "mtdparts" code build with older compilers
index 0d5ab710d480b650882b0f40c74dc39c2fcd7c05..d02add5723e6f5e6d0bbca40faf9cdd6da3f0323 100644 (file)
@@ -29,6 +29,7 @@
 
 void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
+int is_nand_selected(void);
 
 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
 #if 0
@@ -132,10 +133,10 @@ gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
        EBC0_BNCR_BW_8BIT
 
 #define EBC0_BNCR_SMALL_FLASH_CS4                      \
-       EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
-       EBC0_BNCR_BS_8MB                        |       \
+       EBC0_BNCR_BAS_ENCODE(0x87F00000)        |       \
+       EBC0_BNCR_BS_1MB                        |       \
        EBC0_BNCR_BU_RW                         |       \
-       EBC0_BNCR_BW_16BIT
+       EBC0_BNCR_BW_8BIT
 
 /* Large Flash or SRAM */
 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM                  \
@@ -273,6 +274,87 @@ int board_early_init_f(void)
        return 0;
 }
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+
+/*----------------------------------------------------------------------------+
+  | nand_reset.
+  |   Reset Nand flash
+  |   This routine will abort previous cmd
+  +----------------------------------------------------------------------------*/
+int nand_reset(ulong addr)
+{
+       int wait=0, stat=0;
+
+       out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
+       out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
+
+       while ((stat != 0xc0) && (wait != 0xffff)) {
+               stat = in8(addr + NAND_DATA_REG);
+               wait++;
+       }
+
+       if (stat == 0xc0) {
+               return 0;
+       } else {
+               printf("NAND Reset timeout.\n");
+               return -1;
+       }
+}
+
+void board_nand_set_device(int cs, ulong addr)
+{
+       /* Set NandFlash Core Configuration Register */
+       out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
+
+       switch (cs) {
+       case 1:
+               /* -------
+                *  NAND0
+                * -------
+                * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
+                * Set NDF1CR - Enable External CS1 in NAND FLASH controller
+                */
+               out32(addr + NAND_CR1_REG, 0x80002222);
+               break;
+
+       case 2:
+               /* -------
+                *  NAND1
+                * -------
+                * K9K2G0B : 5 addr cyc, 2 col + 3 Row
+                * Set NDF2CR : Enable External CS2 in NAND FLASH controller
+                */
+               out32(addr + NAND_CR2_REG, 0xC0007777);
+               break;
+       }
+
+       /* Perform Reset Command */
+       if (nand_reset(addr) != 0)
+               return;
+}
+
+void nand_init(void)
+{
+       board_nand_set_device(1, CFG_NAND_ADDR);
+
+       nand_probe(CFG_NAND_ADDR);
+       if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+               print_size(nand_dev_desc[0].totlen, "\n");
+       }
+
+#if 0 /* NAND1 not supported yet */
+       board_nand_set_device(2, CFG_NAND2_ADDR);
+
+       nand_probe(CFG_NAND2_ADDR);
+       if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+               print_size(nand_dev_desc[0].totlen, "\n");
+       }
+#endif
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
+
 int checkboard(void)
 {
        sys_info_t sysinfo;
@@ -585,7 +667,11 @@ int is_powerpc440ep_pass1(void)
   +----------------------------------------------------------------------------*/
 int is_nand_selected(void)
 {
-       return FALSE; /* test-only */
+#ifdef CONFIG_BAMBOO_NAND
+       return TRUE;
+#else
+       return FALSE;
+#endif
 }
 
 /*----------------------------------------------------------------------------+
@@ -829,12 +915,8 @@ void ext_bus_cntlr_init(void)
                        /* NAND Flash */
                        ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
                        ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
-                       /*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
-                         ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
-                         ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
-                         ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
-                       ebc0_cs2_bnap_value = 0;
-                       ebc0_cs2_bncr_value = 0;
+                       ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
+                       ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
                        ebc0_cs3_bnap_value = 0;
                        ebc0_cs3_bncr_value = 0;
                } else {
@@ -985,7 +1067,7 @@ void ext_bus_cntlr_init(void)
   +----------------------------------------------------------------------------*/
 uart_config_nb_t get_uart_configuration(void)
 {
-       return (L4); /* test-only */
+       return (L4);
 }
 
 /*----------------------------------------------------------------------------+
@@ -1132,8 +1214,7 @@ void ndfc_selection_in_fpga(void)
 
        fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
        fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
-       /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
-       /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
+       fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
        out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
 }
 
@@ -1725,11 +1806,15 @@ void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t
        *(core_select_P+UIC_0_3)                = CORE_SELECTED;
        *(core_select_P+UIC_4_9)                = CORE_SELECTED;
 
-       *(core_select_P+SCP_CORE)            = CORE_SELECTED;
-       *(core_select_P+DMA_CHANNEL_CD)            = CORE_SELECTED;
-       *(core_select_P+PACKET_REJ_FUNC_AVAIL)            = CORE_SELECTED;
+       *(core_select_P+SCP_CORE)               = CORE_SELECTED;
+       *(core_select_P+DMA_CHANNEL_CD)         = CORE_SELECTED;
+       *(core_select_P+PACKET_REJ_FUNC_AVAIL)  = CORE_SELECTED;
        *(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
 
+       if (is_nand_selected()) {
+               *(core_select_P+NAND_FLASH)     = CORE_SELECTED;
+       }
+
        *config_val_P = CONFIG_IS_VALID;
 
 }
@@ -1901,9 +1986,8 @@ void configure_ppc440ep_pins(void)
                      SDR0_CUST0_NDFC_ENABLE    |
                      SDR0_CUST0_NDFC_BW_8_BIT  |
                      SDR0_CUST0_NDFC_ARE_MASK  |
-                     SDR0_CUST0_CHIPSELGAT_EN1 );
-               /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
-               /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
+                     SDR0_CUST0_CHIPSELGAT_EN1 |
+                     SDR0_CUST0_CHIPSELGAT_EN2);
 
                ndfc_selection_in_fpga();
        }
index 97a4b988d54449eb04fced8cddfd2dff47b2a596..a30ab7ada8f2a2e7ed9316ed73ea1aad89179213 100644 (file)
@@ -50,15 +50,16 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];       /* info for FLASH chips        */
 /*
  * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
  */
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
        {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
        {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
        {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
-       {0x87800000, 0x87880000, 0xFF800001}, /* 3:boot from big flash 33*/
-       {0x87800000, 0x87880000, 0xFF800001}, /* 4:boot from big flash 66*/
+       {0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
+       {0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
        {0x00000000, 0x00000000, 0x00000000}, /* 5:boot from             */
        {0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66      */
        {0x00000000, 0x00000000, 0x00000000}, /* 7:boot from             */
+       {0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
 };
 
 /*
@@ -117,6 +118,10 @@ unsigned long flash_init(void)
                        index = 2;
                        break;
                }
+       } else if (index == 0) {
+               if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
+                       index = 8; /* sram below op code flash -> new index 8 */
+               }
        }
 
        DEBUGF("\n");
index 907029345b0f2519ef05e7a0959958d321b8afca..7820107aa5a1ff38d8db02ac2cf713d18311c77c 100644 (file)
 
 tlbtab:
     tlbtab_start
-       /*
-               0xf0000000 must be first, before relocation SA_I must be off to use the
-           dcache as stack. It is patched after relocation to enable SA_I
-       */
-    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+
+    /*
+     * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+     * speed up boot process. It is patched after relocation to enable SA_I
+     */
+    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+
+    /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+
+    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+    tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
 
     /* PCI */
     tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
@@ -102,6 +108,6 @@ tlbtab:
     tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
 
     /* USB 2.0 Device */
-    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
 
     tlbtab_end
index 63227fa1536210f489dc626f178485dc31b5e27e..68cbf34391c4ea0e5af62e02de0c13ee868b1f8a 100644 (file)
@@ -375,8 +375,8 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
                out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
                                   (RGMII_FER_RGMII << RGMII_FER_V (3))));
        }
-
 #endif
+
        out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
        __asm__ volatile ("eieio");
 
@@ -521,13 +521,13 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
        }
        mtsdr(sdr_mfr, reg);
 #endif
+
        /* Set ZMII/RGMII speed according to the phy link speed */
        reg = in32 (ZMII_SSR);
        if ( (speed == 100) || (speed == 1000) )
                out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
        else
-               out32 (ZMII_SSR,
-                      reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
+               out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
 
        if ((devnum == 2) || (devnum == 3)) {
                if (speed == 1000)
@@ -672,7 +672,7 @@ static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
                /* set RX buffer size */
                mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
                break;
-#endif /*CONFIG_440GX */
+#endif /* CONFIG_440GX */
        case 0:
        default:
                /* setup MAL tx & rx channel pointers */
index 88bbadfc29b75e81c7d7e872144067247b9d26de..64ea6bef91ff602b139a13d013e5c7ed86beb675 100644 (file)
  *----------------------------------------------------------------------*/
 #define CONFIG_BAMBOO          1       /* Board is BAMBOO              */
 #define CONFIG_440EP           1       /* Specific PPC440EP support    */
-
 #define CONFIG_4xx             1       /* ... PPC4xx family            */
-#define CONFIG_BOARD_EARLY_INIT_F      1   /* Call board_early_init_f  */
 #define CONFIG_SYS_CLK_FREQ    33333333    /* external freq to pll     */
 
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f     */
+
+/*
+ * Please note that, if NAND support is enabled, the 2nd ethernet port
+ * can't be used because of pin multiplexing. So, if you want to use the
+ * 2nd ethernet port you have to "undef" the following define.
+ */
+#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
+
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
 
 #define CFG_USB_DEVICE          0x50000000
 #define CFG_NVRAM_BASE_ADDR     0x80000000
-#define CFG_BCSR_BASE          (CFG_NVRAM_BASE_ADDR | 0x2000)
+#define CFG_BOOT_BASE_ADDR      0xf0000000
+#define CFG_NAND_ADDR           0x90000000
+#define CFG_NAND2_ADDR          0x94000000
 
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer (placed in SDRAM)
  *----------------------------------------------------------------------*/
-#define CFG_INIT_RAM_ADDR      0xf0000000              /* DCache       */
-#define CFG_INIT_RAM_END       0x1000
+#define CFG_INIT_RAM_ADDR      0x70000000              /* DCache       */
+#define CFG_INIT_RAM_END       (8 << 10)
 #define CFG_GBL_DATA_SIZE      256                     /* num bytes initial data       */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
@@ -88,7 +97,7 @@
  * The DS1558 code assumes this condition
  *
  *----------------------------------------------------------------------*/
-#define CFG_NVRAM_SIZE     (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
+#define CFG_NVRAM_SIZE         (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
 #define CONFIG_RTC_DS1556      1                        /* DS1556 RTC          */
 
 /*-----------------------------------------------------------------------
 #define CFG_FLASH_ADDR1         0x2aa
 #define CFG_FLASH_WORD_SIZE     unsigned char
 
-#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device     */
-#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device     */
+#define CFG_FLASH_2ND_16BIT_DEV 1         /* bamboo has 8 and 16bit device      */
+#define CFG_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device    */
 
 #ifdef CFG_ENV_IS_IN_FLASH
 #define CFG_ENV_SECT_SIZE      0x10000         /* size of one complete sector  */
 #define CFG_ENV_ADDR           (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
-#define        CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
+#define        CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 
-#if 0 /* test-only */
 /* Address and size of Redundant Environment Sector    */
 #define CFG_ENV_ADDR_REDUND    (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 #define CFG_ENV_SIZE_REDUND    (CFG_ENV_SIZE)
-#endif
 #endif /* CFG_ENV_IS_IN_FLASH */
 
+/*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define NAND_CMD_REG   (0x00) /* NandFlash Command Register */
+#define NAND_ADDR_REG  (0x04) /* NandFlash Address Register */
+#define NAND_DATA_REG  (0x08) /* NandFlash Data Register */
+#define NAND_ECC0_REG  (0x10) /* NandFlash ECC Register0 */
+#define NAND_ECC1_REG  (0x14) /* NandFlash ECC Register1 */
+#define NAND_ECC2_REG  (0x18) /* NandFlash ECC Register2 */
+#define NAND_ECC3_REG  (0x1C) /* NandFlash ECC Register3 */
+#define NAND_ECC4_REG  (0x20) /* NandFlash ECC Register4 */
+#define NAND_ECC5_REG  (0x24) /* NandFlash ECC Register5 */
+#define NAND_ECC6_REG  (0x28) /* NandFlash ECC Register6 */
+#define NAND_ECC7_REG  (0x2C) /* NandFlash ECC Register7 */
+#define NAND_CR0_REG   (0x30) /* NandFlash Device Bank0 Config Register */
+#define NAND_CR1_REG   (0x34) /* NandFlash Device Bank1 Config Register */
+#define NAND_CR2_REG   (0x38) /* NandFlash Device Bank2 Config Register */
+#define NAND_CR3_REG   (0x3C) /* NandFlash Device Bank3 Config Register */
+#define NAND_CCR_REG   (0x40) /* NandFlash Core Configuration Register */
+#define NAND_STAT_REG  (0x44) /* NandFlash Device Status Register */
+#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
+#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
+
+/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
+#define NAND0_CMD_READ1_HALF1     0x00     /* Starting addr for 1rst half of registers */
+#define NAND0_CMD_READ1_HALF2     0x01     /* Starting addr for 2nd half of registers */
+#define NAND0_CMD_READ2           0x50
+#define NAND0_CMD_READ_ID         0x90
+#define NAND0_CMD_READ_STATUS     0x70
+#define NAND0_CMD_RESET           0xFF
+#define NAND0_CMD_PAGE_PROG       0x80
+#define NAND0_CMD_PAGE_PROG_TRUE  0x10
+#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
+#define NAND0_CMD_BLOCK_ERASE     0x60
+#define NAND0_CMD_BLOCK_ERASE_END 0xD0
+
+#define CFG_MAX_NAND_DEVICE     1      /* Max number of NAND devices */
+#define SECTORSIZE              512
+
+#define ADDR_COLUMN             1
+#define ADDR_PAGE               2
+#define ADDR_COLUMN_PAGE        3
+
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS         1
+#define NAND_MAX_CHIPS          1
+
+#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
+#define WRITE_NAND(d, adr)      do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
+#define READ_NAND(adr)          (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
+#define NAND_WAIT_READY(nand)   while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
+
+/* not needed with 440EP NAND controller */
+#define NAND_CTL_CLRALE(nandptr)
+#define NAND_CTL_SETALE(nandptr)
+#define NAND_CTL_CLRCLE(nandptr)
+#define NAND_CTL_SETCLE(nandptr)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------------- */
 #define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
 
 #define CONFIG_MII             1       /* MII PHY management           */
-#define CONFIG_NET_MULTI        1       /* required for netconsole      */
 #define CONFIG_PHY_ADDR                0       /* PHY address, See schematics  */
+
+#ifndef CONFIG_BAMBOO_NAND
+#define CONFIG_NET_MULTI        1       /* required for netconsole      */
 #define CONFIG_PHY1_ADDR        1
 #define CONFIG_HAS_ETH1                1       /* add support for "eth1addr"   */
+#endif /* CONFIG_BAMBOO_NAND */
+
 #define CONFIG_NO_PHY_RESET     1       /* no PHY reset on bamboo!!!    */
 
 #define CFG_RX_ETH_BUFFER      32      /* Number of ethernet rx buffers & descriptors */
 #define USB_2_0_DEVICE
 #endif /*CONFIG_440EP*/
 
+#ifdef CONFIG_BAMBOO_NAND
+#define _CFG_CMD_NAND CFG_CMD_NAND
+#else
+#define _CFG_CMD_NAND 0
+#endif /* CONFIG_BAMBOO_NAND */
+
 #define CONFIG_COMMANDS               (CONFIG_CMD_DFL  | \
                                CFG_CMD_ASKENV  | \
+                               CFG_CMD_EEPROM  | \
                                CFG_CMD_DATE    | \
                                CFG_CMD_DHCP    | \
                                CFG_CMD_DIAG    | \
                                CFG_CMD_REGINFO | \
                                CFG_CMD_SDRAM   | \
                                CFG_CMD_USB     | \
+                               _CFG_CMD_NAND   | \
                                CFG_CMD_SNTP    )
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP                   /* undef to save memory         */
-#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+#define CFG_PROMPT             "=> "   /* Monitor Command Prompt       */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
+#define CFG_CBSIZE             1024    /* Console I/O Buffer Size      */
 #else
-#define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
+#define CFG_CBSIZE             256     /* Console I/O Buffer Size      */
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS    16              /* max number of command args   */
-#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS            16      /* max number of command args   */
+#define CFG_BARGSIZE           CFG_CBSIZE /* Boot Argument Buffer Size */
 
-#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
-#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+#define CFG_MEMTEST_START      0x0400000 /* memtest works on           */
+#define CFG_MEMTEST_END                0x0C00000 /* 4 ... 12 MB in DRAM        */
 
 #define CFG_LOAD_ADDR          0x100000        /* default load address */
-#define CFG_EXTBDINFO              1   /* To use extended board_into (bd_t) */
-#define CONFIG_LYNXKDI          1   /* support kdi files */
+#define CFG_EXTBDINFO          1       /* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
 
-#define CFG_HZ         1000            /* decrementer freq: 1 ms ticks */
+#define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
 
 /*-----------------------------------------------------------------------
  * PCI stuff
  *-----------------------------------------------------------------------
  */
 /* General PCI */
-#define CONFIG_PCI                                 /* include pci support              */
-#undef  CONFIG_PCI_PNP                         /* do (not) pci plug-and-play         */
+#define CONFIG_PCI                     /* include pci support          */
+#undef  CONFIG_PCI_PNP                 /* do (not) pci plug-and-play   */
 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
-#define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
+#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 
 /* Board-specific PCI */
 #define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 #define CFG_PCI_TARGET_INIT
 #define CFG_PCI_MASTER_INIT
 
-#define CFG_PCI_SUBSYS_VENDORID 0x1014  /* IBM */
-#define CFG_PCI_SUBSYS_ID 0xcafe        /* Whatever */
+#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
+#define CFG_PCI_SUBSYS_ID       0xcafe /* Whatever */
 
 /*
  * For booting Linux, the board info and command line data
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                32768   /* For IBM 440 CPUs                     */
+#define CFG_DCACHE_SIZE                (32<<10) /* For IBM 440 CPUs                    */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */