Use new bitmask for SOC_TYPE in QC/A common registers definition header

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index aed2120004ad9a232675571b9324c9354de20315..10f870d0e2cb12ff11a298e217b2ddd796607de7 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -26,7 +26,7 @@
  */
 #define QCA_DDR_CTRL_BASE_REG          QCA_APB_BASE_REG + 0x00000000
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_HSUART_BASE_REG             QCA_APB_BASE_REG + 0x00020000
 #else
        #define QCA_LSUART_BASE_REG             QCA_APB_BASE_REG + 0x00020000
@@ -41,11 +41,10 @@
 #define QCA_RTC_BASE_REG                       QCA_APB_BASE_REG + 0x00107000
 #define QCA_PLL_SRIF_BASE_REG          QCA_APB_BASE_REG + 0x00116000
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_SLIC_BASE_REG               QCA_APB_BASE_REG + 0x00090000
-#elif (SOC_TYPE == QCA_AR9341_SOC || \
-          SOC_TYPE == QCA_AR9344_SOC || \
-          SOC_TYPE == QCA_AR9558_SOC)
+#elif (SOC_TYPE & QCA_AR934X_SOC) || \
+         (SOC_TYPE & QCA_AR955X_SOC)
        #define QCA_SLIC_BASE_REG               QCA_APB_BASE_REG + 0x000A9000
 #endif
 
@@ -62,7 +61,7 @@
 #define QCA_DDR_TAP_CTRL_0_REG                                 QCA_DDR_CTRL_BASE_REG + 0x01C
 #define QCA_DDR_TAP_CTRL_1_REG                                 QCA_DDR_CTRL_BASE_REG + 0x020
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_DDR_WB_FLUSH_GE0_REG                        QCA_DDR_CTRL_BASE_REG + 0x07C
        #define QCA_DDR_WB_FLUSH_GE1_REG                        QCA_DDR_CTRL_BASE_REG + 0x080
        #define QCA_DDR_WB_FLUSH_USB_REG                        QCA_DDR_CTRL_BASE_REG + 0x084
@@ -76,7 +75,7 @@
        #define QCA_DDR_WB_FLUSH_SRC2_REG                       QCA_DDR_CTRL_BASE_REG + 0x0B4
 #endif
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_DDR_DDR2_CFG_REG                            QCA_DDR_CTRL_BASE_REG + 0x08C
        #define QCA_DDR_EMR2_REG                                        QCA_DDR_CTRL_BASE_REG + 0x090
        #define QCA_DDR_EMR3_REG                                        QCA_DDR_CTRL_BASE_REG + 0x094
@@ -344,13 +343,13 @@
 /*
  * GPIO registers
  */
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_GPIO_COUNT                                          30
-#elif (SOC_TYPE == QCA_AR9341_SOC || SOC_TYPE == QCA_AR9344_SOC)
+#elif (SOC_TYPE & QCA_AR934X_SOC)
        #define QCA_GPIO_COUNT                                          23
-#elif (SOC_TYPE == QCA_QCA9531_SOC || QCA_QCA9533_SOC)
+#elif (SOC_TYPE & QCA_QCA953X_SOC)
        #define QCA_GPIO_COUNT                                          18
-#elif (SOC_TYPE == QCA_QCA9558_SOC)
+#elif (SOC_TYPE & QCA_QCA955X_SOC)
        #define QCA_GPIO_COUNT                                          24
 #endif
 
@@ -365,7 +364,7 @@
 #define QCA_GPIO_INT_PENDING_REG                               QCA_GPIO_BASE_REG + 0x20
 #define QCA_GPIO_INT_MASK_REG                                  QCA_GPIO_BASE_REG + 0x24
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_GPIO_FUNC_1_REG                                     QCA_GPIO_BASE_REG + 0x28
        #define QCA_GPIO_IN_ETH_SWITCH_LED_REG          QCA_GPIO_BASE_REG + 0x2C
        #define QCA_GPIO_FUNC_2_REG                                     QCA_GPIO_BASE_REG + 0x30
@@ -374,7 +373,7 @@
        #define QCA_GPIO_WLAN_MUX_SET2_REG                      QCA_GPIO_BASE_REG + 0x3C
        #define QCA_GPIO_WLAN_MUX_SET3_REG                      QCA_GPIO_BASE_REG + 0x40
 #else
-       #if (SOC_TYPE == QCA_QCA9558_SOC)
+       #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_GPIO_SPARE_BITS_REG                 QCA_GPIO_BASE_REG + 0x28
        #else
                #define QCA_GPIO_IN_ETH_SWITCH_LED_REG  QCA_GPIO_BASE_REG + 0x28
@@ -400,7 +399,7 @@
  */
 
 /* GPIO_FUNCTION_1 register (GPIO function) */
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_GPIO_FUNC_1_EJTAG_DIS_SHIFT                 0
        #define QCA_GPIO_FUNC_1_EJTAG_DIS_MASK                  (1 << QCA_GPIO_FUNC_1_EJTAG_DIS_SHIFT)
        #define QCA_GPIO_FUNC_1_UART_EN_SHIFT                   1
@@ -446,7 +445,7 @@
  */
 #define QCA_PLL_CPU_PLL_CFG_REG                                                        QCA_PLL_BASE_REG + 0x00
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_PLL_CPU_PLL_CFG2_REG                                        QCA_PLL_BASE_REG + 0x04
        #define QCA_PLL_CPU_CLK_CTRL_REG                                        QCA_PLL_BASE_REG + 0x08
        #define QCA_PLL_PLL_DITHER_FRAC_REG                                     QCA_PLL_BASE_REG + 0x10
@@ -459,7 +458,7 @@
        #define QCA_PLL_DDR_PLL_CFG_REG                                         QCA_PLL_BASE_REG + 0x04
        #define QCA_PLL_CPU_DDR_CLK_CTRL_REG                            QCA_PLL_BASE_REG + 0x08
 
-       #if (SOC_TYPE == QCA_QCA9558_SOC)
+       #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_PLL_PCIE_PLL_CFG_REG                                QCA_PLL_BASE_REG + 0x0C
                #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG             QCA_PLL_BASE_REG + 0x10
                #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG             QCA_PLL_BASE_REG + 0x14
@@ -486,7 +485,7 @@
                #define QCA_PLL_LDO_POWER_CTRL_REG                              QCA_PLL_BASE_REG + 0x20
                #define QCA_PLL_SWITCH_CLK_CTRL_REG                             QCA_PLL_BASE_REG + 0x24
 
-       #if (SOC_TYPE == QCA_AR9344_SOC)
+       #if (SOC_TYPE & QCA_AR9344_SOC)
                #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG                QCA_PLL_BASE_REG + 0x28
        #else
                #define QCA_PLL_CURR_PLL_DITHER_REG                             QCA_PLL_BASE_REG + 0x28
@@ -509,7 +508,7 @@
  */
 
 /* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT                                 0
        #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK                                  BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10)
        #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT                                  10
@@ -672,7 +671,7 @@
 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT                         31
 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK                          (1 << QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT)
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT                  0
        #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK                   BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 10)
@@ -765,7 +764,7 @@
 #define QCA_RST_GENERAL_TIMER4_REG                             QCA_RST_BASE_REG + 0xA4
 #define QCA_RST_GENERAL_TIMER4_RELOAD_REG              QCA_RST_BASE_REG + 0xA8
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_BOOTSTRAP_REG                           QCA_RST_BASE_REG + 0xAC
 #else
        #define QCA_RST_BOOTSTRAP_REG                           QCA_RST_BASE_REG + 0xB0
@@ -776,7 +775,7 @@
  */
 
 /* RST_BOOTSTRAP (Reset bootstrap) */
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT                 0
 #else
        #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT                 4
@@ -785,7 +784,7 @@
 #define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL                      0x0
 #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL                      0x1
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT                12
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK                 BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL              0
@@ -795,7 +794,7 @@
        #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT                0
 
        /* v2 does not support SDR, but we can read reserved bit and make it universal */
-       #if (SOC_TYPE == QCA_QCA9531_SOC || QCA_QCA9533_SOC)
+       #if (SOC_TYPE & QCA_QCA953X_SOC)
                #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK         BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2)
        #else
                #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK         (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT)
@@ -820,7 +819,7 @@
 #define QCA_RST_RESET_USB_HOST_RST_SHIFT                               5
 #define QCA_RST_RESET_USB_HOST_RST_MASK                                        (1 << QCA_RST_RESET_USB_HOST_RST_SHIFT)
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_RESET_SLIC_RST_SHIFT                            6
        #define QCA_RST_RESET_SLIC_RST_MASK                                     (1 << QCA_RST_RESET_SLIC_RST_SHIFT)
 #else
@@ -833,7 +832,7 @@
 #define QCA_RST_RESET_PCIE_PHY_RST_SHIFT                               7
 #define QCA_RST_RESET_PCIE_PHY_RST_MASK                                        (1 << QCA_RST_RESET_PCIE_PHY_RST_SHIFT)
 
-#if (SOC_TYPE == QCA_QCA9558_SOC)
+#if (SOC_TYPE & QCA_QCA955X_SOC)
        #define QCA_RST_RESET_ETH_SGMII_RST_SHIFT                       8
        #define QCA_RST_RESET_ETH_SGMII_RST_MASK                        (1 << QCA_RST_RESET_ETH_SGMII_RST_SHIFT)
 #else
@@ -846,7 +845,7 @@
 #define QCA_RST_RESET_HOST_DMA_INT_SHIFT                               10
 #define QCA_RST_RESET_HOST_DMA_INT_MASK                                        (1 << QCA_RST_RESET_HOST_DMA_INT_SHIFT)
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_RESET_WLAN_RST_SHIFT                            11
        #define QCA_RST_RESET_WLAN_RST_MASK                                     (1 << QCA_RST_RESET_WLAN_RST_SHIFT)
 #else
@@ -854,11 +853,11 @@
        #define QCA_RST_RESET_USB_PHY_ARST_MASK                         (1 << QCA_RST_RESET_USB_PHY_ARST_SHIFT)
 #endif
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT                     14
        #define QCA_RST_RESET_ETH_SWITCH_ARST_MASK                      (1 << QCA_RST_RESET_ETH_SWITCH_ARST_SHIFT)
 #else
-       #if (SOC_TYPE == QCA_QCA9558_SOC)
+       #if (SOC_TYPE & QCA_QCA955X_SOC)
                #define QCA_RST_RESET_ETH_SGMII_ARST_SHIFT              12
                #define QCA_RST_RESET_ETH_SGMII_ARST_MASK               (1 << QCA_RST_RESET_ETH_SGMII_ARST_SHIFT)
        #else
@@ -901,9 +900,8 @@
 #define QCA_RST_RESET_EXT_RST_SHIFT                                            28
 #define QCA_RST_RESET_EXT_RST_MASK                                             (1 << QCA_RST_RESET_EXT_RST_SHIFT)
 
-#if (SOC_TYPE == QCA_QCA9558_SOC || \
-        SOC_TYPE == QCA_AR9344_SOC  || \
-        SOC_TYPE == QCA_AR9341_SOC)
+#if (SOC_TYPE & QCA_AR934X_SOC) || \
+       (SOC_TYPE & QCA_QCA955X_SOC)
        #define QCA_RST_RESET_HOST_DMA_RST_SHIFT                        29
        #define QCA_RST_RESET_HOST_DMA_RST_MASK                         (1 << QCA_RST_RESET_HOST_DMA_RST_SHIFT)
 #else
@@ -918,7 +916,7 @@
 #define QCA_RST_REVISION_ID_MAJOR_SHIFT                                4
 #define QCA_RST_REVISION_ID_MAJOR_MASK                         BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12)
 
-#if (SOC_TYPE == QCA_AR933X_SOC)
+#if (SOC_TYPE & QCA_AR933X_SOC)
        #define QCA_RST_REVISION_ID_REV_SHIFT                   0
        #define QCA_RST_REVISION_ID_REV_MASK                    BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2)
 #else