mpc8xx: remove netta, netta2, netphone board support
authorMasahiro Yamada <yamada.m@jp.panasonic.com>
Fri, 20 Jun 2014 04:54:54 +0000 (13:54 +0900)
committerTom Rini <trini@ti.com>
Mon, 7 Jul 2014 23:43:02 +0000 (19:43 -0400)
These boards are old enough and have no maintainers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
27 files changed:
arch/powerpc/cpu/mpc8xx/fec.c
board/netphone/Makefile [deleted file]
board/netphone/flash.c [deleted file]
board/netphone/netphone.c [deleted file]
board/netphone/phone_console.c [deleted file]
board/netphone/u-boot.lds [deleted file]
board/netphone/u-boot.lds.debug [deleted file]
board/netta/Makefile [deleted file]
board/netta/codec.c [deleted file]
board/netta/dsp.c [deleted file]
board/netta/flash.c [deleted file]
board/netta/netta.c [deleted file]
board/netta/pcmcia.c [deleted file]
board/netta/u-boot.lds [deleted file]
board/netta/u-boot.lds.debug [deleted file]
board/netta2/Makefile [deleted file]
board/netta2/flash.c [deleted file]
board/netta2/netta2.c [deleted file]
board/netta2/u-boot.lds [deleted file]
board/netta2/u-boot.lds.debug [deleted file]
boards.cfg
doc/README.scrapyard
include/configs/NETPHONE.h [deleted file]
include/configs/NETTA.h [deleted file]
include/configs/NETTA2.h [deleted file]
include/pcmcia.h
include/status_led.h

index 65dfeabba438f82ce25e4716a7cecf200704bdf8..ccb460ef96a8546661fd561b76fb4d8c0283c684 100644 (file)
@@ -377,26 +377,6 @@ static void fec_pin_init(int fecidx)
         */
        immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
 
-#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
-       {
-               volatile fec_t *fecp;
-
-               /*
-                * only two FECs please
-                */
-               if ((unsigned int)fecidx >= 2)
-                       hang();
-
-               if (fecidx == 0)
-                       fecp = &immr->im_cpm.cp_fec1;
-               else
-                       fecp = &immr->im_cpm.cp_fec2;
-
-               /* our PHYs are the limit at 2.5 MHz */
-               fecp->fec_mii_speed <<= 1;
-       }
-#endif
-
 #if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII)
        /* use MDC for MII */
        immr->im_ioport.iop_pdpar |=  0x0080;
diff --git a/board/netphone/Makefile b/board/netphone/Makefile
deleted file mode 100644 (file)
index ba34605..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = netphone.o flash.o phone_console.o
diff --git a/board/netphone/flash.c b/board/netphone/flash.c
deleted file mode 100644 (file)
index 91bd968..0000000
+++ /dev/null
@@ -1,513 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips    */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       unsigned long size;
-#if CONFIG_NETPHONE_VERSION == 2
-       unsigned long size1;
-#endif
-       int i;
-
-       /* Init: no FLASHes known */
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-
-       size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
-       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-                       size, size << 20);
-       }
-
-       /* Remap FLASH according to real size */
-       memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-       memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
-       /* Re-do sizing to get full correct info */
-       size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                       CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-                       &flash_info[0]);
-
-       flash_protect ( FLAG_PROTECT_SET,
-                       CONFIG_ENV_ADDR,
-                       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-                       &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-       flash_protect ( FLAG_PROTECT_SET,
-                       CONFIG_ENV_ADDR_REDUND,
-                       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-                       &flash_info[0]);
-#endif
-
-       flash_info[0].size = size;
-
-#if CONFIG_NETPHONE_VERSION == 2
-       size1 = flash_get_size((vu_long *) FLASH_BASE4_PRELIM, &flash_info[1]);
-       if (size1 > 0) {
-               if (flash_info[1].flash_id == FLASH_UNKNOWN)
-                       printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
-
-               /* Remap FLASH according to real size */
-               memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
-               memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
-
-               /* Re-do sizing to get full correct info */
-               size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
-
-               flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
-
-               size += size1;
-       } else
-               memctl->memc_br4 &= ~BR_V;
-#endif
-
-       return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
-       int i;
-
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000);
-               }
-       } else if (info->flash_id & FLASH_BTYPE) {
-               /* set sector offsets for bottom boot block type    */
-               info->start[0] = base + 0x00000000;
-               info->start[1] = base + 0x00004000;
-               info->start[2] = base + 0x00006000;
-               info->start[3] = base + 0x00008000;
-               for (i = 4; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000) - 0x00030000;
-               }
-       } else {
-               /* set sector offsets for top boot block type       */
-               i = info->sector_count - 1;
-               info->start[i--] = base + info->size - 0x00004000;
-               info->start[i--] = base + info->size - 0x00006000;
-               info->start[i--] = base + info->size - 0x00008000;
-               for (; i >= 0; i--) {
-                       info->start[i] = base + i * 0x00010000;
-               }
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_AMD:
-               printf("AMD ");
-               break;
-       case FLASH_MAN_FUJ:
-               printf("FUJITSU ");
-               break;
-       case FLASH_MAN_MX:
-               printf("MXIC ");
-               break;
-       default:
-               printf("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM040:
-               printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM400B:
-               printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM400T:
-               printf("AM29LV400T (4 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM800B:
-               printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM800T:
-               printf("AM29LV800T (8 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM160B:
-               printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM160T:
-               printf("AM29LV160T (16 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM320B:
-               printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM320T:
-               printf("AM29LV320T (32 Mbit, top boot sector)\n");
-               break;
-       default:
-               printf("Unknown Chip Type\n");
-               break;
-       }
-
-       printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
-       printf("  Sector Start Addresses:");
-       for (i = 0; i < info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf("\n   ");
-               printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
-       }
-       printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-       short i;
-       uchar mid;
-       uchar pid;
-       vu_char *caddr = (vu_char *) addr;
-       ulong base = (ulong) addr;
-
-       /* Write auto select command: read Manufacturer ID */
-       caddr[0x0555] = 0xAA;
-       caddr[0x02AA] = 0x55;
-       caddr[0x0555] = 0x90;
-
-       mid = caddr[0];
-       switch (mid) {
-       case (AMD_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_AMD;
-               break;
-       case (FUJ_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_FUJ;
-               break;
-       case (MX_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_MX;
-               break;
-       case (STM_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_STM;
-               break;
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               return (0);                             /* no or unknown flash  */
-       }
-
-       pid = caddr[1];                         /* device ID        */
-       switch (pid) {
-       case (AMD_ID_LV400T & 0xFF):
-               info->flash_id += FLASH_AM400T;
-               info->sector_count = 11;
-               info->size = 0x00080000;
-               break;                                  /* => 512 kB        */
-
-       case (AMD_ID_LV400B & 0xFF):
-               info->flash_id += FLASH_AM400B;
-               info->sector_count = 11;
-               info->size = 0x00080000;
-               break;                                  /* => 512 kB        */
-
-       case (AMD_ID_LV800T & 0xFF):
-               info->flash_id += FLASH_AM800T;
-               info->sector_count = 19;
-               info->size = 0x00100000;
-               break;                                  /* => 1 MB      */
-
-       case (AMD_ID_LV800B & 0xFF):
-               info->flash_id += FLASH_AM800B;
-               info->sector_count = 19;
-               info->size = 0x00100000;
-               break;                                  /* => 1 MB      */
-
-       case (AMD_ID_LV160T & 0xFF):
-               info->flash_id += FLASH_AM160T;
-               info->sector_count = 35;
-               info->size = 0x00200000;
-               break;                                  /* => 2 MB      */
-
-       case (AMD_ID_LV160B & 0xFF):
-               info->flash_id += FLASH_AM160B;
-               info->sector_count = 35;
-               info->size = 0x00200000;
-               break;                                  /* => 2 MB      */
-
-       case (AMD_ID_LV040B & 0xFF):
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00080000;
-               break;
-
-       case (STM_ID_M29W040B & 0xFF):
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00080000;
-               break;
-
-#if 0                                                  /* enable when device IDs are available */
-       case (AMD_ID_LV320T & 0xFF):
-               info->flash_id += FLASH_AM320T;
-               info->sector_count = 67;
-               info->size = 0x00400000;
-               break;                                  /* => 4 MB      */
-
-       case (AMD_ID_LV320B & 0xFF):
-               info->flash_id += FLASH_AM320B;
-               info->sector_count = 67;
-               info->size = 0x00400000;
-               break;                                  /* => 4 MB      */
-#endif
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               return (0);                             /* => no or unknown flash */
-
-       }
-
-       printf(" ");
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000);
-               }
-       } else if (info->flash_id & FLASH_BTYPE) {
-               /* set sector offsets for bottom boot block type    */
-               info->start[0] = base + 0x00000000;
-               info->start[1] = base + 0x00004000;
-               info->start[2] = base + 0x00006000;
-               info->start[3] = base + 0x00008000;
-               for (i = 4; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000) - 0x00030000;
-               }
-       } else {
-               /* set sector offsets for top boot block type       */
-               i = info->sector_count - 1;
-               info->start[i--] = base + info->size - 0x00004000;
-               info->start[i--] = base + info->size - 0x00006000;
-               info->start[i--] = base + info->size - 0x00008000;
-               for (; i >= 0; i--) {
-                       info->start[i] = base + i * 0x00010000;
-               }
-       }
-
-       /* check for protected sectors */
-       for (i = 0; i < info->sector_count; i++) {
-               /* read sector protection: D0 = 1 if protected */
-               caddr = (volatile unsigned char *)(info->start[i]);
-               info->protect[i] = caddr[2] & 1;
-       }
-
-       /*
-        * Prevent writes to uninitialized FLASH.
-        */
-       if (info->flash_id != FLASH_UNKNOWN) {
-               caddr = (vu_char *) info->start[0];
-
-               caddr[0x0555] = 0xAA;
-               caddr[0x02AA] = 0x55;
-               caddr[0x0555] = 0xF0;
-
-               udelay(20000);
-       }
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-       vu_char *addr = (vu_char *) (info->start[0]);
-       int flag, prot, sect, l_sect;
-       ulong start, now, last;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf("- missing\n");
-               } else {
-                       printf("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       if ((info->flash_id == FLASH_UNKNOWN) ||
-           (info->flash_id > FLASH_AMD_COMP)) {
-               printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf("- Warning: %d protected sectors will not be erased!\n", prot);
-       } else {
-               printf("\n");
-       }
-
-       l_sect = -1;
-
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-       addr[0x0555] = 0x80;
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect <= s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       addr = (vu_char *) (info->start[sect]);
-                       addr[0] = 0x30;
-                       l_sect = sect;
-               }
-       }
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* wait at least 80us - let's wait 1 ms */
-       udelay(1000);
-
-       /*
-        * We wait for the last triggered sector
-        */
-       if (l_sect < 0)
-               goto DONE;
-
-       start = get_timer(0);
-       last = start;
-       addr = (vu_char *) (info->start[l_sect]);
-       while ((addr[0] & 0x80) != 0x80) {
-               if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                       printf("Timeout\n");
-                       return 1;
-               }
-               /* show that we're waiting */
-               if ((now - last) > 1000) {      /* every second */
-                       putc('.');
-                       last = now;
-               }
-       }
-
-DONE:
-       /* reset to read mode */
-       addr = (vu_char *) info->start[0];
-       addr[0] = 0xF0;                         /* reset bank */
-
-       printf(" done\n");
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-       int rc;
-
-       while (cnt > 0) {
-               if ((rc = write_byte(info, addr++, *src++)) != 0) {
-                       return (rc);
-               }
-               --cnt;
-       }
-
-       return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
-       vu_char *addr = (vu_char *) (info->start[0]);
-       ulong start;
-       int flag;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*((vu_char *) dest) & data) != data) {
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-       addr[0x0555] = 0xA0;
-
-       *((vu_char *) dest) = data;
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* data polling for D7 */
-       start = get_timer(0);
-       while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       return (1);
-               }
-       }
-       return (0);
-}
diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c
deleted file mode 100644 (file)
index 8ff4489..0000000
+++ /dev/null
@@ -1,690 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <sed156x.h>
-#include <status_led.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
-               unsigned char  reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char  addr,
-               unsigned char  reg, unsigned short value);
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b)                                (1U << (31-(_b)))
-#define _BDR(_l, _h)                   (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b)                                (1U << (15-(_b)))
-#define _BWR(_l, _h)                   (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b)                                (1U << (7-(_b)))
-#define _BBR(_l, _h)                   (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b)                         _BD(_b)
-#define _BR(_l, _h)                    _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
-       printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
-       return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_     0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000                0x00000000
-#define CS_0001                0x10000000
-#define CS_0010                0x20000000
-#define CS_0011                0x30000000
-#define CS_0100                0x40000000
-#define CS_0101                0x50000000
-#define CS_0110                0x60000000
-#define CS_0111                0x70000000
-#define CS_1000                0x80000000
-#define CS_1001                0x90000000
-#define CS_1010                0xA0000000
-#define CS_1011                0xB0000000
-#define CS_1100                0xC0000000
-#define CS_1101                0xD0000000
-#define CS_1110                0xE0000000
-#define CS_1111                0xF0000000
-
-#define BS_0000                0x00000000
-#define BS_0001                0x01000000
-#define BS_0010                0x02000000
-#define BS_0011                0x03000000
-#define BS_0100                0x04000000
-#define BS_0101                0x05000000
-#define BS_0110                0x06000000
-#define BS_0111                0x07000000
-#define BS_1000                0x08000000
-#define BS_1001                0x09000000
-#define BS_1010                0x0A000000
-#define BS_1011                0x0B000000
-#define BS_1100                0x0C000000
-#define BS_1101                0x0D000000
-#define BS_1110                0x0E000000
-#define BS_1111                0x0F000000
-
-#define GPL0_AAAA      0x00000000
-#define GPL0_AAA0      0x00200000
-#define GPL0_AAA1      0x00300000
-#define GPL0_000A      0x00800000
-#define GPL0_0000      0x00A00000
-#define GPL0_0001      0x00B00000
-#define GPL0_111A      0x00C00000
-#define GPL0_1110      0x00E00000
-#define GPL0_1111      0x00F00000
-
-#define GPL1_0000      0x00000000
-#define GPL1_0001      0x00040000
-#define GPL1_1110      0x00080000
-#define GPL1_1111      0x000C0000
-
-#define GPL2_0000      0x00000000
-#define GPL2_0001      0x00010000
-#define GPL2_1110      0x00020000
-#define GPL2_1111      0x00030000
-
-#define GPL3_0000      0x00000000
-#define GPL3_0001      0x00004000
-#define GPL3_1110      0x00008000
-#define GPL3_1111      0x0000C000
-
-#define GPL4_0000      0x00000000
-#define GPL4_0001      0x00001000
-#define GPL4_1110      0x00002000
-#define GPL4_1111      0x00003000
-
-#define GPL5_0000      0x00000000
-#define GPL5_0001      0x00000400
-#define GPL5_1110      0x00000800
-#define GPL5_1111      0x00000C00
-#define LOOP           0x00000080
-
-#define EXEN           0x00000040
-
-#define AMX_COL                0x00000000
-#define AMX_ROW                0x00000020
-#define AMX_MAR                0x00000030
-
-#define NA             0x00000008
-
-#define UTA            0x00000004
-
-#define TODT           0x00000002
-
-#define LAST           0x00000001
-
-#define A10_AAAA       GPL0_AAAA
-#define A10_AAA0       GPL0_AAA0
-#define A10_AAA1       GPL0_AAA1
-#define A10_000A       GPL0_000A
-#define A10_0000       GPL0_0000
-#define A10_0001       GPL0_0001
-#define A10_111A       GPL0_111A
-#define A10_1110       GPL0_1110
-#define A10_1111       GPL0_1111
-
-#define RAS_0000       GPL1_0000
-#define RAS_0001       GPL1_0001
-#define RAS_1110       GPL1_1110
-#define RAS_1111       GPL1_1111
-
-#define CAS_0000       GPL2_0000
-#define CAS_0001       GPL2_0001
-#define CAS_1110       GPL2_1110
-#define CAS_1111       GPL2_1111
-
-#define WE_0000                GPL3_0000
-#define WE_0001                GPL3_0001
-#define WE_1110                GPL3_1110
-#define WE_1111                GPL3_1111
-
-/* #define CAS_LATENCY 3  */
-#define CAS_LATENCY    2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
-       /* RSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_,
-
-       /* RBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
-       /* RSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-       /* RBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-       _NOT_USED_,
-
-       /* WBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-#endif
-
-       /* UPT */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-       /* EXC */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
-       _NOT_USED_,
-
-       /* REG */
-       CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
-       CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-#if CONFIG_NETPHONE_VERSION == 2
-static const uint nandcs_table[0x40] = {
-       /* RSS */
-       CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_0000 | GPL5_1111,
-       CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
-       CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,   /* NOP   */
-
-       /* RBS */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_1111,
-       CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
-
-       /* WBS */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* UPT */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* EXC */
-       CS_0001 | LAST,
-       _NOT_USED_,
-
-       /* REG */
-       CS_1110 ,
-       CS_0001 | LAST,
-};
-#endif
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT         ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 8 */
-#define CONFIG_SYS_MAMR        ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
-       unsigned int i, j, v, vv;
-       volatile unsigned int *p;
-       unsigned int pv;
-
-       p = (unsigned int *)addr;
-       pv = (unsigned int)p;
-       for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
-               *p++ = pv;
-
-       p = (unsigned int *)addr;
-       for (i = 0; i < size / sizeof(unsigned int); i++) {
-               v = (unsigned int)p;
-               vv = *p;
-               if (vv != v) {
-                       printf("%p: read %08x instead of %08x\n", p, vv, v);
-                       hang();
-               }
-               p++;
-       }
-
-       for (j = 0; j < 5; j++) {
-               switch (j) {
-                       case 0: v = 0x00000000; break;
-                       case 1: v = 0xffffffff; break;
-                       case 2: v = 0x55555555; break;
-                       case 3: v = 0xaaaaaaaa; break;
-                       default:v = 0xdeadbeef; break;
-               }
-               p = (unsigned int *)addr;
-               for (i = 0; i < size / sizeof(unsigned int); i++) {
-                       *p = v;
-                       vv = *p;
-                       if (vv != v) {
-                               printf("%p: read %08x instead of %08x\n", p, vv, v);
-                               hang();
-                       }
-                       *p = ~v;
-                       p++;
-               }
-       }
-}
-
-phys_size_t initdram(int board_type)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size;
-
-       upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
-
-       /*
-        * Preliminary prescaler for refresh
-        */
-       memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
-       memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
-       /*
-        * Map controller bank 3 to the SDRAM bank at preliminary address.
-        */
-       memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-       memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
-       memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;       /* no refresh yet */
-
-       udelay(200);
-
-       /* perform SDRAM initialisation sequence */
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
-       udelay(1);
-
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
-       udelay(1);
-
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
-       udelay(1);
-
-       memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
-
-       udelay(10000);
-
-       {
-               u32 d1, d2;
-
-               d1 = 0xAA55AA55;
-               *(volatile u32 *)0 = d1;
-               d2 = *(volatile u32 *)0;
-               if (d1 != d2) {
-                       printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
-                       hang();
-               }
-
-               d1 = 0x55AA55AA;
-               *(volatile u32 *)0 = d1;
-               d2 = *(volatile u32 *)0;
-               if (d1 != d2) {
-                       printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
-                       hang();
-               }
-       }
-
-       size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
-       if (size == 0) {
-               printf("SIZE is zero: LOOP on 0\n");
-               for (;;) {
-                       *(volatile u32 *)0 = 0;
-                       (void)*(volatile u32 *)0;
-               }
-       }
-
-       return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phys(void)
-{
-       int phyno;
-       unsigned short v;
-
-       udelay(10000);
-       /* reset the damn phys */
-       mii_init();
-
-       for (phyno = 0; phyno < 32; ++phyno) {
-               fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
-               if (v == 0xFFFF)
-                       continue;
-               fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
-               udelay(10000);
-               fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
-                               BMCR_RESET | BMCR_ANENABLE);
-               udelay(10000);
-       }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK   0
-#define PA_GP_OUTMASK  (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
-#define PA_SP_MASK     0
-#define PA_ODR_VAL     0
-#define PA_GP_OUTVAL   (_BW(3) | _BW(14) | _BW(15))
-#define PA_SP_DIRVAL   0
-
-#define PB_GP_INMASK   _B(28)
-#define PB_GP_OUTMASK  (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_MASK     (_BR(22, 25))
-#define PB_ODR_VAL     0
-#define PB_GP_OUTVAL   (_B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_DIRVAL   0
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define PC_GP_INMASK   _BW(12)
-#define PC_GP_OUTMASK  (_BW(10) | _BW(11) | _BW(13) | _BW(15))
-#elif CONFIG_NETPHONE_VERSION == 2
-#define PC_GP_INMASK   (_BW(13) | _BW(15))
-#define PC_GP_OUTMASK  (_BW(10) | _BW(11) | _BW(12))
-#endif
-#define PC_SP_MASK     0
-#define PC_SOVAL       0
-#define PC_INTVAL      0
-#define PC_GP_OUTVAL   (_BW(10) | _BW(11))
-#define PC_SP_DIRVAL   0
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define PE_GP_INMASK   _B(31)
-#define PE_GP_OUTMASK  (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
-#define PE_GP_OUTVAL   (_B(20) | _B(24) | _B(27) | _B(28))
-#elif CONFIG_NETPHONE_VERSION == 2
-#define PE_GP_INMASK   _BR(28, 31)
-#define PE_GP_OUTMASK  (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
-#define PE_GP_OUTVAL   (_B(20) | _B(24) | _B(27))
-#endif
-#define PE_SP_MASK     0
-#define PE_ODR_VAL     0
-#define PE_SP_DIRVAL   0
-
-int board_early_init_f(void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile iop8xx_t *ioport = &immap->im_ioport;
-       volatile cpm8xx_t *cpm = &immap->im_cpm;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-       /* NAND chip select */
-#if CONFIG_NETPHONE_VERSION == 1
-       memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
-       memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-#elif CONFIG_NETPHONE_VERSION == 2
-       upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
-       memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
-       memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
-       memctl->memc_mamr = 0;  /* all clear */
-#endif
-
-       /* DSP chip select */
-       memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
-       memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
-#if CONFIG_NETPHONE_VERSION == 1
-       memctl->memc_br4 &= ~BR_V;
-#endif
-       memctl->memc_br5 &= ~BR_V;
-       memctl->memc_br6 &= ~BR_V;
-       memctl->memc_br7 &= ~BR_V;
-
-       ioport->iop_padat       = PA_GP_OUTVAL;
-       ioport->iop_paodr       = PA_ODR_VAL;
-       ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
-       ioport->iop_papar       = PA_SP_MASK;
-
-       cpm->cp_pbdat           = PB_GP_OUTVAL;
-       cpm->cp_pbodr           = PB_ODR_VAL;
-       cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
-       cpm->cp_pbpar           = PB_SP_MASK;
-
-       ioport->iop_pcdat       = PC_GP_OUTVAL;
-       ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
-       ioport->iop_pcso        = PC_SOVAL;
-       ioport->iop_pcint       = PC_INTVAL;
-       ioport->iop_pcpar       = PC_SP_MASK;
-
-       cpm->cp_pedat           = PE_GP_OUTVAL;
-       cpm->cp_peodr           = PE_ODR_VAL;
-       cpm->cp_pedir           = PE_GP_OUTMASK | PE_SP_DIRVAL;
-       cpm->cp_pepar           = PE_SP_MASK;
-
-       return 0;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
-       /* XXX add here the really funky stuff */
-}
-
-#endif
-
-#ifdef CONFIG_SHOW_ACTIVITY
-
-static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ;      /* poll */
-
-/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */
-void board_show_activity(ulong timestamp)
-{
-       if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
-               --left_to_poll;
-}
-
-extern void phone_console_do_poll(void);
-
-static void do_poll(void)
-{
-       unsigned int base;
-
-       while (left_to_poll <= 0) {
-               phone_console_do_poll();
-               base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
-               do {
-                       left_to_poll = base;
-               } while (base != left_to_poll);
-       }
-}
-
-/* called when looping */
-void show_activity(int arg)
-{
-       do_poll();
-}
-
-#endif
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
-       /* printf("overwrite_console called\n"); */
-       return 0;
-}
-#endif
-
-extern int drv_phone_init(void);
-extern int drv_phone_use_me(void);
-extern int drv_phone_is_idle(void);
-
-int misc_init_r(void)
-{
-       return drv_phone_init();
-}
-
-int last_stage_init(void)
-{
-       int i;
-
-#if CONFIG_NETPHONE_VERSION == 2
-       /* assert peripheral reset */
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
-       for (i = 0; i < 10; i++)
-               udelay(1000);
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
-#endif
-       reset_phys();
-
-       /* check in order to enable the local console */
-       left_to_poll = PHONE_CONSOLE_POLL_HZ;
-       i = CONFIG_SYS_HZ * 2;
-       while (i > 0) {
-
-               if (tstc()) {
-                       getc();
-                       break;
-               }
-
-               do_poll();
-
-               if (drv_phone_use_me()) {
-                       status_led_set(0, STATUS_LED_ON);
-                       while (!drv_phone_is_idle()) {
-                               do_poll();
-                               udelay(1000000 / CONFIG_SYS_HZ);
-                       }
-
-                       console_assign(stdin, "phone");
-                       console_assign(stdout, "phone");
-                       console_assign(stderr, "phone");
-                       setenv("bootdelay", "-1");
-                       break;
-               }
-
-               udelay(1000000 / CONFIG_SYS_HZ);
-               i--;
-               left_to_poll--;
-       }
-       left_to_poll = PHONE_CONSOLE_POLL_HZ;
-
-       return 0;
-}
diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c
deleted file mode 100644 (file)
index d195a39..0000000
+++ /dev/null
@@ -1,1128 +0,0 @@
-/*
- * (C) Copyright 2004 Intracom S.A.
- * Pantelis Antoniou <panto@intracom.gr>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * phone_console.c
- *
- * A phone based console
- *
- * Virtual display of 80x24 characters.
- * The actual display is much smaller and panned to show the virtual one.
- * Input is made by a numeric keypad utilizing the input method of
- * mobile phones. Sorry no T9 lexicons...
- *
- */
-
-#include <common.h>
-
-#include <version.h>
-#include <linux/types.h>
-#include <stdio_dev.h>
-
-#include <sed156x.h>
-
-/*************************************************************************************************/
-
-#define ROWS   24
-#define COLS   80
-
-#define REFRESH_HZ             (CONFIG_SYS_HZ/50)      /* refresh every 20ms */
-#define BLINK_HZ               (CONFIG_SYS_HZ/2)       /* cursor blink every 500ms */
-
-/*************************************************************************************************/
-
-#define DISPLAY_BACKLIT_PORT   ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat
-#define DISPLAY_BACKLIT_MASK   0x0010
-
-/*************************************************************************************************/
-
-#define KP_STABLE_HZ           (CONFIG_SYS_HZ/100)     /* stable for 10ms */
-#define KP_REPEAT_DELAY_HZ     (CONFIG_SYS_HZ/4)       /* delay before repeat 250ms */
-#define KP_REPEAT_HZ           (CONFIG_SYS_HZ/20)      /* repeat every 50ms */
-#define KP_FORCE_DELAY_HZ      (CONFIG_SYS_HZ/2)       /* key was force pressed */
-#define KP_IDLE_DELAY_HZ       (CONFIG_SYS_HZ/2)       /* key was released and idle */
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_RXD_MASK 0x0008
-
-#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_TXD_MASK 0x0004
-
-#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define KP_SPI_CLK_MASK 0x0001
-#elif CONFIG_NETPHONE_VERSION == 2
-#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_RXD_MASK 0x00000008
-
-#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_TXD_MASK 0x00000004
-
-#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define KP_SPI_CLK_MASK 0x00000002
-#endif
-
-#define KP_CS_PORT     (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat)
-#define KP_CS_MASK     0x00000010
-
-#define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK)
-
-#define KP_SPI_TXD(x) \
-       do { \
-               if (x) \
-                       KP_SPI_TXD_PORT |=  KP_SPI_TXD_MASK; \
-               else \
-                       KP_SPI_TXD_PORT &= ~KP_SPI_TXD_MASK; \
-       } while(0)
-
-#define KP_SPI_CLK(x) \
-       do { \
-               if (x) \
-                       KP_SPI_CLK_PORT |=  KP_SPI_CLK_MASK; \
-               else \
-                       KP_SPI_CLK_PORT &= ~KP_SPI_CLK_MASK; \
-       } while(0)
-
-#define KP_SPI_CLK_TOGGLE() (KP_SPI_CLK_PORT ^= KP_SPI_CLK_MASK)
-
-#define KP_SPI_BIT_DELAY()     /* no delay */
-
-#define KP_CS(x) \
-       do { \
-               if (x) \
-                       KP_CS_PORT |=  KP_CS_MASK; \
-               else \
-                       KP_CS_PORT &= ~KP_CS_MASK; \
-       } while(0)
-
-#define KP_ROWS 7
-#define KP_COLS 4
-
-#define KP_ROWS_MASK   ((1 << KP_ROWS) - 1)
-#define KP_COLS_MASK   ((1 << KP_COLS) - 1)
-
-#define SCAN           0
-#define SCAN_FILTER    1
-#define SCAN_COL       2
-#define SCAN_COL_FILTER 3
-#define PRESSED                4
-
-#define KP_F1  0       /* leftmost dot (tab)   */
-#define KP_F2  1       /* middle left dot      */
-#define KP_F3  2       /* up                   */
-#define KP_F4  3       /* middle right dot     */
-#define KP_F5  4       /* rightmost dot        */
-#define KP_F6  5       /* C                    */
-#define KP_F7  6       /* left                 */
-#define KP_F8  7       /* down                 */
-#define KP_F9  8       /* right                */
-#define KP_F10 9       /* enter                */
-#define KP_F11 10      /* R                    */
-#define KP_F12 11      /* save                 */
-#define KP_F13 12      /* redial               */
-#define KP_F14 13      /* speaker              */
-#define KP_F15 14      /* unused               */
-#define KP_F16 15      /* unused               */
-
-#define KP_RELEASE             -1      /* key depressed                                */
-#define KP_FORCE               -2      /* key was pressed for more than force hz       */
-#define KP_IDLE                        -3      /* key was released and idle                    */
-
-#define KP_1   '1'
-#define KP_2   '2'
-#define KP_3   '3'
-#define KP_4   '4'
-#define KP_5   '5'
-#define KP_6   '6'
-#define KP_7   '7'
-#define KP_8   '8'
-#define KP_9   '9'
-#define KP_0   '0'
-#define KP_STAR '*'
-#define KP_HASH '#'
-
-/*************************************************************************************************/
-
-static int curs_disabled;
-static int curs_col, curs_row;
-static int disp_col, disp_row;
-
-static int width, height;
-
-/* the simulated vty buffer */
-static char vty_buf[ROWS * COLS];
-static char last_visible_buf[ROWS * COLS];     /* worst case */
-static char *last_visible_curs_ptr;
-static int last_visible_curs_rev;
-static int blinked_state;
-static int last_input_mode;
-static int refresh_time;
-static int blink_time;
-static char last_fast_punct;
-
-/*************************************************************************************************/
-
-#define IM_SMALL       0
-#define IM_CAPITAL     1
-#define IM_NUMBER      2
-
-static int input_mode;
-static char fast_punct;
-static int tab_indicator;
-static const char *fast_punct_list = ",.:;*";
-
-static const char *input_mode_txt[] = { "abc", "ABC", "123" };
-
-static const char *punct = ".,!;?'\"-()@/:_+&%*=<>$[]{}\\~^#|";
-static const char *whspace = " 0\n";
-/* per mode character select (for 2-9) */
-static const char *digits_sel[2][8] = {
-       {       /* small */
-               "abc2",                                 /* 2 */
-               "def3",                                 /* 3 */
-               "ghi4",                                 /* 4 */
-               "jkl5",                                 /* 5 */
-               "mno6",                                 /* 6 */
-               "pqrs7",                                /* 7 */
-               "tuv8",                                 /* 8 */
-               "wxyz9",                                /* 9 */
-       }, {    /* capital */
-               "ABC2",                                 /* 2 */
-               "DEF3",                                 /* 3 */
-               "GHI4",                                 /* 4 */
-               "JKL5",                                 /* 5 */
-               "MNO6",                                 /* 6 */
-               "PQRS7",                                /* 7 */
-               "TUV8",                                 /* 8 */
-               "WXYZ9",                                /* 9 */
-       }
-};
-
-/*****************************************************************************/
-
-static void update(void);
-static void ensure_visible(int col, int row, int dx, int dy);
-
-static void console_init(void)
-{
-       curs_disabled = 0;
-       curs_col = 0;
-       curs_row = 0;
-
-       disp_col = 0;
-       disp_row = 0;
-
-       input_mode = IM_SMALL;
-       fast_punct = ',';
-       last_fast_punct = '\0';
-       refresh_time = REFRESH_HZ;
-       blink_time = BLINK_HZ;
-
-       memset(vty_buf, ' ', sizeof(vty_buf));
-
-       memset(last_visible_buf, ' ', sizeof(last_visible_buf));
-       last_visible_curs_ptr = NULL;
-       last_input_mode = -1;
-       last_visible_curs_rev = 0;
-
-       blinked_state = 0;
-
-       sed156x_init();
-       width = sed156x_text_width;
-       height = sed156x_text_height - 1;
-
-       tab_indicator = 0;
-}
-
-/*****************************************************************************/
-
-void phone_putc(const char c);
-
-/*****************************************************************************/
-
-static int  queued_char = -1;
-static int  enabled = 0;
-
-/*****************************************************************************/
-
-/* flush buffers */
-int phone_start(void)
-{
-       console_init();
-
-       update();
-       sed156x_sync();
-
-       enabled = 1;
-       queued_char = 'U' - '@';
-
-       /* backlit on */
-       DISPLAY_BACKLIT_PORT &= ~DISPLAY_BACKLIT_MASK;
-
-       return 0;
-}
-
-int phone_stop(void)
-{
-       enabled = 0;
-
-       sed156x_clear();
-       sed156x_sync();
-
-       /* backlit off */
-       DISPLAY_BACKLIT_PORT |= DISPLAY_BACKLIT_MASK;
-
-       return 0;
-}
-
-void phone_puts(const char *s)
-{
-       int count = strlen(s);
-
-       while (count--)
-               phone_putc(*s++);
-}
-
-int phone_tstc(void)
-{
-       return queued_char >= 0 ? 1 : 0;
-}
-
-int phone_getc(void)
-{
-       int r;
-
-       if (queued_char < 0)
-               return -1;
-
-       r = queued_char;
-       queued_char = -1;
-
-       return r;
-}
-
-/*****************************************************************************/
-
-int drv_phone_init(void)
-{
-       struct stdio_dev console_dev;
-
-       console_init();
-
-       memset(&console_dev, 0, sizeof(console_dev));
-       strcpy(console_dev.name, "phone");
-       console_dev.ext = DEV_EXT_VIDEO;        /* Video extensions */
-       console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
-       console_dev.start = phone_start;
-       console_dev.stop = phone_stop;
-       console_dev.putc = phone_putc;  /* 'putc' function */
-       console_dev.puts = phone_puts;  /* 'puts' function */
-       console_dev.tstc = phone_tstc;  /* 'tstc' function */
-       console_dev.getc = phone_getc;  /* 'getc' function */
-
-       if (stdio_register(&console_dev) == 0)
-               return 1;
-
-       return 0;
-}
-
-static int use_me;
-
-int drv_phone_use_me(void)
-{
-       return use_me;
-}
-
-static void kp_do_poll(void);
-
-void phone_console_do_poll(void)
-{
-       int i, x, y;
-
-       kp_do_poll();
-
-       if (enabled) {
-               /* do the blink */
-               blink_time -= PHONE_CONSOLE_POLL_HZ;
-               if (blink_time <= 0) {
-                       blink_time += BLINK_HZ;
-                       if (last_visible_curs_ptr) {
-                               i = last_visible_curs_ptr - last_visible_buf;
-                               x = i % width; y = i / width;
-                               sed156x_reverse_at(x, y, 1);
-                               last_visible_curs_rev ^= 1;
-                       }
-               }
-
-               /* do the refresh */
-               refresh_time -= PHONE_CONSOLE_POLL_HZ;
-               if (refresh_time <= 0) {
-                       refresh_time += REFRESH_HZ;
-                       sed156x_sync();
-               }
-       }
-
-}
-
-static int last_scancode = -1;
-static int forced_scancode = 0;
-static int input_state = -1;
-static int input_scancode = -1;
-static int input_selected_char = -1;
-static char input_covered_char;
-
-static void putchar_at_cursor(char c)
-{
-       vty_buf[curs_row * COLS + curs_col] = c;
-       ensure_visible(curs_col, curs_row, 1, 1);
-}
-
-static char getchar_at_cursor(void)
-{
-       return vty_buf[curs_row * COLS + curs_col];
-}
-
-static void queue_input_char(char c)
-{
-       if (c <= 0)
-               return;
-
-       queued_char = c;
-}
-
-static void terminate_input(void)
-{
-       if (input_state < 0)
-               return;
-
-       if (input_selected_char >= 0)
-               queue_input_char(input_selected_char);
-
-       input_state = -1;
-       input_selected_char = -1;
-       putchar_at_cursor(input_covered_char);
-
-       curs_disabled = 0;
-       blink_time = BLINK_HZ;
-       update();
-}
-
-static void handle_enabled_scancode(int scancode)
-{
-       char c;
-       int new_disp_col, new_disp_row;
-       const char *sel;
-
-
-       switch (scancode) {
-
-                       /* key was released */
-               case KP_RELEASE:
-                       forced_scancode = 0;
-                       break;
-
-                       /* key was forced */
-               case KP_FORCE:
-
-                       switch (last_scancode) {
-                               case '#':
-                                       if (input_mode == IM_NUMBER) {
-                                               input_mode = IM_CAPITAL;
-                                               /* queue backspace to erase # */
-                                               queue_input_char('\b');
-                                       } else {
-                                               input_mode = IM_NUMBER;
-                                               fast_punct = '*';
-                                       }
-                                       update();
-                                       break;
-
-                               case '0': case '1':
-                               case '2': case '3': case '4': case '5':
-                               case '6': case '7': case '8': case '9':
-
-                                       if (input_state < 0)
-                                               break;
-
-                                       input_selected_char = last_scancode;
-                                       putchar_at_cursor((char)input_selected_char);
-                                       terminate_input();
-
-                                       break;
-
-                               default:
-                                       break;
-                       }
-
-                       break;
-
-                       /* release and idle */
-               case KP_IDLE:
-                       input_scancode = -1;
-                       if (input_state < 0)
-                               break;
-                       terminate_input();
-                       break;
-
-                       /* change input mode */
-               case '#':
-                       if (last_scancode == '#')       /* no repeat */
-                               break;
-
-                       if (input_mode == IM_NUMBER) {
-                               input_scancode = scancode;
-                               input_state = 0;
-                               input_selected_char = scancode;
-                               input_covered_char = getchar_at_cursor();
-                               putchar_at_cursor((char)input_selected_char);
-                               terminate_input();
-                               break;
-                       }
-
-                       if (input_mode == IM_SMALL)
-                               input_mode = IM_CAPITAL;
-                       else
-                               input_mode = IM_SMALL;
-
-                       update();
-                       break;
-
-               case '*':
-                       /* no repeat */
-                       if (last_scancode == scancode)
-                               break;
-
-                       if (input_state >= 0)
-                               terminate_input();
-
-                       input_scancode = fast_punct;
-                       input_state = 0;
-                       input_selected_char = input_scancode;
-                       input_covered_char = getchar_at_cursor();
-                       putchar_at_cursor((char)input_selected_char);
-                       terminate_input();
-
-                       break;
-
-               case '0': case '1':
-               case '2': case '3': case '4': case '5':
-               case '6': case '7': case '8': case '9':
-
-                       /* no repeat */
-                       if (last_scancode == scancode)
-                               break;
-
-                       if (input_mode == IM_NUMBER) {
-                               input_scancode = scancode;
-                               input_state = 0;
-                               input_selected_char = scancode;
-                               input_covered_char = getchar_at_cursor();
-                               putchar_at_cursor((char)input_selected_char);
-                               terminate_input();
-                               break;
-                       }
-
-                       if (input_state >= 0 && input_scancode != scancode)
-                               terminate_input();
-
-                       if (input_state < 0) {
-                               curs_disabled = 1;
-                               input_scancode = scancode;
-                               input_state = 0;
-                               input_covered_char = getchar_at_cursor();
-                       } else
-                               input_state++;
-
-                       if (scancode == '0')
-                               sel = whspace;
-                       else if (scancode == '1')
-                               sel = punct;
-                       else
-                               sel = digits_sel[input_mode][scancode - '2'];
-                       c = *(sel + input_state);
-                       if (c == '\0') {
-                               input_state = 0;
-                               c = *sel;
-                       }
-
-                       input_selected_char = (int)c;
-                       putchar_at_cursor((char)input_selected_char);
-                       update();
-
-                       break;
-
-                       /* move visible display */
-               case KP_F3: case KP_F8: case KP_F7: case KP_F9:
-
-                       new_disp_col = disp_col;
-                       new_disp_row = disp_row;
-
-                       switch (scancode) {
-                                       /* up */
-                               case KP_F3:
-                                       if (new_disp_row <= 0)
-                                               break;
-                                       new_disp_row--;
-                                       break;
-
-                                       /* down */
-                               case KP_F8:
-                                       if (new_disp_row >= ROWS - height)
-                                               break;
-                                       new_disp_row++;
-                                       break;
-
-                                       /* left */
-                               case KP_F7:
-                                       if (new_disp_col <= 0)
-                                               break;
-                                       new_disp_col--;
-                                       break;
-
-                                       /* right */
-                               case KP_F9:
-                                       if (new_disp_col >= COLS - width)
-                                               break;
-                                       new_disp_col++;
-                                       break;
-                       }
-
-                       /* no change? */
-                       if (disp_col == new_disp_col && disp_row == new_disp_row)
-                               break;
-
-                       disp_col = new_disp_col;
-                       disp_row = new_disp_row;
-                       update();
-
-                       break;
-
-               case KP_F6:     /* backspace */
-                       /* inputing something; no backspace sent, just cancel input */
-                       if (input_state >= 0) {
-                               input_selected_char = -1;       /* cancel */
-                               terminate_input();
-                               break;
-                       }
-                       queue_input_char('\b');
-                       break;
-
-               case KP_F10:    /* enter */
-                       /* inputing something; first cancel input */
-                       if (input_state >= 0)
-                               terminate_input();
-                       queue_input_char('\r');
-                       break;
-
-               case KP_F11:    /* R -> Ctrl-C (abort) */
-                       if (input_state >= 0)
-                               terminate_input();
-                       queue_input_char('C' - 'Q');    /* ctrl-c */
-                       break;
-
-               case KP_F5:     /* F% -> Ctrl-U (clear line) */
-                       if (input_state >= 0)
-                               terminate_input();
-                       queue_input_char('U' - 'Q');    /* ctrl-c */
-                       break;
-
-
-               case KP_F1:     /* tab */
-                       /* inputing something; first cancel input */
-                       if (input_state >= 0)
-                               terminate_input();
-                       queue_input_char('\t');
-                       break;
-
-               case KP_F2:     /* change fast punct */
-                       sel = strchr(fast_punct_list, fast_punct);
-                       if (sel == NULL)
-                               sel = &fast_punct_list[0];
-                       sel++;
-                       if (*sel == '\0')
-                               sel = &fast_punct_list[0];
-                       fast_punct = *sel;
-                       update();
-                       break;
-
-
-       }
-
-       if (scancode != KP_FORCE && scancode != KP_IDLE)        /* don't record forced or idle scancode */
-               last_scancode = scancode;
-}
-
-static void scancode_action(int scancode)
-{
-#if 0
-       if (scancode == KP_RELEASE)
-               printf(" RELEASE\n");
-       else if (scancode == KP_FORCE)
-               printf(" FORCE\n");
-       else if (scancode == KP_IDLE)
-               printf(" IDLE\n");
-       else if (scancode < 32)
-               printf(" F%d", scancode + 1);
-       else
-               printf(" %c", (char)scancode);
-       printf("\n");
-#endif
-
-       if (enabled) {
-               handle_enabled_scancode(scancode);
-               return;
-       }
-
-       if (scancode == KP_FORCE && last_scancode == '*')
-               use_me = 1;
-
-       last_scancode = scancode;
-}
-
-/**************************************************************************************/
-
-/* update the display; make sure to update only the differences */
-static void update(void)
-{
-       int i;
-       char *s, *e, *t, *r, *b, *cp;
-
-       if (input_mode != last_input_mode)
-               sed156x_output_at(sed156x_text_width - 3, sed156x_text_height - 1, input_mode_txt[input_mode], 3);
-
-       if (tab_indicator == 0) {
-               sed156x_output_at(0, sed156x_text_height - 1, "\\t", 2);
-               tab_indicator = 1;
-       }
-
-       if (fast_punct != last_fast_punct)
-               sed156x_output_at(4, sed156x_text_height - 1, &fast_punct, 1);
-
-       if (curs_disabled ||
-               curs_col < disp_col || curs_col >= (disp_col + width) ||
-               curs_row < disp_row || curs_row >= (disp_row + height)) {
-               cp = NULL;
-       } else
-               cp = last_visible_buf + (curs_row - disp_row) * width + (curs_col - disp_col);
-
-
-       /* printf("(%d,%d) (%d,%d) %s\n", curs_col, curs_row, disp_col, disp_row, cp ? "YES" : "no"); */
-
-       /* clear previous cursor */
-       if (last_visible_curs_ptr && last_visible_curs_rev == 0) {
-               i = last_visible_curs_ptr - last_visible_buf;
-               sed156x_reverse_at(i % width, i / width, 1);
-       }
-
-       b = vty_buf + disp_row * COLS + disp_col;
-       t = last_visible_buf;
-       for (i = 0; i < height; i++) {
-               s = b;
-               e = b + width;
-               /* update only the differences */
-               do {
-                       while (s < e && *s == *t) {
-                               s++;
-                               t++;
-                       }
-                       if (s == e)     /* no more */
-                               break;
-
-                       /* find run */
-                       r = s;
-                       while (s < e && *s != *t)
-                               *t++ = *s++;
-
-                       /* and update */
-                       sed156x_output_at(r - b, i, r, s - r);
-
-               } while (s < e);
-
-               b += COLS;
-       }
-
-       /* set cursor */
-       if (cp) {
-               last_visible_curs_ptr = cp;
-               i = last_visible_curs_ptr - last_visible_buf;
-               sed156x_reverse_at(i % width, i / width, 1);
-               last_visible_curs_rev = 0;
-       } else {
-               last_visible_curs_ptr = NULL;
-       }
-
-       last_input_mode = input_mode;
-       last_fast_punct = fast_punct;
-}
-
-/* ensure visibility; the trick is to minimize the screen movement */
-static void ensure_visible(int col, int row, int dx, int dy)
-{
-       int x1, y1, x2, y2, a1, b1, a2, b2;
-
-       /* clamp visible region */
-       if (col < 0) {
-               dx -= col;
-               col = 0;
-               if (dx <= 0)
-                       dx = 1;
-       }
-
-       if (row < 0) {
-               dy -= row;
-               row = 0;
-               if (dy <= 0)
-                       dy = 1;
-       }
-
-       if (col + dx > COLS)
-               dx = COLS - col;
-
-       if (row + dy > ROWS)
-               dy = ROWS - row;
-
-
-       /* move to easier to use vars */
-       x1 = disp_col;   y1 = disp_row;
-       x2 = x1 + width; y2 = y1 + height;
-       a1 = col;        b1 = row;
-       a2 = a1 + dx;    b2 = b1 + dy;
-
-       /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
-
-       if (a2 > x2) {
-               /* move to the right */
-               x2 = a2;
-               x1 = x2 - width;
-               if (x1 < 0) {
-                       x1 = 0;
-                       x2 = width;
-               }
-       } else if (a1 < x1) {
-               /* move to the left */
-               x1 = a1;
-               x2 = x1 + width;
-               if (x2 > COLS) {
-                       x2 = COLS;
-                       x1 = x2 - width;
-               }
-       }
-
-       if (b2 > y2) {
-               /* move down */
-               y2 = b2;
-               y1 = y2 - height;
-               if (y1 < 0) {
-                       y1 = 0;
-                       y2 = height;
-               }
-       } else if (b1 < y1) {
-               /* move up */
-               y1 = b1;
-               y2 = y1 + width;
-               if (y2 > ROWS) {
-                       y2 = ROWS;
-                       y1 = y2 - height;
-               }
-       }
-
-       /* printf("(%d,%d) - (%d,%d) : (%d, %d) - (%d, %d)\n", x1, y1, x2, y2, a1, b1, a2, b2); */
-
-       /* no movement? */
-       if (disp_col == x1 && disp_row == y1)
-               return;
-
-       disp_col = x1;
-       disp_row = y1;
-}
-
-/**************************************************************************************/
-
-static void newline(void)
-{
-       curs_col = 0;
-       if (curs_row + 1 < ROWS)
-               curs_row++;
-       else {
-               memmove(vty_buf, vty_buf + COLS, COLS * (ROWS - 1));
-               memset(vty_buf + (ROWS - 1) * COLS, ' ', COLS);
-       }
-}
-
-void phone_putc(const char c)
-{
-       int i;
-
-       if (input_mode != -1) {
-               input_selected_char = -1;
-               terminate_input();
-       }
-
-       curs_disabled = 1;
-       update();
-
-       blink_time = BLINK_HZ;
-
-       switch (c) {
-               case '\a':              /* ignore bell            */
-               case '\r':              /* ignore carriage return */
-                       break;
-
-               case '\n':              /* next line */
-                       newline();
-                       ensure_visible(curs_col, curs_row, 1, 1);
-                       break;
-
-               case 9: /* tab 8 */
-                       /* move to tab */
-                       i = curs_col;
-                       i |=  0x0008;
-                       i &= ~0x0007;
-
-                       if (i < COLS)
-                               curs_col = i;
-                       else
-                               newline();
-
-                       ensure_visible(curs_col, curs_row, 1, 1);
-                       break;
-
-               case 8:         /* backspace */
-                       if (curs_col <= 0)
-                               break;
-                       curs_col--;
-
-                       /* make sure that we see a couple of characters before */
-                       if (curs_col > 4)
-                               ensure_visible(curs_col - 4, curs_row, 4, 1);
-                       else
-                               ensure_visible(curs_col, curs_row, 1, 1);
-
-                       break;
-
-               default:                /* draw the char */
-                       putchar_at_cursor(c);
-
-                       /*
-                        * check for newline
-                        */
-                       if (curs_col + 1 < COLS)
-                               curs_col++;
-                       else
-                               newline();
-
-                       ensure_visible(curs_col, curs_row, 1, 1);
-
-                       break;
-       }
-
-       curs_disabled = 0;
-       blink_time = BLINK_HZ;
-       update();
-}
-
-/**************************************************************************************/
-
-static inline unsigned int kp_transfer(unsigned int val)
-{
-       unsigned int rx;
-       int b;
-
-       rx = 0; b = 8;
-       while (--b >= 0) {
-               KP_SPI_TXD(val & 0x80);
-               val <<= 1;
-               KP_SPI_CLK_TOGGLE();
-               KP_SPI_BIT_DELAY();
-               rx <<= 1;
-               if (KP_SPI_RXD())
-                       rx |= 1;
-               KP_SPI_CLK_TOGGLE();
-               KP_SPI_BIT_DELAY();
-       }
-
-       return rx;
-}
-
-unsigned int kp_data_transfer(unsigned int val)
-{
-       KP_SPI_CLK(1);
-       KP_CS(0);
-       val = kp_transfer(val);
-       KP_CS(1);
-
-       return val;
-}
-
-unsigned int kp_get_col_mask(unsigned int row_mask)
-{
-       unsigned int val, col_mask;
-
-       val = 0x80 | (row_mask & 0x7F);
-       (void)kp_data_transfer(val);
-#if CONFIG_NETPHONE_VERSION == 1
-       col_mask = kp_data_transfer(val) & 0x0F;
-#elif CONFIG_NETPHONE_VERSION == 2
-       col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f;
-       /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */
-       col_mask = ((col_mask & 0x08) >> 3) |   /* BKBR1 */
-                  ((col_mask & 0x04) << 1) |   /* BKBR2 */
-                   (col_mask & 0x02) |         /* BKBR3 */
-                  ((col_mask & 0x01) << 2);    /* BKBR4 */
-
-#endif
-       /* printf("col_mask(row_mask = 0x%x) -> col_mask = 0x%x\n", row_mask, col_mask); */
-
-       return col_mask;
-}
-
-/**************************************************************************************/
-
-static const int kp_scancodes[KP_ROWS * KP_COLS] = {
-       KP_F1,   KP_F3,   KP_F4,  KP_F2,
-       KP_F6,   KP_F8,   KP_F9,  KP_F7,
-       KP_1,    KP_3,    KP_F11, KP_2,
-       KP_4,    KP_6,    KP_F12, KP_5,
-       KP_7,    KP_9,    KP_F13, KP_8,
-       KP_STAR, KP_HASH, KP_F14, KP_0,
-       KP_F5,   KP_F15,  KP_F16, KP_F10,
-};
-
-static const int kp_repeats[KP_ROWS * KP_COLS] = {
-       0, 1, 0, 0,
-       0, 1, 1, 1,
-       1, 1, 0, 1,
-       1, 1, 0, 1,
-       1, 1, 0, 1,
-       1, 1, 0, 1,
-       0, 0, 0, 1,
-};
-
-static int kp_state = SCAN;
-static int kp_last_col_mask;
-static int kp_cur_row, kp_cur_col;
-static int kp_scancode;
-static int kp_stable;
-static int kp_repeat;
-static int kp_repeat_time;
-static int kp_force_time;
-static int kp_idle_time;
-
-static void kp_do_poll(void)
-{
-       unsigned int col_mask;
-       int col;
-
-       switch (kp_state) {
-               case SCAN:
-                       if (kp_idle_time > 0) {
-                               kp_idle_time -= PHONE_CONSOLE_POLL_HZ;
-                               if (kp_idle_time <= 0)
-                                       scancode_action(KP_IDLE);
-                       }
-
-                       col_mask = kp_get_col_mask(KP_ROWS_MASK);
-                       if (col_mask == KP_COLS_MASK)
-                               break;  /* nothing */
-                       kp_last_col_mask = col_mask;
-                       kp_stable = 0;
-                       kp_state = SCAN_FILTER;
-                       break;
-
-               case SCAN_FILTER:
-                       col_mask = kp_get_col_mask(KP_ROWS_MASK);
-                       if (col_mask != kp_last_col_mask) {
-                               kp_state = SCAN;
-                               break;
-                       }
-
-                       kp_stable += PHONE_CONSOLE_POLL_HZ;
-                       if (kp_stable < KP_STABLE_HZ)
-                               break;
-
-                       kp_cur_row = 0;
-                       kp_stable = 0;
-                       kp_state = SCAN_COL;
-
-                       (void)kp_get_col_mask(1 << kp_cur_row);
-                       break;
-
-               case SCAN_COL:
-                       col_mask = kp_get_col_mask(1 << kp_cur_row);
-                       if (col_mask == KP_COLS_MASK) {
-                               if (++kp_cur_row >= KP_ROWS) {
-                                       kp_state = SCAN;
-                                       break;
-                               }
-                               kp_get_col_mask(1 << kp_cur_row);
-                               break;
-                       }
-                       kp_last_col_mask = col_mask;
-                       kp_stable = 0;
-                       kp_state = SCAN_COL_FILTER;
-                       break;
-
-               case SCAN_COL_FILTER:
-                       col_mask = kp_get_col_mask(1 << kp_cur_row);
-                       if (col_mask != kp_last_col_mask || col_mask == KP_COLS_MASK) {
-                               kp_state = SCAN;
-                               break;
-                       }
-
-                       kp_stable += PHONE_CONSOLE_POLL_HZ;
-                       if (kp_stable < KP_STABLE_HZ)
-                               break;
-
-                       for (col = 0; col < KP_COLS; col++)
-                               if ((col_mask & (1 << col)) == 0)
-                                       break;
-                       kp_cur_col = col;
-                       kp_state = PRESSED;
-                       kp_scancode = kp_scancodes[kp_cur_row * KP_COLS + kp_cur_col];
-                       kp_repeat = kp_repeats[kp_cur_row * KP_COLS + kp_cur_col];
-
-                       if (kp_repeat)
-                               kp_repeat_time = KP_REPEAT_DELAY_HZ;
-                       kp_force_time = KP_FORCE_DELAY_HZ;
-
-                       scancode_action(kp_scancode);
-
-                       break;
-
-               case PRESSED:
-                       col_mask = kp_get_col_mask(1 << kp_cur_row);
-                       if (col_mask != kp_last_col_mask) {
-                               kp_state = SCAN;
-                               scancode_action(KP_RELEASE);
-                               kp_idle_time = KP_IDLE_DELAY_HZ;
-                               break;
-                       }
-
-                       if (kp_repeat) {
-                               kp_repeat_time -= PHONE_CONSOLE_POLL_HZ;
-                               if (kp_repeat_time <= 0) {
-                                       kp_repeat_time += KP_REPEAT_HZ;
-                                       scancode_action(kp_scancode);
-                               }
-                       }
-
-                       if (kp_force_time > 0) {
-                               kp_force_time -= PHONE_CONSOLE_POLL_HZ;
-                               if (kp_force_time <= 0)
-                                       scancode_action(KP_FORCE);
-                       }
-
-                       break;
-       }
-}
-
-/**************************************************************************************/
-
-int drv_phone_is_idle(void)
-{
-       return kp_state == SCAN;
-}
diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds
deleted file mode 100644 (file)
index 0dff5a4..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text        :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o    (.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o    (.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug
deleted file mode 100644 (file)
index a198cf9..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)          }
-  .dynsym        : { *(.dynsym)                }
-  .dynstr        : { *(.dynstr)                }
-  .rel.text      : { *(.rel.text)              }
-  .rela.text     : { *(.rela.text)     }
-  .rel.data      : { *(.rel.data)              }
-  .rela.data     : { *(.rela.data)     }
-  .rel.rodata    : { *(.rel.rodata)    }
-  .rela.rodata   : { *(.rela.rodata)   }
-  .rel.got       : { *(.rel.got)               }
-  .rela.got      : { *(.rela.got)              }
-  .rel.ctors     : { *(.rel.ctors)     }
-  .rela.ctors    : { *(.rela.ctors)    }
-  .rel.dtors     : { *(.rel.dtors)     }
-  .rela.dtors    : { *(.rela.dtors)    }
-  .rel.bss       : { *(.rel.bss)               }
-  .rela.bss      : { *(.rela.bss)              }
-  .rel.plt       : { *(.rel.plt)               }
-  .rela.plt      : { *(.rela.plt)              }
-  .init          : { *(.init)  }
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within */
-    /* the sector layout of our flash chips!   XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc8xx/start.o            (.text)
-    common/dlmalloc.o          (.text)
-    lib/vsprintf.o     (.text)
-    lib/crc32.o                (.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/netta/Makefile b/board/netta/Makefile
deleted file mode 100644 (file)
index 98bac7e..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = netta.o flash.o dsp.o codec.o pcmcia.o
diff --git a/board/netta/codec.c b/board/netta/codec.c
deleted file mode 100644 (file)
index e303aa4..0000000
+++ /dev/null
@@ -1,1481 +0,0 @@
-/*
- * CODEC
- */
-
-#include <common.h>
-#include <post.h>
-
-#include "mpc8xx.h"
-
-/***********************************************/
-
-#define MAX_DUSLIC     4
-
-#define NUM_CHANNELS   2
-#define MAX_SLICS      (MAX_DUSLIC * NUM_CHANNELS)
-
-/***********************************************/
-
-#define SOP_READ_CH_0          0xC4  /* Read SOP Register for Channel A  */
-#define SOP_READ_CH_1          0xCC  /* Read SOP Register for Channel B  */
-#define SOP_WRITE_CH_0         0x44  /* Write SOP Register for Channel A */
-#define SOP_WRITE_CH_1         0x4C  /* Write SOP Register for Channel B */
-
-#define COP_READ_CH_0          0xC5
-#define COP_READ_CH_1          0xCD
-#define COP_WRITE_CH_0         0x45
-#define COP_WRITE_CH_1         0x4D
-
-#define POP_READ_CH_0          0xC6
-#define POP_READ_CH_1          0xCE
-#define POP_WRITE_CH_0         0x46
-#define POP_WRITE_CH_1         0x4E
-
-#define RST_CMD_DUSLIC_CHIP    0x40  /* OR 0x48 */
-#define RST_CMD_DUSLIC_CH_A    0x41
-#define RST_CMD_DUSLIC_CH_B    0x49
-
-#define PCM_RESYNC_CMD_CH_A    0x42
-#define PCM_RESYNC_CMD_CH_B    0x4A
-
-#define ACTIVE_HOOK_LEV_4      0
-#define ACTIVE_HOOK_LEV_12     1
-
-#define SLIC_P_NORMAL          0x01
-
-/************************************************/
-
-#define CODSP_WR       0x00
-#define CODSP_RD       0x80
-#define CODSP_OP       0x40
-#define CODSP_ADR(x)   (((unsigned char)(x) & 7) << 3)
-#define CODSP_M(x)     ((unsigned char)(x) & 7)
-#define CODSP_CMD(x)   ((unsigned char)(x) & 7)
-
-/************************************************/
-
-/* command indication ops */
-#define CODSP_M_SLEEP_PWRDN    7
-#define CODSP_M_PWRDN_HIZ      0
-#define CODSP_M_ANY_ACT                2
-#define CODSP_M_RING           5
-#define CODSP_M_ACT_MET                6
-#define CODSP_M_GND_START      4
-#define CODSP_M_RING_PAUSE     1
-
-/* single byte commands */
-#define CODSP_CMD_SOFT_RESET   CODSP_CMD(0)
-#define CODSP_CMD_RESET_CH     CODSP_CMD(1)
-#define CODSP_CMD_RESYNC       CODSP_CMD(2)
-
-/* two byte commands */
-#define CODSP_CMD_SOP          CODSP_CMD(4)
-#define CODSP_CMD_COP          CODSP_CMD(5)
-#define CODSP_CMD_POP          CODSP_CMD(6)
-
-/************************************************/
-
-/* read as 4-bytes */
-#define CODSP_INTREG_INT_CH    0x80000000
-#define CODSP_INTREG_HOOK      0x40000000
-#define CODSP_INTREG_GNDK      0x20000000
-#define CODSP_INTREG_GNDP      0x10000000
-#define CODSP_INTREG_ICON      0x08000000
-#define CODSP_INTREG_VRTLIM    0x04000000
-#define CODSP_INTREG_OTEMP     0x02000000
-#define CODSP_INTREG_SYNC_FAIL 0x01000000
-#define CODSP_INTREG_LM_THRES  0x00800000
-#define CODSP_INTREG_READY     0x00400000
-#define CODSP_INTREG_RSTAT     0x00200000
-#define CODSP_INTREG_LM_OK     0x00100000
-#define CODSP_INTREG_IO4_DU    0x00080000
-#define CODSP_INTREG_IO3_DU    0x00040000
-#define CODSP_INTREG_IO2_DU    0x00020000
-#define CODSP_INTREG_IO1_DU    0x00010000
-#define CODSP_INTREG_DTMF_OK   0x00008000
-#define CODSP_INTREG_DTMF_KEY4 0x00004000
-#define CODSP_INTREG_DTMF_KEY3 0x00002000
-#define CODSP_INTREG_DTMF_KEY2 0x00001000
-#define CODSP_INTREG_DTMF_KEY1 0x00000800
-#define CODSP_INTREG_DTMF_KEY0 0x00000400
-#define CODSP_INTREG_UTDR_OK   0x00000200
-#define CODSP_INTREG_UTDX_OK   0x00000100
-#define CODSP_INTREG_EDSP_FAIL 0x00000080
-#define CODSP_INTREG_CIS_BOF   0x00000008
-#define CODSP_INTREG_CIS_BUF   0x00000004
-#define CODSP_INTREG_CIS_REQ   0x00000002
-#define CODSP_INTREG_CIS_ACT   0x00000001
-
-/************************************************/
-
-/* ======== SOP REG ADDRESSES =======*/
-
-#define REVISION_ADDR          0x00
-#define PCMC1_ADDR             0x05
-#define XCR_ADDR               0x06
-#define INTREG1_ADDR           0x07
-#define INTREG2_ADDR           0x08
-#define INTREG3_ADDR           0x09
-#define INTREG4_ADDR           0x0A
-#define LMRES1_ADDR            0x0D
-#define MASK_ADDR              0x11
-#define IOCTL3_ADDR            0x14
-#define BCR1_ADDR              0x15
-#define BCR2_ADDR              0x16
-#define BCR3_ADDR              0x17
-#define BCR4_ADDR              0x18
-#define BCR5_ADDR              0x19
-#define DSCR_ADDR              0x1A
-#define LMCR1_ADDR             0x1C
-#define LMCR2_ADDR             0x1D
-#define LMCR3_ADDR             0x1E
-#define OFR1_ADDR              0x1F
-#define PCMR1_ADDR             0x21
-#define PCMX1_ADDR             0x25
-#define TSTR3_ADDR             0x2B
-#define TSTR4_ADDR             0x2C
-#define TSTR5_ADDR             0x2D
-
-/* ========= POP REG ADDRESSES ========*/
-
-#define CIS_DAT_ADDR           0x00
-
-#define LEC_LEN_ADDR           0x3A
-#define LEC_POWR_ADDR          0x3B
-#define LEC_DELP_ADDR          0x3C
-#define LEC_DELQ_ADDR          0x3D
-#define LEC_GAIN_XI_ADDR       0x3E
-#define LEC_GAIN_RI_ADDR       0x3F
-#define LEC_GAIN_XO_ADDR       0x40
-#define LEC_RES_1_ADDR         0x41
-#define LEC_RES_2_ADDR         0x42
-
-#define NLP_POW_LPF_ADDR       0x30
-#define NLP_POW_LPS_ADDR       0x31
-#define NLP_BN_LEV_X_ADDR      0x32
-#define NLP_BN_LEV_R_ADDR      0x33
-#define NLP_BN_INC_ADDR                0x34
-#define NLP_BN_DEC_ADDR                0x35
-#define NLP_BN_MAX_ADDR                0x36
-#define NLP_BN_ADJ_ADDR                0x37
-#define NLP_RE_MIN_ERLL_ADDR   0x38
-#define NLP_RE_EST_ERLL_ADDR   0x39
-#define NLP_SD_LEV_X_ADDR      0x3A
-#define NLP_SD_LEV_R_ADDR      0x3B
-#define NLP_SD_LEV_BN_ADDR     0x3C
-#define NLP_SD_LEV_RE_ADDR     0x3D
-#define NLP_SD_OT_DT_ADDR      0x3E
-#define NLP_ERL_LIN_LP_ADDR    0x3F
-#define NLP_ERL_LEC_LP_ADDR    0x40
-#define NLP_CT_LEV_RE_ADDR     0x41
-#define NLP_CTRL_ADDR          0x42
-
-#define UTD_CF_H_ADDR          0x4B
-#define UTD_CF_L_ADDR          0x4C
-#define UTD_BW_H_ADDR          0x4D
-#define UTD_BW_L_ADDR          0x4E
-#define UTD_NLEV_ADDR          0x4F
-#define UTD_SLEV_H_ADDR                0x50
-#define UTD_SLEV_L_ADDR                0x51
-#define UTD_DELT_ADDR          0x52
-#define UTD_RBRK_ADDR          0x53
-#define UTD_RTIME_ADDR         0x54
-#define UTD_EBRK_ADDR          0x55
-#define UTD_ETIME_ADDR         0x56
-
-#define DTMF_LEV_ADDR          0x30
-#define DTMF_TWI_ADDR          0x31
-#define DTMF_NCF_H_ADDR                0x32
-#define DTMF_NCF_L_ADDR                0x33
-#define DTMF_NBW_H_ADDR                0x34
-#define DTMF_NBW_L_ADDR                0x35
-#define DTMF_GAIN_ADDR         0x36
-#define DTMF_RES1_ADDR         0x37
-#define DTMF_RES2_ADDR         0x38
-#define DTMF_RES3_ADDR         0x39
-
-#define CIS_LEV_H_ADDR         0x43
-#define CIS_LEV_L_ADDR         0x44
-#define CIS_BRS_ADDR           0x45
-#define CIS_SEIZ_H_ADDR                0x46
-#define CIS_SEIZ_L_ADDR                0x47
-#define CIS_MARK_H_ADDR                0x48
-#define CIS_MARK_L_ADDR                0x49
-#define CIS_LEC_MODE_ADDR      0x4A
-
-/*=====================================*/
-
-#define HOOK_LEV_ACT_START_ADDR 0x89
-#define RO1_START_ADDR         0x70
-#define RO2_START_ADDR         0x95
-#define RO3_START_ADDR         0x96
-
-#define TG1_FREQ_START_ADDR    0x38
-#define TG1_GAIN_START_ADDR    0x39
-#define TG1_BANDPASS_START_ADDR 0x3B
-#define TG1_BANDPASS_END_ADDR  0x3D
-
-#define TG2_FREQ_START_ADDR    0x40
-#define TG2_GAIN_START_ADDR    0x41
-#define TG2_BANDPASS_START_ADDR 0x43
-#define TG2_BANDPASS_END_ADDR  0x45
-
-/*====================================*/
-
-#define PCM_HW_B               0x80
-#define PCM_HW_A               0x00
-#define PCM_TIME_SLOT_0                0x00   /*  Byte 0 of PCM Frame (by default is assigned to channel A ) */
-#define PCM_TIME_SLOT_1                0x01   /*  Byte 1 of PCM Frame (by default is assigned to channel B ) */
-#define PCM_TIME_SLOT_4                0x04   /*  Byte 4 of PCM Frame (Corresponds to B1 of the Second GCI ) */
-
-#define         RX_LEV_ADDR    0x28
-#define         TX_LEV_ADDR    0x30
-#define         Ik1_ADDR       0x83
-
-#define         AR_ROW         3 /* Is the row (AR Params) of the ac_Coeff array in SMS_CODEC_Defaults struct  */
-#define         AX_ROW         6 /* Is the row (AX Params) of the ac_Coeff array in SMS_CODEC_Defaults struct  */
-#define         DCF_ROW        0 /* Is the row (DCF Params) of the dc_Coeff array in SMS_CODEC_Defaults struct */
-
-/* Mark the start byte of Duslic parameters that we use with configurator */
-#define         Ik1_START_BYTE         3
-#define         RX_LEV_START_BYTE      0
-#define         TX_LEV_START_BYTE      0
-
-/************************************************/
-
-#define INTREG4_CIS_ACT                (1 << 0)
-
-#define BCR1_SLEEP             0x20
-#define BCR1_REVPOL            0x10
-#define BCR1_ACTR              0x08
-#define BCR1_ACTL              0x04
-#define BCR1_SLIC_MASK         0x03
-
-#define BCR2_HARD_POL_REV      0x40
-#define BCR2_TTX               0x20
-#define BCR2_TTX_12K           0x10
-#define BCR2_HIMAN             0x08
-#define BCR2_PDOT              0x01
-
-#define BCR3_PCMX_EN           (1 << 4)
-
-#define BCR5_DTMF_EN           (1 << 0)
-#define BCR5_DTMF_SRC          (1 << 1)
-#define BCR5_LEC_EN            (1 << 2)
-#define BCR5_LEC_OUT           (1 << 3)
-#define BCR5_CIS_EN            (1 << 4)
-#define BCR5_CIS_AUTO          (1 << 5)
-#define BCR5_UTDX_EN           (1 << 6)
-#define BCR5_UTDR_EN           (1 << 7)
-
-#define DSCR_TG1_EN            (1 << 0)
-#define DSCR_TG2_EN            (1 << 1)
-#define DSCR_PTG               (1 << 2)
-#define DSCR_COR8              (1 << 3)
-#define DSCR_DG_KEY(x)         (((x) & 0x0F) << 4)
-
-#define CIS_LEC_MODE_CIS_V23   (1 << 0)
-#define CIS_LEC_MODE_CIS_FRM   (1 << 1)
-#define CIS_LEC_MODE_NLP_EN    (1 << 2)
-#define CIS_LEC_MODE_UTDR_SUM  (1 << 4)
-#define CIS_LEC_MODE_UTDX_SUM  (1 << 5)
-#define CIS_LEC_MODE_LEC_FREEZE (1 << 6)
-#define CIS_LEC_MODE_LEC_ADAPT (1 << 7)
-
-#define TSTR4_COR_64           (1 << 5)
-
-#define TSTR3_AC_DLB_8K                (1 << 2)
-#define TSTR3_AC_DLB_32K       (1 << 3)
-#define TSTR3_AC_DLB_4M                (1 << 5)
-
-
-#define LMCR1_TEST_EN          (1 << 7)
-#define LMCR1_LM_EN            (1 << 6)
-#define LMCR1_LM_THM           (1 << 5)
-#define LMCR1_LM_ONCE          (1 << 2)
-#define LMCR1_LM_MASK          (1 << 1)
-
-#define LMCR2_LM_RECT                  (1 << 5)
-#define LMCR2_LM_SEL_VDD               0x0D
-#define LMCR2_LM_SEL_IO3               0x0A
-#define LMCR2_LM_SEL_IO4               0x0B
-#define LMCR2_LM_SEL_IO4_MINUS_IO3     0x0F
-
-#define LMCR3_RTR_SEL          (1 << 6)
-
-#define LMCR3_RNG_OFFSET_NONE  0x00
-#define LMCR3_RNG_OFFSET_1     0x01
-#define LMCR3_RNG_OFFSET_2     0x02
-#define LMCR3_RNG_OFFSET_3     0x03
-
-#define TSTR5_DC_HOLD          (1 << 3)
-
-/************************************************/
-
-#define TARGET_ONHOOK_BATH_x100                4600    /* 46.0 Volt */
-#define TARGET_ONHOOK_BATL_x100                2500    /* 25.0 Volt */
-#define TARGET_V_DIVIDER_RATIO_x100    21376L  /* (R1+R2)/R2 = 213.76 */
-#define DIVIDER_RATIO_ACCURx100                (22 * 100)
-#define V_AD_x10000                    10834L  /* VAD = 1.0834 */
-#define TARGET_VDDx100                 330     /* VDD = 3.3 * 10 */
-#define VDD_MAX_DIFFx100               20      /* VDD Accur = 0.2*100 */
-
-#define RMS_MULTIPLIERx100             111     /* pi/(2xsqrt(2)) = 1.11*/
-#define K_INTDC_RECT_ON                        4       /* When Rectifier is ON this value is necessary(2^4) */
-#define K_INTDC_RECT_OFF               2       /* 2^2 */
-#define RNG_FREQ                       25
-#define SAMPLING_FREQ                  (2000L)
-#define N_SAMPLES                      (SAMPLING_FREQ/RNG_FREQ)     /* for Ring Freq =25Hz (40ms Integration Period)[Sampling rate 2KHz -->1 Sample every 500us] */
-#define HOOK_THRESH_RING_START_ADDR    0x8B
-#define RING_PARAMS_START_ADDR         0x70
-
-#define V_OUT_BATH_MAX_DIFFx100                300     /* 3.0 x100 */
-#define V_OUT_BATL_MAX_DIFFx100                400     /* 4.0 x100 */
-#define MAX_V_RING_MEANx100            50
-#define TARGET_V_RING_RMSx100          2720
-#define V_RMS_RING_MAX_DIFFx100                250
-
-#define LM_OK_SRC_IRG_2                        (1 << 4)
-
-/************************************************/
-
-#define PORTB          (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define PORTC          (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define PORTD          (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
-
-#define _PORTD_SET(mask, state) \
-       do { \
-               if (state) \
-                       PORTD |= mask; \
-               else \
-                       PORTD &= ~mask; \
-       } while (0)
-
-#define _PORTB_SET(mask, state) \
-       do { \
-               if (state) \
-                       PORTB |= mask; \
-               else \
-                       PORTB &= ~mask; \
-       } while (0)
-
-#define _PORTB_TGL(mask) do { PORTB ^= mask; } while (0)
-#define _PORTB_GET(mask) (!!(PORTB & mask))
-
-#define _PORTC_GET(mask) (!!(PORTC & mask))
-
-/* port B */
-#define SPI_RXD                (1 << (31 - 28))
-#define SPI_TXD                (1 << (31 - 29))
-#define SPI_CLK                (1 << (31 - 30))
-
-/* port C */
-#define COM_HOOK1      (1 << (15 - 9))
-#define COM_HOOK2      (1 << (15 - 10))
-
-#ifndef CONFIG_NETTA_SWAPHOOK
-
-#define COM_HOOK3      (1 << (15 - 11))
-#define COM_HOOK4      (1 << (15 - 12))
-
-#else
-
-#define COM_HOOK3      (1 << (15 - 12))
-#define COM_HOOK4      (1 << (15 - 11))
-
-#endif
-
-/* port D */
-#define SPIENC1                (1 << (15 - 9))
-#define SPIENC2                (1 << (15 - 10))
-#define SPIENC3                (1 << (15 - 11))
-#define SPIENC4                (1 << (15 - 14))
-
-#define SPI_DELAY() udelay(1)
-
-static inline unsigned int __SPI_Transfer(unsigned int tx)
-{
-       unsigned int rx;
-       int b;
-
-       rx = 0; b = 8;
-       while (--b >= 0) {
-               _PORTB_SET(SPI_TXD, tx & 0x80);
-               tx <<= 1;
-               _PORTB_TGL(SPI_CLK);
-               SPI_DELAY();
-               rx <<= 1;
-               rx |= _PORTB_GET(SPI_RXD);
-               _PORTB_TGL(SPI_CLK);
-               SPI_DELAY();
-       }
-
-       return rx;
-}
-
-static const char *codsp_dtmf_map = "D1234567890*#ABC";
-
-static const int spienc_mask_tab[4] = { SPIENC1, SPIENC2, SPIENC3, SPIENC4 };
-static const int com_hook_mask_tab[4] = { COM_HOOK1, COM_HOOK2, COM_HOOK3, COM_HOOK4 };
-
-static unsigned int codsp_send(int duslic_id, const unsigned char *cmd, int cmdlen, unsigned char *res, int reslen)
-{
-       unsigned int rx;
-       int i;
-
-       /* just some sanity checks */
-       if (cmd == 0 || cmdlen < 0)
-               return -1;
-
-       _PORTD_SET(spienc_mask_tab[duslic_id], 0);
-
-       /* first 2 bytes are without response */
-       i = 2;
-       while (i-- > 0 && cmdlen-- > 0)
-               __SPI_Transfer(*cmd++);
-
-       while (cmdlen-- > 0) {
-               rx = __SPI_Transfer(*cmd++);
-               if (res != 0 && reslen-- > 0)
-                       *res++ = (unsigned char)rx;
-       }
-       if (res != 0) {
-               while (reslen-- > 0)
-                       *res++ = __SPI_Transfer(0xFF);
-       }
-
-       _PORTD_SET(spienc_mask_tab[duslic_id], 1);
-
-       return 0;
-}
-
-/****************************************************************************/
-
-void codsp_set_ciop_m(int duslic_id, int channel, unsigned char m)
-{
-       unsigned char cmd = CODSP_WR | CODSP_ADR(channel) | CODSP_M(m);
-       codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-void codsp_reset_chip(int duslic_id)
-{
-       static const unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_CMD_SOFT_RESET;
-       codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-void codsp_reset_channel(int duslic_id, int channel)
-{
-       unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESET_CH;
-       codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-void codsp_resync_channel(int duslic_id, int channel)
-{
-       unsigned char cmd = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_RESYNC;
-       codsp_send(duslic_id, &cmd, 1, 0, 0);
-}
-
-/****************************************************************************/
-
-void codsp_write_sop_char(int duslic_id, int channel, unsigned char regno, unsigned char val)
-{
-       unsigned char cmd[3];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
-       cmd[1] = regno;
-       cmd[2] = val;
-
-       codsp_send(duslic_id, cmd, 3, 0, 0);
-}
-
-void codsp_write_sop_short(int duslic_id, int channel, unsigned char regno, unsigned short val)
-{
-       unsigned char cmd[4];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
-       cmd[1] = regno;
-       cmd[2] = (unsigned char)(val >> 8);
-       cmd[3] = (unsigned char)val;
-
-       codsp_send(duslic_id, cmd, 4, 0, 0);
-}
-
-void codsp_write_sop_int(int duslic_id, int channel, unsigned char regno, unsigned int val)
-{
-       unsigned char cmd[6];
-
-       cmd[0] = CODSP_WR | CODSP_ADR(channel) | CODSP_CMD_SOP;
-       cmd[1] = regno;
-       cmd[2] = (unsigned char)(val >> 24);
-       cmd[3] = (unsigned char)(val >> 16);
-       cmd[4] = (unsigned char)(val >> 8);
-       cmd[5] = (unsigned char)val;
-
-       codsp_send(duslic_id, cmd, 6, 0, 0);
-}
-
-unsigned char codsp_read_sop_char(int duslic_id, int channel, unsigned char regno)
-{
-       unsigned char cmd[3];
-       unsigned char res[2];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
-       cmd[1] = regno;
-
-       codsp_send(duslic_id, cmd, 2, res, 2);
-
-       return res[1];
-}
-
-unsigned short codsp_read_sop_short(int duslic_id, int channel, unsigned char regno)
-{
-       unsigned char cmd[2];
-       unsigned char res[3];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
-       cmd[1] = regno;
-
-       codsp_send(duslic_id, cmd, 2, res, 3);
-
-       return ((unsigned short)res[1] << 8) | res[2];
-}
-
-unsigned int codsp_read_sop_int(int duslic_id, int channel, unsigned char regno)
-{
-       unsigned char cmd[2];
-       unsigned char res[5];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_SOP;
-       cmd[1] = regno;
-
-       codsp_send(duslic_id, cmd, 2, res, 5);
-
-       return ((unsigned int)res[1] << 24) | ((unsigned int)res[2] << 16) | ((unsigned int)res[3] << 8) | res[4];
-}
-
-/****************************************************************************/
-
-void codsp_write_cop_block(int duslic_id, int channel, unsigned char addr, const unsigned char *block)
-{
-       unsigned char cmd[10];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
-       cmd[1] = addr;
-       memcpy(cmd + 2, block, 8);
-       codsp_send(duslic_id, cmd, 10, 0, 0);
-}
-
-void codsp_write_cop_char(int duslic_id, int channel, unsigned char addr, unsigned char val)
-{
-       unsigned char cmd[3];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
-       cmd[1] = addr;
-       cmd[2] = val;
-       codsp_send(duslic_id, cmd, 3, 0, 0);
-}
-
-void codsp_write_cop_short(int duslic_id, int channel, unsigned char addr, unsigned short val)
-{
-       unsigned char cmd[4];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
-       cmd[1] = addr;
-       cmd[2] = (unsigned char)(val >> 8);
-       cmd[3] = (unsigned char)val;
-
-       codsp_send(duslic_id, cmd, 4, 0, 0);
-}
-
-void codsp_read_cop_block(int duslic_id, int channel, unsigned char addr, unsigned char *block)
-{
-       unsigned char cmd[2];
-       unsigned char res[9];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
-       cmd[1] = addr;
-       codsp_send(duslic_id, cmd, 2, res, 9);
-       memcpy(block, res + 1, 8);
-}
-
-unsigned char codsp_read_cop_char(int duslic_id, int channel, unsigned char addr)
-{
-       unsigned char cmd[2];
-       unsigned char res[2];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
-       cmd[1] = addr;
-       codsp_send(duslic_id, cmd, 2, res, 2);
-       return res[1];
-}
-
-unsigned short codsp_read_cop_short(int duslic_id, int channel, unsigned char addr)
-{
-       unsigned char cmd[2];
-       unsigned char res[3];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR(channel) | CODSP_CMD_COP;
-       cmd[1] = addr;
-
-       codsp_send(duslic_id, cmd, 2, res, 3);
-
-       return ((unsigned short)res[1] << 8) | res[2];
-}
-
-/****************************************************************************/
-
-#define MAX_POP_BLOCK  50
-
-void codsp_write_pop_block (int duslic_id, int channel, unsigned char addr,
-                           const unsigned char *block, int len)
-{
-       unsigned char cmd[2 + MAX_POP_BLOCK];
-
-       if (len > MAX_POP_BLOCK)        /* truncate */
-               len = MAX_POP_BLOCK;
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = addr;
-       memcpy (cmd + 2, block, len);
-       codsp_send (duslic_id, cmd, 2 + len, 0, 0);
-}
-
-void codsp_write_pop_char (int duslic_id, int channel, unsigned char regno,
-                          unsigned char val)
-{
-       unsigned char cmd[3];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = regno;
-       cmd[2] = val;
-
-       codsp_send (duslic_id, cmd, 3, 0, 0);
-}
-
-void codsp_write_pop_short (int duslic_id, int channel, unsigned char regno,
-                           unsigned short val)
-{
-       unsigned char cmd[4];
-
-       cmd[0] = CODSP_WR | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = regno;
-       cmd[2] = (unsigned char) (val >> 8);
-       cmd[3] = (unsigned char) val;
-
-       codsp_send (duslic_id, cmd, 4, 0, 0);
-}
-
-void codsp_write_pop_int (int duslic_id, int channel, unsigned char regno,
-                         unsigned int val)
-{
-       unsigned char cmd[6];
-
-       cmd[0] = CODSP_WR | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = regno;
-       cmd[2] = (unsigned char) (val >> 24);
-       cmd[3] = (unsigned char) (val >> 16);
-       cmd[4] = (unsigned char) (val >> 8);
-       cmd[5] = (unsigned char) val;
-
-       codsp_send (duslic_id, cmd, 6, 0, 0);
-}
-
-unsigned char codsp_read_pop_char (int duslic_id, int channel,
-                                  unsigned char regno)
-{
-       unsigned char cmd[3];
-       unsigned char res[2];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = regno;
-
-       codsp_send (duslic_id, cmd, 2, res, 2);
-
-       return res[1];
-}
-
-unsigned short codsp_read_pop_short (int duslic_id, int channel,
-                                    unsigned char regno)
-{
-       unsigned char cmd[2];
-       unsigned char res[3];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = regno;
-
-       codsp_send (duslic_id, cmd, 2, res, 3);
-
-       return ((unsigned short) res[1] << 8) | res[2];
-}
-
-unsigned int codsp_read_pop_int (int duslic_id, int channel,
-                                unsigned char regno)
-{
-       unsigned char cmd[2];
-       unsigned char res[5];
-
-       cmd[0] = CODSP_RD | CODSP_OP | CODSP_ADR (channel) | CODSP_CMD_POP;
-       cmd[1] = regno;
-
-       codsp_send (duslic_id, cmd, 2, res, 5);
-
-       return (((unsigned int) res[1] << 24) |
-               ((unsigned int) res[2] << 16) |
-               ((unsigned int) res[3] <<  8) |
-               res[4] );
-}
-/****************************************************************************/
-
-struct _coeffs {
-       unsigned char addr;
-       unsigned char values[8];
-};
-
-struct _coeffs ac_coeffs[11] = {
-       { 0x60, {0xAD,0xDA,0xB5,0x9B,0xC7,0x2A,0x9D,0x00} }, /* 0x60 IM-Filter part 1 */
-       { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x77,0x0A,0x00} }, /* 0x68 IM-Filter part 2 */
-       { 0x18, {0x08,0xC0,0xD2,0xAB,0xA5,0xE2,0xAB,0x07} }, /* 0x18 FRR-Filter       */
-       { 0x28, {0x44,0x93,0xF5,0x92,0x88,0x00,0x00,0x00} }, /* 0x28 AR-Filter        */
-       { 0x48, {0x96,0x38,0x29,0x96,0xC9,0x2B,0x8B,0x00} }, /* 0x48 LPR-Filter       */
-       { 0x20, {0x08,0xB0,0xDA,0x9D,0xA7,0xFA,0x93,0x06} }, /* 0x20 FRX-Filter       */
-       { 0x30, {0xBA,0xAC,0x00,0x01,0x85,0x50,0xC0,0x1A} }, /* 0x30 AX-Filter        */
-       { 0x50, {0x96,0x38,0x29,0xF5,0xFA,0x2B,0x8B,0x00} }, /* 0x50 LPX-Filter       */
-       { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} }, /* 0x00 TH-Filter part 1 */
-       { 0x08, {0x81,0x00,0x80,0x00,0xD7,0x33,0xBA,0x01} }, /* 0x08 TH-Filter part 2 */
-       { 0x10, {0xB3,0x6C,0xDC,0xA3,0xA4,0xE5,0x88,0x00} }  /* 0x10 TH-Filter part 3 */
-};
-
-struct _coeffs ac_coeffs_0dB[11] = {
-       { 0x60, {0xAC,0x2A,0xB5,0x9A,0xB7,0x2A,0x9D,0x00} },
-       { 0x68, {0x10,0x00,0xA9,0x82,0x0D,0x83,0x0A,0x00} },
-       { 0x18, {0x08,0x20,0xD4,0xA4,0x65,0xEE,0x92,0x07} },
-       { 0x28, {0x2B,0xAB,0x36,0xA5,0x88,0x00,0x00,0x00} },
-       { 0x48, {0xAB,0xE9,0x4E,0x32,0xAB,0x25,0xA5,0x03} },
-       { 0x20, {0x08,0x20,0xDB,0x9C,0xA7,0xFA,0xB4,0x07} },
-       { 0x30, {0xF3,0x10,0x07,0x60,0x85,0x40,0xC0,0x1A} },
-       { 0x50, {0x96,0x38,0x29,0x97,0x39,0x19,0x8B,0x00} },
-       { 0x00, {0x00,0x08,0x08,0x81,0x00,0x80,0x00,0x08} },
-       { 0x08, {0x81,0x00,0x80,0x00,0x47,0x3C,0xD2,0x01} },
-       { 0x10, {0x62,0xDB,0x4A,0x87,0x73,0x28,0x88,0x00} }
-};
-
-struct _coeffs dc_coeffs[9] = {
-       { 0x80, {0x25,0x59,0x9C,0x23,0x24,0x23,0x32,0x1C} }, /* 0x80 DC-Parameter     */
-       { 0x70, {0x90,0x30,0x1B,0xC0,0x33,0x43,0xAC,0x02} }, /* 0x70 Ringing          */
-       { 0x90, {0x3F,0xC3,0x2E,0x3A,0x80,0x90,0x00,0x09} }, /* 0x90 LP-Filters       */
-       { 0x88, {0xAF,0x80,0x27,0x7B,0x01,0x4C,0x7B,0x02} }, /* 0x88 Hook Levels      */
-       { 0x78, {0x00,0xC0,0x6D,0x7A,0xB3,0x78,0x89,0x00} }, /* 0x78 Ramp Generator   */
-       { 0x58, {0xA5,0x44,0x34,0xDB,0x0E,0xA2,0x2A,0x00} }, /* 0x58 TTX              */
-       { 0x38, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x38 TG1              */
-       { 0x40, {0x33,0x49,0x9A,0x65,0xBB,0x00,0x00,0x00} }, /* 0x40 TG2              */
-       { 0x98, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} }  /* 0x98 Reserved         */
-};
-
-void program_coeffs(int duslic_id, int channel, struct _coeffs *coeffs, int tab_size)
-{
-       int i;
-
-       for (i = 0; i < tab_size; i++)
-       codsp_write_cop_block(duslic_id, channel, coeffs[i].addr, coeffs[i].values);
-}
-
-#define SS_OPEN_CIRCUIT                        0
-#define SS_RING_PAUSE                  1
-#define SS_ACTIVE                      2
-#define SS_ACTIVE_HIGH                 3
-#define SS_ACTIVE_RING                 4
-#define SS_RINGING                     5
-#define SS_ACTIVE_WITH_METERING                6
-#define SS_ONHOOKTRNSM                 7
-#define SS_STANDBY                     8
-#define SS_MAX                         8
-
-static void codsp_set_slic(int duslic_id, int channel, int state)
-{
-       unsigned char v;
-
-       v = codsp_read_sop_char(duslic_id, channel, BCR1_ADDR);
-
-       switch (state) {
-
-               case SS_ACTIVE:
-                       codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTR) | BCR1_ACTL);
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
-                       break;
-
-               case SS_ACTIVE_HIGH:
-                       codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTR | BCR1_ACTL));
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
-                       break;
-
-               case SS_ACTIVE_RING:
-               case SS_ONHOOKTRNSM:
-                       codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, (v & ~BCR1_ACTL) | BCR1_ACTR);
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_ANY_ACT);
-                       break;
-
-               case SS_STANDBY:
-                       codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, v & ~(BCR1_ACTL | BCR1_ACTR));
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_SLEEP_PWRDN);
-                       break;
-
-               case SS_OPEN_CIRCUIT:
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_PWRDN_HIZ);
-                       break;
-
-               case SS_RINGING:
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING);
-                       break;
-
-               case SS_RING_PAUSE:
-                       codsp_set_ciop_m(duslic_id, channel, CODSP_M_RING_PAUSE);
-                       break;
-       }
-}
-
-const unsigned char Ring_Sin_28Vrms_25Hz[8] = { 0x90, 0x30, 0x1B, 0xC0, 0xC3, 0x9C, 0x88, 0x00 };
-const unsigned char Max_HookRingTh[3] = { 0x7B, 0x41, 0x62 };
-
-void retrieve_slic_state(int slic_id)
-{
-       int duslic_id = slic_id >> 1;
-       int channel = slic_id & 1;
-
-       /* Retrieve the state of the SLICs */
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
-
-       /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
-       udelay(10000);
-
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-       codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
-       codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);
-
-       /* Program Default Hook Ring thresholds */
-       codsp_write_cop_block(duslic_id, channel, dc_coeffs[1].addr, dc_coeffs[1].values);
-
-       /* Now program Hook Threshold while Ring and ac RingTrip to max values */
-       codsp_write_cop_block(duslic_id, channel, dc_coeffs[3].addr, dc_coeffs[3].values);
-
-       codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
-
-       udelay(40000);
-}
-
-int wait_level_metering_finish(int duslic_id, int channel)
-{
-       int cnt;
-
-       for (cnt = 0; cnt < 1000 &&
-               (codsp_read_sop_char(duslic_id, channel, INTREG2_ADDR) & LM_OK_SRC_IRG_2) == 0; cnt++) { }
-
-       return cnt != 1000;
-}
-
-int measure_on_hook_voltages(int slic_id, long *vdd,
-               long *v_oh_H, long *v_oh_L, long *ring_mean_v, long *ring_rms_v)
-{
-       short LM_Result, Offset_Compensation;   /* Signed 16 bit */
-       long int VDD, VDD_diff, V_in, V_out, Divider_Ratio, Vout_diff ;
-       unsigned char err_mask = 0;
-       int duslic_id = slic_id >> 1;
-       int channel = slic_id & 1;
-       int i;
-
-       /* measure VDD */
-       /* Now select the VDD level Measurement (but first of all Hold the DC characteristic) */
-       codsp_write_sop_char(duslic_id, channel, TSTR5_ADDR, TSTR5_DC_HOLD);
-
-       /* Activate Test Mode ==> To Enable DC Hold !!! */
-       /* (else the LMRES is treated as Feeding Current and the Feeding voltage changes */
-       /* imediatelly (after 500us when the LMRES Registers is updated for the first time after selection of (IO4-IO3) measurement !!!!))*/
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
-
-       udelay(40000);
-
-       /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_VDD);
-
-       /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
-       udelay(10000);
-
-       /* Now Read the LM Result Registers */
-       LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-       VDD = (-1)*((((long int)LM_Result) * 390L ) >> 15) ;    /* VDDx100 */
-
-       *vdd = VDD;
-
-       VDD_diff = VDD - TARGET_VDDx100;
-
-       if (VDD_diff < 0)
-               VDD_diff = -VDD_diff;
-
-       if (VDD_diff > VDD_MAX_DIFFx100)
-               err_mask |= 1;
-
-       Divider_Ratio = TARGET_V_DIVIDER_RATIO_x100;
-
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-
-       codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH); /* Go back to ONHOOK Voltage */
-
-       udelay(40000);
-
-       codsp_write_sop_char(duslic_id, channel,
-               LMCR1_ADDR, LMCR1_TEST_EN | LMCR1_LM_THM | LMCR1_LM_MASK);
-
-       udelay(40000);
-
-       /* Now I Can select what to measure by DC Level Meter (select IO4-IO3) */
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
-
-       /* wait at least 1000us to clear the LM_OK and 500us to set the LM_OK ==> for the LM to make the first Measurement */
-       udelay(10000);
-
-       /* Now Read the LM Result Registers */
-       LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-       V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
-
-       V_out = (V_in * Divider_Ratio) / 10000L ;       /* Vout x100 */
-
-       *v_oh_H = V_out;
-
-       Vout_diff = V_out - TARGET_ONHOOK_BATH_x100;
-
-       if (Vout_diff < 0)
-               Vout_diff = -Vout_diff;
-
-       if (Vout_diff > V_OUT_BATH_MAX_DIFFx100)
-               err_mask |= 2;
-
-       codsp_set_slic(duslic_id, channel, SS_ACTIVE); /* Go back to ONHOOK Voltage */
-
-       udelay(40000);
-
-       /* Now Read the LM Result Registers */
-       LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-
-       V_in = (-1)* ((((long int)LM_Result) * V_AD_x10000 ) >> 15) ;  /* Vin x 10000*/
-
-       V_out = (V_in * Divider_Ratio) / 10000L ;       /* Vout x100 */
-
-       *v_oh_L = V_out;
-
-       Vout_diff = V_out - TARGET_ONHOOK_BATL_x100;
-
-       if (Vout_diff < 0)
-               Vout_diff = -Vout_diff;
-
-       if (Vout_diff > V_OUT_BATL_MAX_DIFFx100)
-               err_mask |= 4;
-
-       /* perform ring tests */
-
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, 0x00);
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-
-       udelay(40000);
-
-       codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, LMCR3_RTR_SEL | LMCR3_RNG_OFFSET_NONE);
-
-       /* Now program RO1 =0V , Ring Amplitude and frequency and shift factor K = 1 (LMDC=0x0088)*/
-       codsp_write_cop_block(duslic_id, channel, RING_PARAMS_START_ADDR, Ring_Sin_28Vrms_25Hz);
-
-       /* By Default RO1 is selected when ringing RNG-OFFSET = 00 */
-
-       /* Now program Hook Threshold while Ring and ac RingTrip to max values */
-       for(i = 0; i < sizeof(Max_HookRingTh); i++)
-               codsp_write_cop_char(duslic_id, channel, HOOK_THRESH_RING_START_ADDR + i, Max_HookRingTh[i]);
-
-       codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
-
-       codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
-
-       /* select source for the levelmeter to be IO4-IO3 */
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR, LMCR2_LM_SEL_IO4_MINUS_IO3);
-
-       udelay(40000);
-
-       /* Before Enabling Level Meter Programm the apropriate shift factor K_INTDC=(4 if Rectifier Enabled and 2 if Rectifier Disabled) */
-       codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_OFF);
-
-       udelay(10000);
-
-       /* Enable LevelMeter to Integrate only once (Rectifier Disabled) */
-       codsp_write_sop_char(duslic_id, channel,
-                       LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
-       udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
-
-       if (wait_level_metering_finish(duslic_id, channel)) {
-
-               udelay(10000); /* To be sure that Integration Results are Valid wait at least 500us !!! */
-
-               /* Now Read the LM Result Registers (Will be valid until LM_EN becomes zero again( after that the Result is updated every 500us) ) */
-               Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-               Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_OFF)) / N_SAMPLES);
-
-               /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
-               codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
-
-               /* Now programm Integrator Offset Registers !!! */
-               codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
-
-               codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing */
-
-               udelay(40000);
-
-               /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
-               codsp_write_sop_char(duslic_id, channel,
-                               LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
-               udelay(40000); /* Integration Period == Ring Period = 40ms (for 25Hz Ring) */
-
-               /* Poll the LM_OK bit to see when Integration Result is Ready */
-               if (wait_level_metering_finish(duslic_id, channel)) {
-
-                       udelay(10000); /* wait at least 500us to be sure that the Integration Result are valid !!! */
-
-                       /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
-                       /*                                  ==>After that Result Regs will be updated every 500us !!!) */
-                       LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-                       V_in = (-1) * ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_OFF)) ;  /* Vin x 10000*/
-
-                       V_out = (V_in * Divider_Ratio) / 10000L ;       /* Vout x100 */
-
-                       if (V_out < 0)
-                               V_out= -V_out;
-
-                       if (V_out > MAX_V_RING_MEANx100)
-                               err_mask |= 8;
-
-                       *ring_mean_v = V_out;
-               } else {
-                       err_mask |= 8;
-                       *ring_mean_v = 0;
-               }
-       } else {
-               err_mask |= 8;
-               *ring_mean_v = 0;
-       }
-
-       /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
-               LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
-       codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, 0x0000);
-
-       codsp_set_slic(duslic_id, channel, SS_RING_PAUSE); /* Start Ringing */
-
-       /* Now Enable Rectifier */
-       /* select source for the levelmeter to be IO4-IO3 */
-       codsp_write_sop_char(duslic_id, channel, LMCR2_ADDR,
-               LMCR2_LM_SEL_IO4_MINUS_IO3 | LMCR2_LM_RECT);
-
-       /* Program the apropriate shift factor K_INTDC (in order to avoid Overflow at Integtation Result !!!) */
-       codsp_write_cop_char(duslic_id, channel, RING_PARAMS_START_ADDR + 7, K_INTDC_RECT_ON);
-
-       udelay(40000);
-
-       /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
-                       LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
-       udelay(40000);
-
-       /* Poll the LM_OK bit to see when Integration Result is Ready */
-       if (wait_level_metering_finish(duslic_id, channel)) {
-
-               udelay(10000);
-
-               /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
-               /*                                  ==>After that Result Regs will be updated every 500us !!!) */
-               Offset_Compensation = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-               Offset_Compensation = (-1) * ((Offset_Compensation * (1 << K_INTDC_RECT_ON)) / N_SAMPLES);
-
-               /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
-               codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_ONCE);
-
-               /* Now programm Integrator Offset Registers !!! */
-               codsp_write_sop_short(duslic_id, channel, OFR1_ADDR, Offset_Compensation);
-
-               /* Be sure that a Ring is generated !!!! */
-               codsp_set_slic(duslic_id, channel, SS_RINGING); /* Start Ringing again */
-
-               udelay(40000);
-
-               /* Reenable Level Meter Integrator (The Result will be valid after Integration Period=Ring Period and until LN_EN become zero again) */
-               codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR,
-                               LMCR1_LM_THM | LMCR1_LM_MASK | LMCR1_LM_EN | LMCR1_LM_ONCE);
-
-               udelay(40000);
-
-               /* Poll the LM_OK bit to see when Integration Result is Ready */
-               if (wait_level_metering_finish(duslic_id, channel)) {
-
-                       udelay(10000);
-
-                       /* Now Read the LM Result Registers (They will hold their value until LM_EN become zero again */
-                       /*                                  ==>After that Result Regs will be updated every 500us !!!) */
-                       LM_Result = codsp_read_sop_short(duslic_id, channel, LMRES1_ADDR);
-                       V_in = (-1) *  ( ( (((long int)LM_Result) * V_AD_x10000) / N_SAMPLES) >> (15 - K_INTDC_RECT_ON) ) ;  /* Vin x 10000*/
-
-                       V_out = (((V_in * Divider_Ratio) / 10000L) * RMS_MULTIPLIERx100) / 100 ;        /* Vout_RMS x100 */
-                       if (V_out < 0)
-                               V_out = -V_out;
-
-                       Vout_diff = (V_out - TARGET_V_RING_RMSx100);
-
-                       if (Vout_diff < 0)
-                               Vout_diff = -Vout_diff;
-
-                       if (Vout_diff > V_RMS_RING_MAX_DIFFx100)
-                               err_mask |= 16;
-
-                       *ring_rms_v = V_out;
-               } else {
-                       err_mask |= 16;
-                       *ring_rms_v = 0;
-               }
-       } else {
-               err_mask |= 16;
-               *ring_rms_v = 0;
-       }
-       /* Disable LevelMeter ==> In order to be able to restart Integrator again (for the next integration) */
-       codsp_write_sop_char(duslic_id, channel, LMCR1_ADDR, LMCR1_LM_THM | LMCR1_LM_MASK);
-
-       retrieve_slic_state(slic_id);
-
-       return(err_mask);
-}
-
-int test_dtmf(int slic_id)
-{
-       unsigned char code;
-       unsigned char b;
-       unsigned int intreg;
-       int duslic_id = slic_id >> 1;
-       int channel = slic_id & 1;
-
-       for (code = 0; code < 16; code++) {
-               b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
-               codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
-                       (b & ~(DSCR_PTG | DSCR_DG_KEY(15))) | DSCR_DG_KEY(code) | DSCR_TG1_EN | DSCR_TG2_EN);
-               udelay(80000);
-
-               intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR);
-               if ((intreg & CODSP_INTREG_INT_CH) == 0)
-                       break;
-
-               if ((intreg & CODSP_INTREG_DTMF_OK) == 0 ||
-                               codsp_dtmf_map[(intreg >> 10) & 15] != codsp_dtmf_map[code])
-                       break;
-
-               b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR);
-               codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
-                               b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
-
-               udelay(80000);
-
-               intreg = codsp_read_sop_int(duslic_id, channel, INTREG1_ADDR); /* for dtmf_pause irq */
-       }
-
-       if (code != 16) {
-               b = codsp_read_sop_char(duslic_id, channel, DSCR_ADDR); /* stop dtmf */
-               codsp_write_sop_char(duslic_id, channel, DSCR_ADDR,
-                               b & ~(DSCR_COR8 | DSCR_TG1_EN | DSCR_TG2_EN));
-               return(1);
-       }
-
-       return(0);
-}
-
-void data_up_persist_time(int duslic_id, int channel, int time_ms)
-{
-       unsigned char b;
-
-       b = codsp_read_sop_char(duslic_id, channel, IOCTL3_ADDR);
-       b = (b & 0x0F) | ((time_ms & 0x0F) << 4);
-       codsp_write_sop_char(duslic_id, channel, IOCTL3_ADDR, b);
-}
-
-static void program_dtmf_params(int duslic_id, int channel)
-{
-       unsigned char b;
-
-       codsp_write_pop_char(duslic_id, channel, DTMF_LEV_ADDR, 0x10);
-       codsp_write_pop_char(duslic_id, channel, DTMF_TWI_ADDR, 0x0C);
-       codsp_write_pop_char(duslic_id, channel, DTMF_NCF_H_ADDR, 0x79);
-       codsp_write_pop_char(duslic_id, channel, DTMF_NCF_L_ADDR, 0x10);
-       codsp_write_pop_char(duslic_id, channel, DTMF_NBW_H_ADDR, 0x02);
-       codsp_write_pop_char(duslic_id, channel, DTMF_NBW_L_ADDR, 0xFB);
-       codsp_write_pop_char(duslic_id, channel, DTMF_GAIN_ADDR, 0x91);
-       codsp_write_pop_char(duslic_id, channel, DTMF_RES1_ADDR, 0x00);
-       codsp_write_pop_char(duslic_id, channel, DTMF_RES2_ADDR, 0x00);
-       codsp_write_pop_char(duslic_id, channel, DTMF_RES3_ADDR, 0x00);
-
-       b = codsp_read_sop_char(duslic_id, channel, BCR5_ADDR);
-       codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, b | BCR5_DTMF_EN);
-}
-
-static void codsp_channel_full_reset(int duslic_id, int channel)
-{
-
-       program_coeffs(duslic_id, channel, ac_coeffs, sizeof(ac_coeffs) / sizeof(struct _coeffs));
-       program_coeffs(duslic_id, channel, dc_coeffs, sizeof(dc_coeffs) / sizeof(struct _coeffs));
-
-       /* program basic configuration registers */
-       codsp_write_sop_char(duslic_id, channel, BCR1_ADDR, 0x01);
-       codsp_write_sop_char(duslic_id, channel, BCR2_ADDR, 0x41);
-       codsp_write_sop_char(duslic_id, channel, BCR3_ADDR, 0x43);
-       codsp_write_sop_char(duslic_id, channel, BCR4_ADDR, 0x00);
-       codsp_write_sop_char(duslic_id, channel, BCR5_ADDR, 0x00);
-
-       codsp_write_sop_char(duslic_id, channel, DSCR_ADDR, 0x04);              /* PG */
-
-       program_dtmf_params(duslic_id, channel);
-
-       codsp_write_sop_char(duslic_id, channel, LMCR3_ADDR, 0x40);     /* RingTRip_SEL */
-
-       data_up_persist_time(duslic_id, channel, 4);
-
-       codsp_write_sop_char(duslic_id, channel, MASK_ADDR, 0xFF);     /* All interrupts masked */
-
-       codsp_set_slic(duslic_id, channel, SS_ACTIVE_HIGH);
-}
-
-static int codsp_chip_full_reset(int duslic_id)
-{
-       int i, cnt;
-       int intreg[NUM_CHANNELS];
-       unsigned char pcm_resync;
-       unsigned char revision;
-
-       codsp_reset_chip(duslic_id);
-
-       udelay(2000);
-
-       for (i = 0; i < NUM_CHANNELS; i++)
-               intreg[i] = codsp_read_sop_int(duslic_id, i, INTREG1_ADDR);
-
-       udelay(1500);
-
-       if (_PORTC_GET(com_hook_mask_tab[duslic_id]) == 0) {
-               printf("_HOOK(%d) stayed low\n", duslic_id);
-               return -1;
-       }
-
-       for (pcm_resync = 0, i = 0; i < NUM_CHANNELS; i++) {
-               if (intreg[i] & CODSP_INTREG_SYNC_FAIL)
-                       pcm_resync |= 1 << i;
-       }
-
-       for (cnt = 0; cnt < 5 && pcm_resync; cnt++) {
-               for (i = 0; i < NUM_CHANNELS; i++)
-                       codsp_resync_channel(duslic_id, i);
-
-               udelay(2000);
-
-               pcm_resync = 0;
-
-               for (i = 0; i < NUM_CHANNELS; i++) {
-                       if (codsp_read_sop_int(duslic_id, i, INTREG1_ADDR) & CODSP_INTREG_SYNC_FAIL)
-                               pcm_resync |= 1 << i;
-               }
-       }
-
-       if (cnt == 5) {
-               printf("PCM_Resync(%u) not completed\n", duslic_id);
-               return -2;
-       }
-
-       revision = codsp_read_sop_char(duslic_id, 0, REVISION_ADDR);
-       printf("DuSLIC#%d hardware version %d.%d\r\n", duslic_id, (revision & 0xF0) >> 4, revision & 0x0F);
-
-       codsp_write_sop_char(duslic_id, 0, XCR_ADDR, 0x80);     /* EDSP_EN */
-
-       for (i = 0; i < NUM_CHANNELS; i++) {
-               codsp_write_sop_char(duslic_id, i, PCMC1_ADDR, 0x01);
-               codsp_channel_full_reset(duslic_id, i);
-       }
-
-       return 0;
-}
-
-int slic_self_test(int duslic_mask)
-{
-       int slic;
-       int i;
-       int r;
-       long vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v;
-       const char *err_txt[] = { "VDD", "V_OH_H", "V_OH_L", "V_RING_MEAN", "V_RING_RMS" };
-       int error = 0;
-
-       for (slic = 0; slic < MAX_SLICS; slic++) { /* voltages self test */
-               if (duslic_mask & (1 << (slic >> 1))) {
-                       r = measure_on_hook_voltages(slic, &vdd,
-                               &v_oh_H, &v_oh_L, &ring_mean_v, &ring_rms_v);
-
-                       printf("SLIC %u measured voltages (x100):\n\t"
-                                   "VDD = %ld\tV_OH_H = %ld\tV_OH_L = %ld\tV_RING_MEAN = %ld\tV_RING_RMS = %ld\n",
-                                   slic, vdd, v_oh_H, v_oh_L, ring_mean_v, ring_rms_v);
-
-                       if (r != 0)
-                               error |= 1 << slic;
-
-                       for (i = 0; i < 5; i++)
-                               if (r & (1 << i))
-                                       printf("\t%s out of range\n", err_txt[i]);
-               }
-       }
-
-       for (slic = 0; slic < MAX_SLICS; slic++) { /* voice path self test */
-               if (duslic_mask & (1 << (slic >> 1))) {
-                       printf("SLIC %u VOICE PATH...CHECKING", slic);
-                       printf("\rSLIC %u VOICE PATH...%s\n", slic,
-                               (r = test_dtmf(slic)) != 0 ? "FAILED  " : "PASSED  ");
-
-                       if (r != 0)
-                               error |= 1 << slic;
-               }
-       }
-
-       return(error);
-}
-
-#if defined(CONFIG_NETTA_ISDN)
-
-#define SPIENS1                (1 << (31 - 15))
-#define SPIENS2                (1 << (31 - 19))
-
-static const int spiens_mask_tab[2] = { SPIENS1, SPIENS2 };
-int s_initialized = 0;
-
-static inline unsigned int s_transfer_internal(int s_id, unsigned int address, unsigned int value)
-{
-       unsigned int rx, v;
-
-       _PORTB_SET(spiens_mask_tab[s_id], 0);
-
-       rx = __SPI_Transfer(address);
-
-       switch (address & 0xF0) {
-       case 0x60:      /* write byte register */
-       case 0x70:
-               rx = __SPI_Transfer(value);
-               break;
-
-       case 0xE0:      /* read R6 register */
-               v = __SPI_Transfer(0);
-
-               rx = (rx << 8) | v;
-
-               break;
-
-       case 0xF0:      /* read byte register */
-               rx = __SPI_Transfer(0);
-
-               break;
-       }
-
-       _PORTB_SET(spiens_mask_tab[s_id], 1);
-
-       return rx;
-}
-
-static void s_write_BR(int s_id, unsigned int regno, unsigned int val)
-{
-       unsigned int address;
-
-       address = 0x70 | (regno & 15);
-       val &= 0xff;
-
-       (void)s_transfer_internal(s_id, address, val);
-}
-
-static void s_write_OR(int s_id, unsigned int regno, unsigned int val)
-{
-       unsigned int address;
-
-       address = 0x70 | (regno & 15);
-       val &= 0xff;
-
-       (void)s_transfer_internal(s_id, address, val);
-}
-
-static void s_write_NR(int s_id, unsigned int regno, unsigned int val)
-{
-       unsigned int address;
-
-       address = (regno & 7) << 4;
-       val &= 0xf;
-
-       (void)s_transfer_internal(s_id, address | val, 0x00);
-}
-
-#define BR7_IFR                        0x08    /* IDL2 free run */
-#define BR7_ICSLSB             0x04    /* IDL2 clock speed LSB */
-
-#define BR15_OVRL_REG_EN       0x80
-#define OR7_D3VR               0x80    /* disable 3V regulator */
-
-#define OR8_TEME               0x10    /* TE mode enable */
-#define OR8_MME                        0x08    /* master mode enable */
-
-void s_initialize(void)
-{
-       int s_id;
-
-       for (s_id = 0; s_id < 2; s_id++) {
-               s_write_BR(s_id, 7, BR7_IFR | BR7_ICSLSB);
-               s_write_BR(s_id, 15, BR15_OVRL_REG_EN);
-               s_write_OR(s_id, 8, OR8_TEME | OR8_MME);
-               s_write_OR(s_id, 7, OR7_D3VR);
-               s_write_OR(s_id, 6, 0);
-               s_write_BR(s_id, 15, 0);
-               s_write_NR(s_id, 3, 0);
-       }
-}
-
-#endif
-
-int board_post_codec(int flags)
-{
-       int j;
-       int r;
-       int duslic_mask;
-
-       printf("board_post_dsp\n");
-
-#if defined(CONFIG_NETTA_ISDN)
-       if (s_initialized == 0) {
-               s_initialize();
-               s_initialized = 1;
-
-               printf("s_initialized\n");
-
-               udelay(20000);
-       }
-#endif
-       duslic_mask = 0;
-
-       for (j = 0; j < MAX_DUSLIC; j++) {
-               if (codsp_chip_full_reset(j) < 0)
-                       printf("Error initializing DuSLIC#%d\n", j);
-               else
-                       duslic_mask |= 1 << j;
-       }
-
-       if (duslic_mask != 0) {
-               printf("Testing SLICs...\n");
-
-               r = slic_self_test(duslic_mask);
-               for (j = 0; j < MAX_SLICS; j++) {
-                       if (duslic_mask & (1 << (j >> 1)))
-                               printf("SLIC %u...%s\n", j, r & (1 << j) ? "FAULTY" : "OK");
-               }
-       }
-       printf("DuSLIC self test finished\n");
-
-       return 0;       /* return -1 on error */
-}
diff --git a/board/netta/dsp.c b/board/netta/dsp.c
deleted file mode 100644 (file)
index cd57647..0000000
+++ /dev/null
@@ -1,1208 +0,0 @@
-/*
- * Intracom TI6711/TI6412 DSP
- */
-
-#include <common.h>
-#include <post.h>
-
-#include "mpc8xx.h"
-
-struct ram_range {
-       u32 start;
-       u32 size;
-};
-
-#if defined(CONFIG_NETTA_6412)
-
-static const struct ram_range int_ram[] = {
-       { 0x00000000U, 0x00040000U },
-};
-
-static const struct ram_range ext_ram[] = {
-       { 0x80000000U, 0x00100000U },
-};
-
-static const struct ram_range ranges[] = {
-       { 0x00000000U, 0x00040000U },
-       { 0x80000000U, 0x00100000U },
-};
-
-static inline u16 bit_invert(u16 d)
-{
-       register u8 i;
-       register u16 r;
-       register u16 bit;
-
-       r = 0;
-       for (i = 0; i < 16; i++) {
-               bit = d & (1 << i);
-               if (bit != 0)
-                       r |= 1 << (15 - i);
-       }
-       return r;
-}
-
-#else
-
-static const struct ram_range int_ram[] = {
-       { 0x00000000U, 0x00010000U },
-};
-
-static const struct ram_range ext_ram[] = {
-       { 0x80000000U, 0x00100000U },
-};
-
-static const struct ram_range ranges[] = {
-       { 0x00000000U, 0x00010000U },
-       { 0x80000000U, 0x00100000U },
-};
-
-#endif
-
-/*******************************************************************************************************/
-
-static inline int addr_in_int_ram(u32 addr)
-{
-       int i;
-
-       for (i = 0; i < sizeof(int_ram)/sizeof(int_ram[0]); i++)
-               if (addr >= int_ram[i].start && addr < int_ram[i].start + int_ram[i].size)
-                       return 1;
-
-       return 0;
-}
-
-static inline int addr_in_ext_ram(u32 addr)
-{
-       int i;
-
-       for (i = 0; i < sizeof(ext_ram)/sizeof(ext_ram[0]); i++)
-               if (addr >= ext_ram[i].start && addr < ext_ram[i].start + ext_ram[i].size)
-                       return 1;
-
-       return 0;
-}
-
-/*******************************************************************************************************/
-
-#define DSP_HPIC       0x0
-#define DSP_HPIA       0x4
-#define DSP_HPID1      0x8
-#define DSP_HPID2      0xC
-
-static u32 dummy_delay;
-static volatile u32 *ti6711_delay = &dummy_delay;
-
-static inline void dsp_go_slow(void)
-{
-       volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
-#if defined(CONFIG_NETTA_6412)
-       memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
-#else
-       memctl->memc_or2 |= OR_SCY_15_CLK | OR_TRLX;
-#endif
-       memctl->memc_or5 |= OR_SCY_15_CLK | OR_TRLX;
-
-       ti6711_delay = (u32 *)DUMMY_BASE;
-}
-
-static inline void dsp_go_fast(void)
-{
-       volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
-#if defined(CONFIG_NETTA_6412)
-       memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
-#else
-       memctl->memc_or2 = (memctl->memc_or2 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_3_CLK;
-#endif
-       memctl->memc_or5 = (memctl->memc_or5 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
-
-       ti6711_delay = &dummy_delay;
-}
-
-/*******************************************************************************************************/
-
-static inline void dsp_delay(void)
-{
-       /* perform ti6711_delay chip select read to have a small delay */
-       (void) *(volatile u32 *)ti6711_delay;
-}
-
-static inline u16 dsp_read_hpic(void)
-{
-#if defined(CONFIG_NETTA_6412)
-       return bit_invert(*((volatile u16 *)DSP_BASE));
-#else
-       return *((volatile u16 *)DSP_BASE);
-#endif
-}
-
-static inline void dsp_write_hpic(u16 val)
-{
-#if defined(CONFIG_NETTA_6412)
-       *((volatile u16 *)DSP_BASE) = bit_invert(val);
-#else
-       *((volatile u16 *)DSP_BASE) = val;
-#endif
-}
-
-static inline void dsp_reset(void)
-{
-#if defined(CONFIG_NETTA_6412)
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
-       udelay(500);
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
-       udelay(500);
-#else
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
-       udelay(250);
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
-       udelay(250);
-#endif
-}
-
-static inline u32 dsp_read_hpic_word(u32 addr)
-{
-       u32 val;
-       volatile u16 *p;
-#if defined(CONFIG_NETTA_6412)
-       p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-
-       val = ((u32) bit_invert(p[0]) << 16);
-       /* dsp_delay(); */
-
-       val |= bit_invert(p[1]);
-       /* dsp_delay(); */
-#else
-       p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-
-       val = ((u32) p[0] << 16);
-       dsp_delay();
-
-       val |= p[1];
-       dsp_delay();
-#endif
-       return val;
-}
-
-static inline u16 dsp_read_hpic_hi_hword(u32 addr)
-{
-#if defined(CONFIG_NETTA_6412)
-       return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr));
-#else
-       return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-#endif
-}
-
-static inline u16 dsp_read_hpic_lo_hword(u32 addr)
-{
-#if defined(CONFIG_NETTA_6412)
-       return bit_invert(*(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2));
-#else
-       return *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2);
-#endif
-}
-
-static inline void dsp_wait_hrdy(void)
-{
-       int i;
-
-       i = 0;
-#if defined(CONFIG_NETTA_6412)
-       while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
-#else
-       while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
-#endif
-               dsp_delay();
-               i++;
-       }
-}
-
-static inline void dsp_write_hpic_word(u32 addr, u32 val)
-{
-       volatile u16 *p;
-#if defined(CONFIG_NETTA_6412)
-       p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-       p[0] = bit_invert((u16)(val >> 16));
-       /* dsp_delay(); */
-
-       p[1] = bit_invert((u16)val);
-       /* dsp_delay(); */
-#else
-       p = (volatile u16 *)((volatile u8 *)DSP_BASE + addr);
-       p[0] = (u16)(val >> 16);
-       dsp_delay();
-
-       p[1] = (u16)val;
-       dsp_delay();
-#endif
-}
-
-static inline void dsp_write_hpic_hi_hword(u32 addr, u16 val_h)
-{
-#if defined(CONFIG_NETTA_6412)
-       *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = bit_invert(val_h);
-#else
-
-       *(volatile u16 *)((volatile u8 *)DSP_BASE + addr) = val_h;
-#endif
-}
-
-static inline void dsp_write_hpic_lo_hword(u32 addr, u16 val_l)
-{
-#if defined(CONFIG_NETTA_6412)
-       *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = bit_invert(val_l);
-#else
-       *(volatile u16 *)((volatile u8 *)DSP_BASE + addr + 2) = val_l;
-#endif
-}
-
-/********************************************************************/
-
-static inline void c62_write_word(u32 addr, u32 val)
-{
-       dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-       dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-
-       dsp_wait_hrdy();
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-       dsp_write_hpic_hi_hword(DSP_HPID2, (u16)(val >> 16));
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-
-       /* dsp_wait_hrdy();
-       dsp_delay(); */
-#endif
-       dsp_write_hpic_lo_hword(DSP_HPID2, (u16)val);
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-}
-
-static u32 c62_read_word(u32 addr)
-{
-       u32 val;
-
-       dsp_write_hpic_hi_hword(DSP_HPIA, (u16)(addr >> 16));
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-       dsp_write_hpic_lo_hword(DSP_HPIA, (u16)addr);
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-
-       /* FETCH */
-#if defined(CONFIG_NETTA_6412)
-       dsp_write_hpic_word(DSP_HPIC, 0x00100010);
-#else
-       dsp_write_hpic(0x10);
-       dsp_delay();
-#endif
-       dsp_wait_hrdy();
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-       val = (u32)dsp_read_hpic_hi_hword(DSP_HPID2) << 16;
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-
-       /* dsp_wait_hrdy();
-       dsp_delay(); */
-#endif
-       val |= dsp_read_hpic_lo_hword(DSP_HPID2);
-#if !defined(CONFIG_NETTA_6412)
-       dsp_delay();
-#endif
-       return val;
-}
-
-static inline void c62_read(u32 addr, u32 *buffer, int numdata)
-{
-       int i;
-
-       if (numdata <= 0)
-               return;
-
-       for (i = 0; i < numdata; i++) {
-               *buffer++ = c62_read_word(addr);
-               addr += 4;
-       }
-}
-
-static inline u32 c62_checksum(u32 addr, int numdata)
-{
-       int i;
-       u32 chksum;
-
-       chksum = 0;
-       for (i = 0; i < numdata; i++) {
-               chksum += c62_read_word(addr);
-               addr += 4;
-       }
-
-       return chksum;
-}
-
-static inline void c62_write(u32 addr, const u32 *buffer, int numdata)
-{
-       int i;
-
-       if (numdata <= 0)
-               return;
-
-       for (i = 0; i < numdata; i++) {
-               c62_write_word(addr, *buffer++);
-               addr += 4;
-       }
-}
-
-static inline int c62_write_word_validated(u32 addr, u32 val)
-{
-       c62_write_word(addr, val);
-       return c62_read_word(addr) == val ? 0 : -1;
-}
-
-static inline int c62_write_validated(u32 addr, const u32 *buffer, int numdata)
-{
-       int i, r;
-
-       if (numdata <= 0)
-               return 0;
-
-       for (i = 0; i < numdata; i++) {
-               r = c62_write_word_validated(addr, *buffer++);
-               if (r < 0)
-                       return r;
-               addr += 4;
-       }
-       return 0;
-}
-
-#if defined(CONFIG_NETTA_6412)
-
-#define DRAM_REGS_BASE 0x1800000
-
-#define GBLCTL DRAM_REGS_BASE
-#define CECTL1 (DRAM_REGS_BASE + 0x4)
-#define CECTL0 (DRAM_REGS_BASE + 0x8)
-#define CECTL2 (DRAM_REGS_BASE + 0x10)
-#define CECTL3 (DRAM_REGS_BASE + 0x14)
-#define SDCTL  (DRAM_REGS_BASE + 0x18)
-#define SDTIM  (DRAM_REGS_BASE + 0x1C)
-#define SDEXT  (DRAM_REGS_BASE + 0x20)
-#define SESEC1 (DRAM_REGS_BASE + 0x44)
-#define SESEC0 (DRAM_REGS_BASE + 0x48)
-#define SESEC2 (DRAM_REGS_BASE + 0x50)
-#define SESEC3 (DRAM_REGS_BASE + 0x54)
-
-#define MAR128 0x1848200
-#define MAR129 0x1848204
-
-void dsp_dram_initialize(void)
-{
-       c62_write_word(GBLCTL, 0x120E4);
-       c62_write_word(CECTL1, 0x18);
-       c62_write_word(CECTL0, 0xD0);
-       c62_write_word(CECTL2, 0x18);
-       c62_write_word(CECTL3, 0x18);
-       c62_write_word(SDCTL, 0x47115000);
-       c62_write_word(SDTIM, 1536);
-       c62_write_word(SDEXT, 0x534A9);
-#if 0
-       c62_write_word(SESEC1, 0);
-       c62_write_word(SESEC0, 0);
-       c62_write_word(SESEC2, 0);
-       c62_write_word(SESEC3, 0);
-#endif
-       c62_write_word(MAR128, 1);
-       c62_write_word(MAR129, 0);
-}
-
-#endif
-
-static inline void dsp_init_hpic(void)
-{
-       int i;
-       volatile u16 *p;
-#if defined(CONFIG_NETTA_6412)
-       dsp_go_fast();
-#else
-       dsp_go_slow();
-#endif
-       i = 0;
-#if defined(CONFIG_NETTA_6412)
-       while (i < 1000 && (dsp_read_hpic_word(DSP_HPIC) & 0x08) == 0) {
-#else
-       while (i < 1000 && (dsp_read_hpic() & 0x08) == 0) {
-#endif
-               dsp_delay();
-               i++;
-       }
-
-       if (i == 1000)
-               printf("HRDY stuck\n");
-
-       dsp_delay();
-
-       /* write control register */
-       p = (volatile u16 *)DSP_BASE;
-       p[0] = 0x0000;
-       dsp_delay();
-       p[1] = 0x0000;
-       dsp_delay();
-
-#if !defined(CONFIG_NETTA_6412)
-       dsp_go_fast();
-#endif
-}
-
-/***********************************************************************************************************/
-
-#if !defined(CONFIG_NETTA_6412)
-
-static const u8 bootstrap_rbin[5084] = {
-       0x52, 0x42, 0x49, 0x4e, 0xc5, 0xa9, 0x9f, 0x1a, 0x00, 0x00, 0x00, 0x02,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00,
-       0x00, 0x00, 0x11, 0xc0, 0x00, 0x17, 0x94, 0x2a, 0x00, 0x00, 0x00, 0x6a,
-       0x00, 0x00, 0x03, 0x62, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
-       0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
-       0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
-       0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
-       0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2,
-       0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0xe2, 0x00, 0x00, 0x60, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x29, 0x02, 0x80, 0x00, 0x6a,
-       0x03, 0x94, 0x10, 0x59, 0x00, 0x10, 0x02, 0xf4, 0x00, 0x00, 0x12, 0xaa,
-       0x00, 0x80, 0x00, 0xa8, 0x04, 0x08, 0x00, 0x28, 0x04, 0x00, 0x00, 0x68,
-       0x20, 0x03, 0xe0, 0x5b, 0x90, 0x14, 0x02, 0x64, 0x20, 0x00, 0x00, 0x12,
-       0x93, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x00, 0x00, 0x03, 0x20, 0x02, 0x65,
-       0x02, 0x19, 0x2a, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x79,
-       0x01, 0xa0, 0x36, 0x65, 0x02, 0x00, 0x00, 0x68, 0x80, 0x87, 0xe0, 0x59,
-       0x90, 0x14, 0x02, 0x75, 0x02, 0x90, 0x01, 0xa0, 0x00, 0x14, 0x02, 0x64,
-       0x00, 0x00, 0x40, 0x00, 0x03, 0x1c, 0x36, 0x74, 0x00, 0x00, 0x60, 0x78,
-       0x00, 0x14, 0x02, 0x74, 0x00, 0x19, 0x2a, 0x28, 0x00, 0x00, 0x00, 0x68,
-       0x00, 0x18, 0xe0, 0x29, 0x00, 0x00, 0x02, 0x66, 0x00, 0x00, 0x00, 0x68,
-       0x00, 0x00, 0x40, 0x00, 0x31, 0x80, 0x80, 0x59, 0x32, 0x19, 0x2e, 0x2a,
-       0x32, 0x00, 0x00, 0x6a, 0x31, 0x90, 0x02, 0xf4, 0x30, 0x02, 0x9d, 0x41,
-       0x32, 0x19, 0x30, 0x2a, 0x32, 0x00, 0x00, 0x6a, 0x30, 0x10, 0x02, 0xf4,
-       0x30, 0x00, 0x09, 0x12, 0x00, 0x00, 0x80, 0x00, 0x02, 0x80, 0x00, 0xfa,
-       0x02, 0x80, 0xc0, 0x6a, 0x03, 0x14, 0x02, 0xe6, 0x02, 0x00, 0x08, 0x2a,
-       0x00, 0x00, 0x40, 0x00, 0x02, 0x18, 0x8d, 0xfa, 0x02, 0x14, 0x02, 0xf6,
-       0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0xc0, 0x68, 0x01, 0x80, 0x02, 0x64,
-       0x00, 0x00, 0x60, 0x00, 0x01, 0x8d, 0x0d, 0xd8, 0x01, 0x80, 0x02, 0x74,
-       0x0f, 0xff, 0xf9, 0x90, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0c, 0x03, 0x62,
-       0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-};
-
-static int load_bootstrap(void)
-{
-       const u8 *s = bootstrap_rbin;
-       u32 l = sizeof(bootstrap_rbin);
-       const u8 *data, *hdr, *h;
-       u32 chksum, chksum2;
-       int i, j, rangenr;
-       u32 start, length;
-
-       if (l < 12) {
-               printf("bootstrap image corrupted. (too short header)\n");
-               return -1;
-       }
-
-       chksum  = ((u32)s[4] << 24) | ((u32)s[5] << 16) | ((u32)s[ 6] <<  8) |  (u32)s[ 7];
-       rangenr = ((u32)s[8] << 24) | ((u32)s[9] << 16) | ((u32)s[10] <<  8) |  (u32)s[11];
-       s += 12; l -= 12;
-
-       hdr = s;
-       s += 8 * rangenr; l -= 8 * rangenr;
-       data = s;
-
-       /* validate bootstrap image */
-       h = hdr; s = data; chksum2 = 0;
-       for (i = 0; i < rangenr; i++) {
-               start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
-               length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
-               h += 8;
-
-               /* too short */
-               if (l < length) {
-                       printf("bootstrap image corrupted. (too short data)\n");
-                       return -1;
-               }
-               l -= length;
-
-               j = (int)length / 4;
-               while (j-- > 0) {
-                       chksum2 += ((u32)s[0] << 24) | ((u32)s[1] << 16) | ((u32)s[2] <<  8) |  (u32)s[3];
-                       s += 4;
-               }
-       }
-
-       /* checksum must match */
-       if (chksum != chksum2) {
-               printf("bootstrap image corrupted. (checksum error)\n");
-               return -1;
-       }
-
-       /* nothing must be left */
-       if (l != 0) {
-               printf("bootstrap image corrupted. (garbage at the end)\n");
-               return -1;
-       }
-
-       /* write the image */
-       h = hdr;
-       s = data;
-       for (i = 0; i < rangenr; i++) {
-               start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
-               length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
-               h += 8;
-               c62_write(start, (u32 *)s, length / 4);
-               s += length;
-       }
-
-       /* and now validate checksum */
-       h = hdr;
-       s = data;
-       chksum2 = 0;
-       for (i = 0; i < rangenr; i++) {
-               start  = ((u32)h[0] << 24) | ((u32)h[1] << 16) | ((u32)h[2] <<  8) |  (u32)h[3];
-               length = ((u32)h[4] << 24) | ((u32)h[5] << 16) | ((u32)h[6] <<  8) |  (u32)h[7];
-               h += 8;
-               chksum2 += c62_checksum(start, length / 4);
-               s += length;
-       }
-
-       /* checksum must match */
-       if (chksum != chksum2) {
-               printf("bootstrap in DSP memory is corrupted\n");
-               return -1;
-       }
-
-       return 0;
-}
-
-struct host_init {
-       u32 master_mode;
-       struct {
-               u8 port_id;
-               u8 slot_id;
-       } ch_serial_map[32];
-       u32 clk_divider[2];
-       /* pll */
-       u32 initmode;
-       u32 pllm;
-       u32 div[4];
-       u32 oscdiv1;
-       u32 unused[10];
-};
-
-const struct host_init hi_default = {
-       .master_mode    =
-#if !defined(CONFIG_NETTA_ISDN)
-               -1,
-#else
-               0,
-#endif
-
-       .ch_serial_map  = {
-               [ 0]    = { .port_id = 2, .slot_id = 16 },
-               [ 1]    = { .port_id = 2, .slot_id = 17 },
-               [ 2]    = { .port_id = 2, .slot_id = 18 },
-               [ 3]    = { .port_id = 2, .slot_id = 19 },
-               [ 4]    = { .port_id = 2, .slot_id = 20 },
-               [ 5]    = { .port_id = 2, .slot_id = 21 },
-               [ 6]    = { .port_id = 2, .slot_id = 22 },
-               [ 7]    = { .port_id = 2, .slot_id = 23 },
-               [ 8]    = { .port_id = 2, .slot_id = 24 },
-               [ 9]    = { .port_id = 2, .slot_id = 25 },
-               [10]    = { .port_id = 2, .slot_id = 26 },
-               [11]    = { .port_id = 2, .slot_id = 27 },
-               [12]    = { .port_id = 2, .slot_id = 28 },
-               [13]    = { .port_id = 2, .slot_id = 29 },
-               [14]    = { .port_id = 2, .slot_id = 30 },
-               [15]    = { .port_id = 2, .slot_id = 31 },
-       },
-
-       /*
-          dsp_clk(xin, pllm)         = xin * pllm
-          serial_clk(xin, pllm, div) = (dsp_clk(xin, pllm) / 2) / (div + 1)
-        */
-
-       .clk_divider    = {
-               [0]     = 47,           /* must be 2048Hz */
-               [1]     = 47,
-       },
-
-       .initmode       = 1,
-       .pllm           =
-#if !defined(CONFIG_NETTA_ISDN)
-       8,              /* for =~ 25MHz 8 */
-#else
-       4,
-#endif
-       .div            = {
-               [0]     = 0x8000,
-               [1]     = 0x8000,       /* for =~ 25MHz 0x8000 */
-               [2]     = 0x8001,       /* for =~ 25MHz 0x8001 */
-               [3]     = 0x8001,       /* for =~ 25MHz 0x8001 */
-       },
-
-       .oscdiv1        = 0,
-};
-
-static void hi_write(const struct host_init *hi)
-{
-       u32 hi_buf[1 + sizeof(*hi) / sizeof(u32)];
-       u32 *s;
-       u32 chksum;
-       int i;
-
-       memset(hi_buf, 0, sizeof(hi_buf));
-
-       s = hi_buf;
-       s++;
-       *s++ = hi->master_mode;
-       for (i = 0; i < (sizeof(hi->ch_serial_map) / sizeof(hi->ch_serial_map[0])) / 2; i++)
-               *s++ = ((u32)hi->ch_serial_map[i * 2 + 1].slot_id << 24) | ((u32)hi->ch_serial_map[i * 2 + 1].port_id << 16) |
-                               ((u32)hi->ch_serial_map[i * 2 + 0].slot_id << 8) | (u32)hi->ch_serial_map[i * 2 + 0].port_id;
-
-       for (i = 0; i < sizeof(hi->clk_divider)/sizeof(hi->clk_divider[0]); i++)
-               *s++ = hi->clk_divider[i];
-
-       *s++ = hi->initmode;
-       *s++ = hi->pllm;
-       for (i = 0; i < sizeof(hi->div)/sizeof(hi->div[0]); i++)
-               *s++ = hi->div[i];
-       *s++ = hi->oscdiv1;
-
-       chksum = 0;
-       for (i = 1; i < sizeof(hi_buf)/sizeof(hi_buf[0]); i++)
-               chksum += hi_buf[i];
-       hi_buf[0] = -chksum;
-
-       c62_write(0x1000, hi_buf, sizeof(hi_buf) / sizeof(hi_buf[0]));
-}
-
-static void run_bootstrap(void)
-{
-       dsp_go_slow();
-
-       hi_write(&hi_default);
-
-       /* signal interrupt */
-       dsp_write_hpic(0x0002);
-       dsp_delay();
-
-       dsp_go_fast();
-}
-
-#endif
-
-/***********************************************************************************************************/
-
-int board_post_dsp(int flags)
-{
-       u32 ramS, ramE;
-       u32 data, data2;
-       int i, j, k;
-#if !defined(CONFIG_NETTA_6412)
-       int r;
-#endif
-       dsp_reset();
-       dsp_init_hpic();
-#if !defined(CONFIG_NETTA_6412)
-       dsp_go_slow();
-#endif
-       data = 0x11223344;
-       dsp_write_hpic_word(DSP_HPIA, data);
-       data2 = dsp_read_hpic_word(DSP_HPIA);
-       if (data2 !=   0x11223344) {
-               printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
-               goto err;
-       }
-
-       data = 0xFFEEDDCC;
-       dsp_write_hpic_word(DSP_HPIA, data);
-       data2 = dsp_read_hpic_word(DSP_HPIA);
-       if (data2 != 0xFFEEDDCC) {
-               printf("HPIA: ** ERROR; wrote 0x%08X read 0x%08X **\n", data, data2);
-               goto err;
-       }
-#if defined(CONFIG_NETTA_6412)
-       dsp_dram_initialize();
-#else
-       r = load_bootstrap();
-       if (r < 0) {
-               printf("BOOTSTRAP: ** ERROR ** failed to load\n");
-               goto err;
-       }
-
-       run_bootstrap();
-
-       dsp_go_fast();
-#endif
-       printf("    ");
-
-       /* test RAMs */
-       for (k = 0; k < sizeof(ranges)/sizeof(ranges[0]); k++) {
-
-               ramS = ranges[k].start;
-               ramE = ranges[k].start + ranges[k].size;
-
-               for (j = 0; j < 3; j++) {
-
-                       printf("\b\b\b\bR%d.%d", k, j);
-
-                       for (i = ramS; i < ramE; i += 4) {
-
-                               data = 0;
-                               switch (j) {
-                                       case 0: data = 0xAA55AA55; break;
-                                       case 1: data = 0x55AA55AA; break;
-                                       case 2: data = (u32)i;     break;
-                               }
-
-                               c62_write_word(i, data);
-                               data2 = c62_read_word(i);
-                               if (data != data2) {
-                                       printf(" ** ERROR at 0x%08X; wrote 0x%08X read 0x%08X **\n", i, data, data2);
-                                       goto err;
-                               }
-                       }
-               }
-       }
-
-       printf("\b\b\b\b    \b\b\b\bOK\n");
-#if !defined(CONFIG_NETTA_6412)
-       /* XXX assume that this works */
-       load_bootstrap();
-       run_bootstrap();
-       dsp_go_fast();
-#endif
-       return 0;
-
-err:
-       return -1;
-}
-
-int board_dsp_reset(void)
-{
-#if !defined(CONFIG_NETTA_6412)
-       int r;
-#endif
-       dsp_reset();
-       dsp_init_hpic();
-#if defined(CONFIG_NETTA_6412)
-       dsp_dram_initialize();
-#else
-       dsp_go_slow();
-       r = load_bootstrap();
-       if (r < 0)
-               return r;
-
-       run_bootstrap();
-       dsp_go_fast();
-#endif
-       return 0;
-}
diff --git a/board/netta/flash.c b/board/netta/flash.c
deleted file mode 100644 (file)
index d6902a6..0000000
+++ /dev/null
@@ -1,492 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips    */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       unsigned long size;
-       int i;
-
-       /* Init: no FLASHes known */
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-
-       size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
-       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-               printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
-       }
-
-       /* Remap FLASH according to real size */
-       memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-       memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
-       /* Re-do sizing to get full correct info */
-       size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                       CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-                       &flash_info[0]);
-
-       flash_protect ( FLAG_PROTECT_SET,
-                       CONFIG_ENV_ADDR,
-                       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-                       &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-       flash_protect ( FLAG_PROTECT_SET,
-                       CONFIG_ENV_ADDR_REDUND,
-                       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-                       &flash_info[0]);
-#endif
-
-
-       flash_info[0].size = size;
-
-       return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
-       int i;
-
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000);
-               }
-       } else if (info->flash_id & FLASH_BTYPE) {
-               /* set sector offsets for bottom boot block type    */
-               info->start[0] = base + 0x00000000;
-               info->start[1] = base + 0x00004000;
-               info->start[2] = base + 0x00006000;
-               info->start[3] = base + 0x00008000;
-               for (i = 4; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000) - 0x00030000;
-               }
-       } else {
-               /* set sector offsets for top boot block type       */
-               i = info->sector_count - 1;
-               info->start[i--] = base + info->size - 0x00004000;
-               info->start[i--] = base + info->size - 0x00006000;
-               info->start[i--] = base + info->size - 0x00008000;
-               for (; i >= 0; i--) {
-                       info->start[i] = base + i * 0x00010000;
-               }
-       }
-
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_AMD:
-               printf("AMD ");
-               break;
-       case FLASH_MAN_FUJ:
-               printf("FUJITSU ");
-               break;
-       case FLASH_MAN_MX:
-               printf("MXIC ");
-               break;
-       default:
-               printf("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM040:
-               printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM400B:
-               printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM400T:
-               printf("AM29LV400T (4 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM800B:
-               printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM800T:
-               printf("AM29LV800T (8 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM160B:
-               printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM160T:
-               printf("AM29LV160T (16 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM320B:
-               printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM320T:
-               printf("AM29LV320T (32 Mbit, top boot sector)\n");
-               break;
-       default:
-               printf("Unknown Chip Type\n");
-               break;
-       }
-
-       printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
-       printf("  Sector Start Addresses:");
-       for (i = 0; i < info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf("\n   ");
-               printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
-       }
-       printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-       short i;
-       uchar mid;
-       uchar pid;
-       vu_char *caddr = (vu_char *) addr;
-       ulong base = (ulong) addr;
-
-
-       /* Write auto select command: read Manufacturer ID */
-       caddr[0x0555] = 0xAA;
-       caddr[0x02AA] = 0x55;
-       caddr[0x0555] = 0x90;
-
-       mid = caddr[0];
-       switch (mid) {
-       case (AMD_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_AMD;
-               break;
-       case (FUJ_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_FUJ;
-               break;
-       case (MX_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_MX;
-               break;
-       case (STM_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_STM;
-               break;
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               return (0);                             /* no or unknown flash  */
-       }
-
-       pid = caddr[1];                         /* device ID        */
-       switch (pid) {
-       case (AMD_ID_LV400T & 0xFF):
-               info->flash_id += FLASH_AM400T;
-               info->sector_count = 11;
-               info->size = 0x00080000;
-               break;                                  /* => 512 kB        */
-
-       case (AMD_ID_LV400B & 0xFF):
-               info->flash_id += FLASH_AM400B;
-               info->sector_count = 11;
-               info->size = 0x00080000;
-               break;                                  /* => 512 kB        */
-
-       case (AMD_ID_LV800T & 0xFF):
-               info->flash_id += FLASH_AM800T;
-               info->sector_count = 19;
-               info->size = 0x00100000;
-               break;                                  /* => 1 MB      */
-
-       case (AMD_ID_LV800B & 0xFF):
-               info->flash_id += FLASH_AM800B;
-               info->sector_count = 19;
-               info->size = 0x00100000;
-               break;                                  /* => 1 MB      */
-
-       case (AMD_ID_LV160T & 0xFF):
-               info->flash_id += FLASH_AM160T;
-               info->sector_count = 35;
-               info->size = 0x00200000;
-               break;                                  /* => 2 MB      */
-
-       case (AMD_ID_LV160B & 0xFF):
-               info->flash_id += FLASH_AM160B;
-               info->sector_count = 35;
-               info->size = 0x00200000;
-               break;                                  /* => 2 MB      */
-
-       case (AMD_ID_LV040B & 0xFF):
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00080000;
-               break;
-
-       case (STM_ID_M29W040B & 0xFF):
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00080000;
-               break;
-
-#if 0                                                  /* enable when device IDs are available */
-       case (AMD_ID_LV320T & 0xFF):
-               info->flash_id += FLASH_AM320T;
-               info->sector_count = 67;
-               info->size = 0x00400000;
-               break;                                  /* => 4 MB      */
-
-       case (AMD_ID_LV320B & 0xFF):
-               info->flash_id += FLASH_AM320B;
-               info->sector_count = 67;
-               info->size = 0x00400000;
-               break;                                  /* => 4 MB      */
-#endif
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               return (0);                             /* => no or unknown flash */
-
-       }
-
-       printf(" ");
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000);
-               }
-       } else if (info->flash_id & FLASH_BTYPE) {
-               /* set sector offsets for bottom boot block type    */
-               info->start[0] = base + 0x00000000;
-               info->start[1] = base + 0x00004000;
-               info->start[2] = base + 0x00006000;
-               info->start[3] = base + 0x00008000;
-               for (i = 4; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000) - 0x00030000;
-               }
-       } else {
-               /* set sector offsets for top boot block type       */
-               i = info->sector_count - 1;
-               info->start[i--] = base + info->size - 0x00004000;
-               info->start[i--] = base + info->size - 0x00006000;
-               info->start[i--] = base + info->size - 0x00008000;
-               for (; i >= 0; i--) {
-                       info->start[i] = base + i * 0x00010000;
-               }
-       }
-
-       /* check for protected sectors */
-       for (i = 0; i < info->sector_count; i++) {
-               /* read sector protection: D0 = 1 if protected */
-               caddr = (volatile unsigned char *)(info->start[i]);
-               info->protect[i] = caddr[2] & 1;
-       }
-
-       /*
-        * Prevent writes to uninitialized FLASH.
-        */
-       if (info->flash_id != FLASH_UNKNOWN) {
-               caddr = (vu_char *) info->start[0];
-
-               caddr[0x0555] = 0xAA;
-               caddr[0x02AA] = 0x55;
-               caddr[0x0555] = 0xF0;
-
-               udelay(20000);
-       }
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-       vu_char *addr = (vu_char *) (info->start[0]);
-       int flag, prot, sect, l_sect;
-       ulong start, now, last;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf("- missing\n");
-               } else {
-                       printf("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       if ((info->flash_id == FLASH_UNKNOWN) ||
-           (info->flash_id > FLASH_AMD_COMP)) {
-               printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf("- Warning: %d protected sectors will not be erased!\n", prot);
-       } else {
-               printf("\n");
-       }
-
-       l_sect = -1;
-
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-       addr[0x0555] = 0x80;
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect <= s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       addr = (vu_char *) (info->start[sect]);
-                       addr[0] = 0x30;
-                       l_sect = sect;
-               }
-       }
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* wait at least 80us - let's wait 1 ms */
-       udelay(1000);
-
-       /*
-        * We wait for the last triggered sector
-        */
-       if (l_sect < 0)
-               goto DONE;
-
-       start = get_timer(0);
-       last = start;
-       addr = (vu_char *) (info->start[l_sect]);
-       while ((addr[0] & 0x80) != 0x80) {
-               if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                       printf("Timeout\n");
-                       return 1;
-               }
-               /* show that we're waiting */
-               if ((now - last) > 1000) {      /* every second */
-                       putc('.');
-                       last = now;
-               }
-       }
-
-  DONE:
-       /* reset to read mode */
-       addr = (vu_char *) info->start[0];
-       addr[0] = 0xF0;                         /* reset bank */
-
-       printf(" done\n");
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-       int rc;
-
-       while (cnt > 0) {
-               if ((rc = write_byte(info, addr++, *src++)) != 0) {
-                       return (rc);
-               }
-               --cnt;
-       }
-
-       return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
-       vu_char *addr = (vu_char *) (info->start[0]);
-       ulong start;
-       int flag;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*((vu_char *) dest) & data) != data) {
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-       addr[0x0555] = 0xA0;
-
-       *((vu_char *) dest) = data;
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* data polling for D7 */
-       start = get_timer(0);
-       while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       return (1);
-               }
-       }
-       return (0);
-}
diff --git a/board/netta/netta.c b/board/netta/netta.c
deleted file mode 100644 (file)
index 2c9c6bf..0000000
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
-               unsigned char  reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char  addr,
-               unsigned char  reg, unsigned short value);
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b)                                (1U << (31-(_b)))
-#define _BDR(_l, _h)                   (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b)                                (1U << (15-(_b)))
-#define _BWR(_l, _h)                   (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b)                                (1U << (7-(_b)))
-#define _BBR(_l, _h)                   (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b)                         _BD(_b)
-#define _BR(_l, _h)                    _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
-       printf ("Intracom NETTA"
-#if defined(CONFIG_NETTA_ISDN)
-                       " with ISDN support"
-#endif
-#if defined(CONFIG_NETTA_6412)
-                       " (DSP:TI6412)"
-#else
-                       " (DSP:TI6711)"
-#endif
-                       "\n"
-                       );
-       return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_     0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000                0x00000000
-#define CS_0001                0x10000000
-#define CS_0010                0x20000000
-#define CS_0011                0x30000000
-#define CS_0100                0x40000000
-#define CS_0101                0x50000000
-#define CS_0110                0x60000000
-#define CS_0111                0x70000000
-#define CS_1000                0x80000000
-#define CS_1001                0x90000000
-#define CS_1010                0xA0000000
-#define CS_1011                0xB0000000
-#define CS_1100                0xC0000000
-#define CS_1101                0xD0000000
-#define CS_1110                0xE0000000
-#define CS_1111                0xF0000000
-
-#define BS_0000                0x00000000
-#define BS_0001                0x01000000
-#define BS_0010                0x02000000
-#define BS_0011                0x03000000
-#define BS_0100                0x04000000
-#define BS_0101                0x05000000
-#define BS_0110                0x06000000
-#define BS_0111                0x07000000
-#define BS_1000                0x08000000
-#define BS_1001                0x09000000
-#define BS_1010                0x0A000000
-#define BS_1011                0x0B000000
-#define BS_1100                0x0C000000
-#define BS_1101                0x0D000000
-#define BS_1110                0x0E000000
-#define BS_1111                0x0F000000
-
-#define A10_AAAA       0x00000000
-#define A10_AAA0       0x00200000
-#define A10_AAA1       0x00300000
-#define A10_000A       0x00800000
-#define A10_0000       0x00A00000
-#define A10_0001       0x00B00000
-#define A10_111A       0x00C00000
-#define A10_1110       0x00E00000
-#define A10_1111       0x00F00000
-
-#define RAS_0000       0x00000000
-#define RAS_0001       0x00040000
-#define RAS_1110       0x00080000
-#define RAS_1111       0x000C0000
-
-#define CAS_0000       0x00000000
-#define CAS_0001       0x00010000
-#define CAS_1110       0x00020000
-#define CAS_1111       0x00030000
-
-#define WE_0000                0x00000000
-#define WE_0001                0x00004000
-#define WE_1110                0x00008000
-#define WE_1111                0x0000C000
-
-#define GPL4_0000      0x00000000
-#define GPL4_0001      0x00001000
-#define GPL4_1110      0x00002000
-#define GPL4_1111      0x00003000
-
-#define GPL5_0000      0x00000000
-#define GPL5_0001      0x00000400
-#define GPL5_1110      0x00000800
-#define GPL5_1111      0x00000C00
-#define LOOP           0x00000080
-
-#define EXEN           0x00000040
-
-#define AMX_COL                0x00000000
-#define AMX_ROW                0x00000020
-#define AMX_MAR                0x00000030
-
-#define NA             0x00000008
-
-#define UTA            0x00000004
-
-#define TODT           0x00000002
-
-#define LAST           0x00000001
-
-/* #define CAS_LATENCY 3 */
-#define CAS_LATENCY    2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
-       /* RSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_,
-
-       /* RBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
-       /* RSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-       /* RBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-       _NOT_USED_,
-
-       /* WBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-#endif
-
-       /* UPT */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-       /* EXC */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
-       _NOT_USED_,
-
-       /* REG */
-       CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
-       CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT         ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 8 */
-#define CONFIG_SYS_MAMR        ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
-       unsigned int i, j, v, vv;
-       volatile unsigned int *p;
-       unsigned int pv;
-
-       p = (unsigned int *)addr;
-       pv = (unsigned int)p;
-       for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
-               *p++ = pv;
-
-       p = (unsigned int *)addr;
-       for (i = 0; i < size / sizeof(unsigned int); i++) {
-               v = (unsigned int)p;
-               vv = *p;
-               if (vv != v) {
-                       printf("%p: read %08x instead of %08x\n", p, vv, v);
-                       hang();
-               }
-               p++;
-       }
-
-       for (j = 0; j < 5; j++) {
-               switch (j) {
-                       case 0: v = 0x00000000; break;
-                       case 1: v = 0xffffffff; break;
-                       case 2: v = 0x55555555; break;
-                       case 3: v = 0xaaaaaaaa; break;
-                       default:v = 0xdeadbeef; break;
-               }
-               p = (unsigned int *)addr;
-               for (i = 0; i < size / sizeof(unsigned int); i++) {
-                       *p = v;
-                       vv = *p;
-                       if (vv != v) {
-                               printf("%p: read %08x instead of %08x\n", p, vv, v);
-                               hang();
-                       }
-                       *p = ~v;
-                       p++;
-               }
-       }
-}
-
-phys_size_t initdram(int board_type)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size;
-
-       upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
-
-       /*
-        * Preliminary prescaler for refresh
-        */
-       memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
-       memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
-       /*
-        * Map controller bank 3 to the SDRAM bank at preliminary address.
-        */
-       memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-       memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
-       memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;       /* no refresh yet */
-
-       udelay(200);
-
-       /* perform SDRAM initialisation sequence */
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
-       udelay(1);
-
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
-       udelay(1);
-
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
-       udelay(1);
-
-       memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
-
-       udelay(10000);
-
-       {
-               u32 d1, d2;
-
-               d1 = 0xAA55AA55;
-               *(volatile u32 *)0 = d1;
-               d2 = *(volatile u32 *)0;
-               if (d1 != d2) {
-                       printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
-                       hang();
-               }
-
-               d1 = 0x55AA55AA;
-               *(volatile u32 *)0 = d1;
-               d2 = *(volatile u32 *)0;
-               if (d1 != d2) {
-                       printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
-                       hang();
-               }
-       }
-
-       size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
-#if 0
-       printf("check 0\n");
-       check_ram(( 0 << 20), (2 << 20));
-       printf("check 16\n");
-       check_ram((16 << 20), (2 << 20));
-       printf("check 32\n");
-       check_ram((32 << 20), (2 << 20));
-       printf("check 48\n");
-       check_ram((48 << 20), (2 << 20));
-#endif
-
-       if (size == 0) {
-               printf("SIZE is zero: LOOP on 0\n");
-               for (;;) {
-                       *(volatile u32 *)0 = 0;
-                       (void)*(volatile u32 *)0;
-               }
-       }
-
-       return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_r(void)
-{
-       return(0);
-}
-
-void reset_phys(void)
-{
-       int phyno;
-       unsigned short v;
-
-       /* reset the damn phys */
-       mii_init();
-
-       for (phyno = 0; phyno < 32; ++phyno) {
-               fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
-               if (v == 0xFFFF)
-                       continue;
-               fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
-               udelay(10000);
-               fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
-                               BMCR_RESET | BMCR_ANENABLE);
-               udelay(10000);
-       }
-}
-
-extern int board_dsp_reset(void);
-
-int last_stage_init(void)
-{
-       int r;
-
-       reset_phys();
-       r = board_dsp_reset();
-       if (r < 0)
-               printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
-       return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK   (_BWR(3) | _BWR(7, 9) | _BW(11))
-#define PA_GP_OUTMASK  (_BW(6) | _BW(10) | _BWR(12, 15))
-#define PA_SP_MASK     (_BWR(0, 2) | _BWR(4, 5))
-#define PA_ODR_VAL     0
-#define PA_GP_OUTVAL   (_BW(13) | _BWR(14, 15))
-#define PA_SP_DIRVAL   0
-
-#define PB_GP_INMASK   (_B(28) | _B(31))
-#define PB_GP_OUTMASK  (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
-#define PB_SP_MASK     (_BR(22, 25))
-#define PB_ODR_VAL     0
-#define PB_GP_OUTVAL   (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
-#define PB_SP_DIRVAL   0
-
-#define PC_GP_INMASK   (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
-#define PC_GP_OUTMASK  (_BW(6) | _BW(12))
-#define PC_SP_MASK     (_BW(4) | _BW(8))
-#define PC_SOVAL       0
-#define PC_INTVAL      _BW(7)
-#define PC_GP_OUTVAL   (_BW(6) | _BW(12))
-#define PC_SP_DIRVAL   0
-
-#define PD_GP_INMASK   0
-#define PD_GP_OUTMASK  _BWR(3, 15)
-#define PD_SP_MASK     0
-
-#if defined(CONFIG_NETTA_6412)
-
-#define PD_GP_OUTVAL   (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
-
-#else
-
-#define PD_GP_OUTVAL   (_BWR(5, 7) | _BW(9) | _BW(11))
-
-#endif
-
-#define PD_SP_DIRVAL   0
-
-int board_early_init_f(void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile iop8xx_t *ioport = &immap->im_ioport;
-       volatile cpm8xx_t *cpm = &immap->im_cpm;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-       /* CS1: NAND chip select */
-       memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
-       memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-#if !defined(CONFIG_NETTA_6412)
-       /* CS2: DSP */
-       memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
-       memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-#else
-       /* CS6: DSP */
-       memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
-       memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-#endif
-       /* CS4: External register chip select */
-       memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
-       memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
-
-       /* CS5: dummy for accurate delay */
-       memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
-       memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
-
-       ioport->iop_padat       = PA_GP_OUTVAL;
-       ioport->iop_paodr       = PA_ODR_VAL;
-       ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
-       ioport->iop_papar       = PA_SP_MASK;
-
-       cpm->cp_pbdat           = PB_GP_OUTVAL;
-       cpm->cp_pbodr           = PB_ODR_VAL;
-       cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
-       cpm->cp_pbpar           = PB_SP_MASK;
-
-       ioport->iop_pcdat       = PC_GP_OUTVAL;
-       ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
-       ioport->iop_pcso        = PC_SOVAL;
-       ioport->iop_pcint       = PC_INTVAL;
-       ioport->iop_pcpar       = PC_SP_MASK;
-
-       ioport->iop_pddat       = PD_GP_OUTVAL;
-       ioport->iop_pddir       = PD_GP_OUTMASK | PD_SP_DIRVAL;
-       ioport->iop_pdpar       = PD_SP_MASK;
-
-       /* ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7)); */
-
-       return 0;
-}
-
-#if defined(CONFIG_CMD_PCMCIA)
-
-int pcmcia_init(void)
-{
-       return 0;
-}
-
-#endif
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
-       /* XXX add here the really funky stuff */
-}
-
-#endif
diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c
deleted file mode 100644 (file)
index 3fa1925..0000000
+++ /dev/null
@@ -1,346 +0,0 @@
-#include <common.h>
-#include <mpc8xx.h>
-#include <pcmcia.h>
-
-#undef CONFIG_PCMCIA
-
-#if defined(CONFIG_CMD_PCMCIA)
-#define        CONFIG_PCMCIA
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
-#define        CONFIG_PCMCIA
-#endif
-
-#ifdef CONFIG_PCMCIA
-
-/* some sane bit macros */
-#define _BD(_b)                                (1U << (31-(_b)))
-#define _BDR(_l, _h)                   (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b)                                (1U << (15-(_b)))
-#define _BWR(_l, _h)                   (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b)                                (1U << (7-(_b)))
-#define _BBR(_l, _h)                   (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b)                         _BD(_b)
-#define _BR(_l, _h)                    _BDR(_l, _h)
-
-#define PCMCIA_BOARD_MSG "NETTA"
-
-static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) };
-
-static void cfg_vppd(int no)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask;
-
-       if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
-               return;
-
-       mask = vppd_masks[no];
-
-       immap->im_ioport.iop_papar &= ~mask;
-       immap->im_ioport.iop_paodr &= ~mask;
-       immap->im_ioport.iop_padir |=  mask;
-}
-
-static void set_vppd(int no, int what)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask;
-
-       if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
-               return;
-
-       mask = vppd_masks[no];
-
-       if (what)
-               immap->im_ioport.iop_padat |= mask;
-       else
-               immap->im_ioport.iop_padat &= ~mask;
-}
-
-static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) };
-
-static void cfg_vccd(int no)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask;
-
-       if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
-               return;
-
-       mask = vccd_masks[no];
-
-       immap->im_ioport.iop_papar &= ~mask;
-       immap->im_ioport.iop_paodr &= ~mask;
-       immap->im_ioport.iop_padir |=  mask;
-}
-
-static void set_vccd(int no, int what)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask;
-
-       if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
-               return;
-
-       mask = vccd_masks[no];
-
-       if (what)
-               immap->im_ioport.iop_padat |= mask;
-       else
-               immap->im_ioport.iop_padat &= ~mask;
-}
-
-static const unsigned short oc_mask = _BW(8);
-
-static void cfg_oc(void)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask = oc_mask;
-
-       immap->im_ioport.iop_pcdir &= ~mask;
-       immap->im_ioport.iop_pcso  &= ~mask;
-       immap->im_ioport.iop_pcint &= ~mask;
-       immap->im_ioport.iop_pcpar &= ~mask;
-}
-
-static int get_oc(void)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask = oc_mask;
-       int what;
-
-       what = !!(immap->im_ioport.iop_pcdat & mask);;
-       return what;
-}
-
-static const unsigned short shdn_mask = _BW(12);
-
-static void cfg_shdn(void)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask;
-
-       mask = shdn_mask;
-
-       immap->im_ioport.iop_papar &= ~mask;
-       immap->im_ioport.iop_paodr &= ~mask;
-       immap->im_ioport.iop_padir |=  mask;
-}
-
-static void set_shdn(int what)
-{
-       volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-       unsigned short mask;
-
-       mask = shdn_mask;
-
-       if (what)
-               immap->im_ioport.iop_padat |= mask;
-       else
-               immap->im_ioport.iop_padat &= ~mask;
-}
-
-static void cfg_ports (void)
-{
-       cfg_vppd(0); cfg_vppd(1);       /* VPPD0,VPPD1 VAVPP => Hi-Z */
-       cfg_vccd(0); cfg_vccd(1);       /* 3V and 5V off */
-       cfg_shdn();
-       cfg_oc();
-
-       /*
-        * Configure Port A for TPS2211 PC-Card Power-Interface Switch
-        *
-        * Switch off all voltages, assert shutdown
-        */
-       set_vppd(0, 1); set_vppd(1, 1);
-       set_vccd(0, 0); set_vccd(1, 0);
-       set_shdn(1);
-
-       udelay(100000);
-}
-
-int pcmcia_hardware_enable(int slot)
-{
-       volatile pcmconf8xx_t   *pcmp;
-       uint reg, pipr, mask;
-       int i;
-
-       debug ("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-       udelay(10000);
-
-       pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-
-       /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
-       cfg_ports ();
-
-       /* clear interrupt state, and disable interrupts */
-       pcmp->pcmc_pscr =  PCMCIA_MASK(_slot_);
-       pcmp->pcmc_per &= ~PCMCIA_MASK(_slot_);
-
-       /*
-        * Disable interrupts, DMA, and PCMCIA buffers
-        * (isolate the interface) and assert RESET signal
-        */
-       debug ("Disable PCMCIA buffers and assert RESET\n");
-       reg  = 0;
-       reg |= __MY_PCMCIA_GCRX_CXRESET;        /* active high */
-       reg |= __MY_PCMCIA_GCRX_CXOE;           /* active low  */
-       PCMCIA_PGCRX(_slot_) = reg;
-
-       udelay(500);
-
-       /*
-       * Make sure there is a card in the slot, then configure the interface.
-       */
-       udelay(10000);
-       debug ("[%d] %s: PIPR(%p)=0x%x\n",
-              __LINE__,__FUNCTION__,
-              &(pcmp->pcmc_pipr),pcmp->pcmc_pipr);
-       if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) {
-               printf ("   No Card found\n");
-               return (1);
-       }
-
-       /*
-        * Power On: Set VAVCC to 3.3V or 5V, set VAVPP to Hi-Z
-        */
-       mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
-       pipr = pcmp->pcmc_pipr;
-       debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
-              pipr,
-              (reg&PCMCIA_VS1(slot))?"n":"ff",
-              (reg&PCMCIA_VS2(slot))?"n":"ff");
-
-       if ((pipr & mask) == mask) {
-               set_vppd(0, 1); set_vppd(1, 1);         /* VAVPP => Hi-Z */
-               set_vccd(0, 0); set_vccd(1, 1);         /* 5V on, 3V off */
-               puts (" 5.0V card found: ");
-       } else {
-               set_vppd(0, 1); set_vppd(1, 1);         /* VAVPP => Hi-Z */
-               set_vccd(0, 1); set_vccd(1, 0);         /* 5V off, 3V on */
-               puts (" 3.3V card found: ");
-       }
-
-       /*  Wait 500 ms; use this to check for over-current */
-       for (i=0; i<5000; ++i) {
-               if (!get_oc()) {
-                       printf ("   *** Overcurrent - Safety shutdown ***\n");
-                       set_vccd(0, 0); set_vccd(1, 0);         /* VAVPP => Hi-Z */
-                       return (1);
-               }
-               udelay (100);
-       }
-
-       debug ("Enable PCMCIA buffers and stop RESET\n");
-       reg  =  PCMCIA_PGCRX(_slot_);
-       reg &= ~__MY_PCMCIA_GCRX_CXRESET;       /* active high */
-       reg &= ~__MY_PCMCIA_GCRX_CXOE;          /* active low  */
-       PCMCIA_PGCRX(_slot_) = reg;
-
-       udelay(250000); /* some cards need >150 ms to come up :-( */
-
-       debug ("# hardware_enable done\n");
-
-       return (0);
-}
-
-
-#if defined(CONFIG_CMD_PCMCIA)
-int pcmcia_hardware_disable(int slot)
-{
-       u_long reg;
-
-       debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
-
-       /* Configure PCMCIA General Control Register */
-       debug ("Disable PCMCIA buffers and assert RESET\n");
-       reg  = 0;
-       reg |= __MY_PCMCIA_GCRX_CXRESET;        /* active high */
-       reg |= __MY_PCMCIA_GCRX_CXOE;           /* active low  */
-       PCMCIA_PGCRX(_slot_) = reg;
-
-       /* All voltages off / Hi-Z */
-       set_vppd(0, 1); set_vppd(1, 1);
-       set_vccd(0, 1); set_vccd(1, 1);
-
-       udelay(10000);
-
-       return (0);
-}
-#endif
-
-
-int pcmcia_voltage_set(int slot, int vcc, int vpp)
-{
-       volatile pcmconf8xx_t   *pcmp;
-       u_long reg;
-
-       debug ("voltage_set: "
-                       PCMCIA_BOARD_MSG
-                       " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
-       'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
-
-       pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
-       /*
-        * Disable PCMCIA buffers (isolate the interface)
-        * and assert RESET signal
-        */
-       debug ("Disable PCMCIA buffers and assert RESET\n");
-       reg  = PCMCIA_PGCRX(_slot_);
-       reg |= __MY_PCMCIA_GCRX_CXRESET;        /* active high */
-       reg |= __MY_PCMCIA_GCRX_CXOE;           /* active low  */
-       PCMCIA_PGCRX(_slot_) = reg;
-       udelay(500);
-
-       /*
-        * Configure Port C pins for
-        * 5 Volts Enable and 3 Volts enable,
-        * Turn all power pins to Hi-Z
-        */
-       debug ("PCMCIA power OFF\n");
-       cfg_ports ();   /* Enables switch, but all in Hi-Z */
-
-       set_vppd(0, 1); set_vppd(1, 1);
-
-       switch(vcc) {
-       case  0:
-               break;  /* Switch off           */
-
-       case 33:
-               set_vccd(0, 1); set_vccd(1, 0);
-               break;
-
-       case 50:
-               set_vccd(0, 0); set_vccd(1, 1);
-               break;
-
-       default:
-               goto done;
-       }
-
-       /* Checking supported voltages */
-
-       debug ("PIPR: 0x%x --> %s\n",
-              pcmp->pcmc_pipr,
-              (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
-
-done:
-                       debug ("Enable PCMCIA buffers and stop RESET\n");
-       reg  =  PCMCIA_PGCRX(_slot_);
-       reg &= ~__MY_PCMCIA_GCRX_CXRESET;       /* active high */
-       reg &= ~__MY_PCMCIA_GCRX_CXOE;          /* active low  */
-       PCMCIA_PGCRX(_slot_) = reg;
-       udelay(500);
-
-       debug ("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n",
-              slot+'A');
-       return (0);
-}
-
-#endif /* CONFIG_PCMCIA */
diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds
deleted file mode 100644 (file)
index 0dff5a4..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text        :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o    (.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o    (.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug
deleted file mode 100644 (file)
index a198cf9..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)          }
-  .dynsym        : { *(.dynsym)                }
-  .dynstr        : { *(.dynstr)                }
-  .rel.text      : { *(.rel.text)              }
-  .rela.text     : { *(.rela.text)     }
-  .rel.data      : { *(.rel.data)              }
-  .rela.data     : { *(.rela.data)     }
-  .rel.rodata    : { *(.rel.rodata)    }
-  .rela.rodata   : { *(.rela.rodata)   }
-  .rel.got       : { *(.rel.got)               }
-  .rela.got      : { *(.rela.got)              }
-  .rel.ctors     : { *(.rel.ctors)     }
-  .rela.ctors    : { *(.rela.ctors)    }
-  .rel.dtors     : { *(.rel.dtors)     }
-  .rela.dtors    : { *(.rela.dtors)    }
-  .rel.bss       : { *(.rel.bss)               }
-  .rela.bss      : { *(.rela.bss)              }
-  .rel.plt       : { *(.rel.plt)               }
-  .rela.plt      : { *(.rela.plt)              }
-  .init          : { *(.init)  }
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within */
-    /* the sector layout of our flash chips!   XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc8xx/start.o            (.text)
-    common/dlmalloc.o          (.text)
-    lib/vsprintf.o     (.text)
-    lib/crc32.o                (.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/netta2/Makefile b/board/netta2/Makefile
deleted file mode 100644 (file)
index c3bfb0d..0000000
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  = netta2.o flash.o
diff --git a/board/netta2/flash.c b/board/netta2/flash.c
deleted file mode 100644 (file)
index 133f36d..0000000
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* info for FLASH chips    */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size(vu_long * addr, flash_info_t * info);
-static int write_byte(flash_info_t * info, ulong dest, uchar data);
-static void flash_get_offsets(ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init(void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       unsigned long size;
-       int i;
-
-       /* Init: no FLASHes known */
-       for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
-               flash_info[i].flash_id = FLASH_UNKNOWN;
-
-       size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
-
-       if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-                       size, size << 20);
-       }
-
-       /* Remap FLASH according to real size */
-       memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-       memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
-
-       /* Re-do sizing to get full correct info */
-       size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
-       /* monitor protection ON by default */
-       flash_protect(FLAG_PROTECT_SET,
-                       CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-                       &flash_info[0]);
-
-       flash_protect ( FLAG_PROTECT_SET,
-                       CONFIG_ENV_ADDR,
-                       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-                       &flash_info[0]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-       flash_protect ( FLAG_PROTECT_SET,
-                       CONFIG_ENV_ADDR_REDUND,
-                       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-                       &flash_info[0]);
-#endif
-
-       flash_info[0].size = size;
-
-       return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets(ulong base, flash_info_t * info)
-{
-       int i;
-
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000);
-               }
-       } else if (info->flash_id & FLASH_BTYPE) {
-               /* set sector offsets for bottom boot block type    */
-               info->start[0] = base + 0x00000000;
-               info->start[1] = base + 0x00004000;
-               info->start[2] = base + 0x00006000;
-               info->start[3] = base + 0x00008000;
-               for (i = 4; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000) - 0x00030000;
-               }
-       } else {
-               /* set sector offsets for top boot block type       */
-               i = info->sector_count - 1;
-               info->start[i--] = base + info->size - 0x00004000;
-               info->start[i--] = base + info->size - 0x00006000;
-               info->start[i--] = base + info->size - 0x00008000;
-               for (; i >= 0; i--) {
-                       info->start[i] = base + i * 0x00010000;
-               }
-       }
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info(flash_info_t * info)
-{
-       int i;
-
-       if (info->flash_id == FLASH_UNKNOWN) {
-               printf("missing or unknown FLASH type\n");
-               return;
-       }
-
-       switch (info->flash_id & FLASH_VENDMASK) {
-       case FLASH_MAN_AMD:
-               printf("AMD ");
-               break;
-       case FLASH_MAN_FUJ:
-               printf("FUJITSU ");
-               break;
-       case FLASH_MAN_MX:
-               printf("MXIC ");
-               break;
-       default:
-               printf("Unknown Vendor ");
-               break;
-       }
-
-       switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM040:
-               printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM400B:
-               printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM400T:
-               printf("AM29LV400T (4 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM800B:
-               printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM800T:
-               printf("AM29LV800T (8 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM160B:
-               printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM160T:
-               printf("AM29LV160T (16 Mbit, top boot sector)\n");
-               break;
-       case FLASH_AM320B:
-               printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
-               break;
-       case FLASH_AM320T:
-               printf("AM29LV320T (32 Mbit, top boot sector)\n");
-               break;
-       default:
-               printf("Unknown Chip Type\n");
-               break;
-       }
-
-       printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
-
-       printf("  Sector Start Addresses:");
-       for (i = 0; i < info->sector_count; ++i) {
-               if ((i % 5) == 0)
-                       printf("\n   ");
-               printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
-       }
-       printf("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size(vu_long * addr, flash_info_t * info)
-{
-       short i;
-       uchar mid;
-       uchar pid;
-       vu_char *caddr = (vu_char *) addr;
-       ulong base = (ulong) addr;
-
-       /* Write auto select command: read Manufacturer ID */
-       caddr[0x0555] = 0xAA;
-       caddr[0x02AA] = 0x55;
-       caddr[0x0555] = 0x90;
-
-       mid = caddr[0];
-       switch (mid) {
-       case (AMD_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_AMD;
-               break;
-       case (FUJ_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_FUJ;
-               break;
-       case (MX_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_MX;
-               break;
-       case (STM_MANUFACT & 0xFF):
-               info->flash_id = FLASH_MAN_STM;
-               break;
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               info->sector_count = 0;
-               info->size = 0;
-               return (0);                             /* no or unknown flash  */
-       }
-
-       pid = caddr[1];                         /* device ID        */
-       switch (pid) {
-       case (AMD_ID_LV400T & 0xFF):
-               info->flash_id += FLASH_AM400T;
-               info->sector_count = 11;
-               info->size = 0x00080000;
-               break;                                  /* => 512 kB        */
-
-       case (AMD_ID_LV400B & 0xFF):
-               info->flash_id += FLASH_AM400B;
-               info->sector_count = 11;
-               info->size = 0x00080000;
-               break;                                  /* => 512 kB        */
-
-       case (AMD_ID_LV800T & 0xFF):
-               info->flash_id += FLASH_AM800T;
-               info->sector_count = 19;
-               info->size = 0x00100000;
-               break;                                  /* => 1 MB      */
-
-       case (AMD_ID_LV800B & 0xFF):
-               info->flash_id += FLASH_AM800B;
-               info->sector_count = 19;
-               info->size = 0x00100000;
-               break;                                  /* => 1 MB      */
-
-       case (AMD_ID_LV160T & 0xFF):
-               info->flash_id += FLASH_AM160T;
-               info->sector_count = 35;
-               info->size = 0x00200000;
-               break;                                  /* => 2 MB      */
-
-       case (AMD_ID_LV160B & 0xFF):
-               info->flash_id += FLASH_AM160B;
-               info->sector_count = 35;
-               info->size = 0x00200000;
-               break;                                  /* => 2 MB      */
-
-       case (AMD_ID_LV040B & 0xFF):
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00080000;
-               break;
-
-       case (STM_ID_M29W040B & 0xFF):
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00080000;
-               break;
-
-#if 0                                                  /* enable when device IDs are available */
-       case (AMD_ID_LV320T & 0xFF):
-               info->flash_id += FLASH_AM320T;
-               info->sector_count = 67;
-               info->size = 0x00400000;
-               break;                                  /* => 4 MB      */
-
-       case (AMD_ID_LV320B & 0xFF):
-               info->flash_id += FLASH_AM320B;
-               info->sector_count = 67;
-               info->size = 0x00400000;
-               break;                                  /* => 4 MB      */
-#endif
-       default:
-               info->flash_id = FLASH_UNKNOWN;
-               return (0);                             /* => no or unknown flash */
-
-       }
-
-       printf(" ");
-       /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000);
-               }
-       } else if (info->flash_id & FLASH_BTYPE) {
-               /* set sector offsets for bottom boot block type    */
-               info->start[0] = base + 0x00000000;
-               info->start[1] = base + 0x00004000;
-               info->start[2] = base + 0x00006000;
-               info->start[3] = base + 0x00008000;
-               for (i = 4; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00010000) - 0x00030000;
-               }
-       } else {
-               /* set sector offsets for top boot block type       */
-               i = info->sector_count - 1;
-               info->start[i--] = base + info->size - 0x00004000;
-               info->start[i--] = base + info->size - 0x00006000;
-               info->start[i--] = base + info->size - 0x00008000;
-               for (; i >= 0; i--) {
-                       info->start[i] = base + i * 0x00010000;
-               }
-       }
-
-       /* check for protected sectors */
-       for (i = 0; i < info->sector_count; i++) {
-               /* read sector protection: D0 = 1 if protected */
-               caddr = (volatile unsigned char *)(info->start[i]);
-               info->protect[i] = caddr[2] & 1;
-       }
-
-       /*
-        * Prevent writes to uninitialized FLASH.
-        */
-       if (info->flash_id != FLASH_UNKNOWN) {
-               caddr = (vu_char *) info->start[0];
-
-               caddr[0x0555] = 0xAA;
-               caddr[0x02AA] = 0x55;
-               caddr[0x0555] = 0xF0;
-
-               udelay(20000);
-       }
-
-       return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase(flash_info_t * info, int s_first, int s_last)
-{
-       vu_char *addr = (vu_char *) (info->start[0]);
-       int flag, prot, sect, l_sect;
-       ulong start, now, last;
-
-       if ((s_first < 0) || (s_first > s_last)) {
-               if (info->flash_id == FLASH_UNKNOWN) {
-                       printf("- missing\n");
-               } else {
-                       printf("- no sectors to erase\n");
-               }
-               return 1;
-       }
-
-       if ((info->flash_id == FLASH_UNKNOWN) ||
-           (info->flash_id > FLASH_AMD_COMP)) {
-               printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
-               return 1;
-       }
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-
-       if (prot) {
-               printf("- Warning: %d protected sectors will not be erased!\n", prot);
-       } else {
-               printf("\n");
-       }
-
-       l_sect = -1;
-
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-       addr[0x0555] = 0x80;
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-
-       /* Start erase on unprotected sectors */
-       for (sect = s_first; sect <= s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       addr = (vu_char *) (info->start[sect]);
-                       addr[0] = 0x30;
-                       l_sect = sect;
-               }
-       }
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* wait at least 80us - let's wait 1 ms */
-       udelay(1000);
-
-       /*
-        * We wait for the last triggered sector
-        */
-       if (l_sect < 0)
-               goto DONE;
-
-       start = get_timer(0);
-       last = start;
-       addr = (vu_char *) (info->start[l_sect]);
-       while ((addr[0] & 0x80) != 0x80) {
-               if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-                       printf("Timeout\n");
-                       return 1;
-               }
-               /* show that we're waiting */
-               if ((now - last) > 1000) {      /* every second */
-                       putc('.');
-                       last = now;
-               }
-       }
-
-DONE:
-       /* reset to read mode */
-       addr = (vu_char *) info->start[0];
-       addr[0] = 0xF0;                         /* reset bank */
-
-       printf(" done\n");
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-       int rc;
-
-       while (cnt > 0) {
-               if ((rc = write_byte(info, addr++, *src++)) != 0) {
-                       return (rc);
-               }
-               --cnt;
-       }
-
-       return (0);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_byte(flash_info_t * info, ulong dest, uchar data)
-{
-       vu_char *addr = (vu_char *) (info->start[0]);
-       ulong start;
-       int flag;
-
-       /* Check if Flash is (sufficiently) erased */
-       if ((*((vu_char *) dest) & data) != data) {
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAA;
-       addr[0x02AA] = 0x55;
-       addr[0x0555] = 0xA0;
-
-       *((vu_char *) dest) = data;
-
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
-
-       /* data polling for D7 */
-       start = get_timer(0);
-       while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-               if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-                       return (1);
-               }
-       }
-       return (0);
-}
diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c
deleted file mode 100644 (file)
index 008ae67..0000000
+++ /dev/null
@@ -1,624 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#include <common.h>
-#include <miiphy.h>
-
-#include "mpc8xx.h"
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-int fec8xx_miiphy_read(char *devname, unsigned char addr,
-               unsigned char  reg, unsigned short *value);
-int fec8xx_miiphy_write(char *devname, unsigned char  addr,
-               unsigned char  reg, unsigned short value);
-
-/****************************************************************/
-
-/* some sane bit macros */
-#define _BD(_b)                                (1U << (31-(_b)))
-#define _BDR(_l, _h)                   (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
-
-#define _BW(_b)                                (1U << (15-(_b)))
-#define _BWR(_l, _h)                   (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
-
-#define _BB(_b)                                (1U << (7-(_b)))
-#define _BBR(_l, _h)                   (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
-
-#define _B(_b)                         _BD(_b)
-#define _BR(_l, _h)                    _BDR(_l, _h)
-
-/****************************************************************/
-
-/*
- * Check Board Identity:
- *
- * Return 1 always.
- */
-
-int checkboard(void)
-{
-       printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
-       return (0);
-}
-
-/****************************************************************/
-
-#define _NOT_USED_     0xFFFFFFFF
-
-/****************************************************************/
-
-#define CS_0000                0x00000000
-#define CS_0001                0x10000000
-#define CS_0010                0x20000000
-#define CS_0011                0x30000000
-#define CS_0100                0x40000000
-#define CS_0101                0x50000000
-#define CS_0110                0x60000000
-#define CS_0111                0x70000000
-#define CS_1000                0x80000000
-#define CS_1001                0x90000000
-#define CS_1010                0xA0000000
-#define CS_1011                0xB0000000
-#define CS_1100                0xC0000000
-#define CS_1101                0xD0000000
-#define CS_1110                0xE0000000
-#define CS_1111                0xF0000000
-
-#define BS_0000                0x00000000
-#define BS_0001                0x01000000
-#define BS_0010                0x02000000
-#define BS_0011                0x03000000
-#define BS_0100                0x04000000
-#define BS_0101                0x05000000
-#define BS_0110                0x06000000
-#define BS_0111                0x07000000
-#define BS_1000                0x08000000
-#define BS_1001                0x09000000
-#define BS_1010                0x0A000000
-#define BS_1011                0x0B000000
-#define BS_1100                0x0C000000
-#define BS_1101                0x0D000000
-#define BS_1110                0x0E000000
-#define BS_1111                0x0F000000
-
-#define GPL0_AAAA      0x00000000
-#define GPL0_AAA0      0x00200000
-#define GPL0_AAA1      0x00300000
-#define GPL0_000A      0x00800000
-#define GPL0_0000      0x00A00000
-#define GPL0_0001      0x00B00000
-#define GPL0_111A      0x00C00000
-#define GPL0_1110      0x00E00000
-#define GPL0_1111      0x00F00000
-
-#define GPL1_0000      0x00000000
-#define GPL1_0001      0x00040000
-#define GPL1_1110      0x00080000
-#define GPL1_1111      0x000C0000
-
-#define GPL2_0000      0x00000000
-#define GPL2_0001      0x00010000
-#define GPL2_1110      0x00020000
-#define GPL2_1111      0x00030000
-
-#define GPL3_0000      0x00000000
-#define GPL3_0001      0x00004000
-#define GPL3_1110      0x00008000
-#define GPL3_1111      0x0000C000
-
-#define GPL4_0000      0x00000000
-#define GPL4_0001      0x00001000
-#define GPL4_1110      0x00002000
-#define GPL4_1111      0x00003000
-
-#define GPL5_0000      0x00000000
-#define GPL5_0001      0x00000400
-#define GPL5_1110      0x00000800
-#define GPL5_1111      0x00000C00
-#define LOOP           0x00000080
-
-#define EXEN           0x00000040
-
-#define AMX_COL                0x00000000
-#define AMX_ROW                0x00000020
-#define AMX_MAR                0x00000030
-
-#define NA             0x00000008
-
-#define UTA            0x00000004
-
-#define TODT           0x00000002
-
-#define LAST           0x00000001
-
-#define A10_AAAA       GPL0_AAAA
-#define A10_AAA0       GPL0_AAA0
-#define A10_AAA1       GPL0_AAA1
-#define A10_000A       GPL0_000A
-#define A10_0000       GPL0_0000
-#define A10_0001       GPL0_0001
-#define A10_111A       GPL0_111A
-#define A10_1110       GPL0_1110
-#define A10_1111       GPL0_1111
-
-#define RAS_0000       GPL1_0000
-#define RAS_0001       GPL1_0001
-#define RAS_1110       GPL1_1110
-#define RAS_1111       GPL1_1111
-
-#define CAS_0000       GPL2_0000
-#define CAS_0001       GPL2_0001
-#define CAS_1110       GPL2_1110
-#define CAS_1111       GPL2_1111
-
-#define WE_0000                GPL3_0000
-#define WE_0001                GPL3_0001
-#define WE_1110                GPL3_1110
-#define WE_1111                GPL3_1111
-
-/* #define CAS_LATENCY 3  */
-#define CAS_LATENCY    2
-
-const uint sdram_table[0x40] = {
-
-#if CAS_LATENCY == 3
-       /* RSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_,
-
-       /* RBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-#endif
-
-#if CAS_LATENCY == 2
-       /* RSS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-       /* RBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-       _NOT_USED_,
-
-       /* WBS */
-       CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
-       CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
-       CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
-       CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
-       _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-#endif
-
-       /* UPT */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
-       CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_,
-
-       /* EXC */
-       CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
-       _NOT_USED_,
-
-       /* REG */
-       CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
-       CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
-};
-
-#if CONFIG_NETTA2_VERSION == 2
-static const uint nandcs_table[0x40] = {
-       /* RSS */
-       CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_0000 | GPL5_1111,
-       CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
-       CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,   /* NOP   */
-
-       /* RBS */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* WSS */
-       CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
-       CS_0000 | GPL4_1111 | GPL5_1111,
-       CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
-
-       /* WBS */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* UPT */
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-       _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
-
-       /* EXC */
-       CS_0001 | LAST,
-       _NOT_USED_,
-
-       /* REG */
-       CS_1110 ,
-       CS_0001 | LAST,
-};
-#endif
-
-/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
-/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
-#define MAR_SDRAM_INIT         ((CAS_LATENCY << 6) | 0x00000008LU)
-
-/* 8 */
-#define CONFIG_SYS_MAMR        ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-void check_ram(unsigned int addr, unsigned int size)
-{
-       unsigned int i, j, v, vv;
-       volatile unsigned int *p;
-       unsigned int pv;
-
-       p = (unsigned int *)addr;
-       pv = (unsigned int)p;
-       for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
-               *p++ = pv;
-
-       p = (unsigned int *)addr;
-       for (i = 0; i < size / sizeof(unsigned int); i++) {
-               v = (unsigned int)p;
-               vv = *p;
-               if (vv != v) {
-                       printf("%p: read %08x instead of %08x\n", p, vv, v);
-                       hang();
-               }
-               p++;
-       }
-
-       for (j = 0; j < 5; j++) {
-               switch (j) {
-                       case 0: v = 0x00000000; break;
-                       case 1: v = 0xffffffff; break;
-                       case 2: v = 0x55555555; break;
-                       case 3: v = 0xaaaaaaaa; break;
-                       default:v = 0xdeadbeef; break;
-               }
-               p = (unsigned int *)addr;
-               for (i = 0; i < size / sizeof(unsigned int); i++) {
-                       *p = v;
-                       vv = *p;
-                       if (vv != v) {
-                               printf("%p: read %08x instead of %08x\n", p, vv, v);
-                               hang();
-                       }
-                       *p = ~v;
-                       p++;
-               }
-       }
-}
-
-phys_size_t initdram(int board_type)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size;
-
-       upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
-
-       /*
-        * Preliminary prescaler for refresh
-        */
-       memctl->memc_mptpr = MPTPR_PTP_DIV8;
-
-       memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
-
-       /*
-        * Map controller bank 3 to the SDRAM bank at preliminary address.
-        */
-       memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
-       memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
-
-       memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;       /* no refresh yet */
-
-       udelay(200);
-
-       /* perform SDRAM initialisation sequence */
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
-       udelay(1);
-
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
-       udelay(1);
-
-       memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
-       udelay(1);
-
-       memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
-
-       udelay(10000);
-
-       {
-               u32 d1, d2;
-
-               d1 = 0xAA55AA55;
-               *(volatile u32 *)0 = d1;
-               d2 = *(volatile u32 *)0;
-               if (d1 != d2) {
-                       printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
-                       hang();
-               }
-
-               d1 = 0x55AA55AA;
-               *(volatile u32 *)0 = d1;
-               d2 = *(volatile u32 *)0;
-               if (d1 != d2) {
-                       printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
-                       hang();
-               }
-       }
-
-       size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
-
-       if (size == 0) {
-               printf("SIZE is zero: LOOP on 0\n");
-               for (;;) {
-                       *(volatile u32 *)0 = 0;
-                       (void)*(volatile u32 *)0;
-               }
-       }
-
-       return size;
-}
-
-/* ------------------------------------------------------------------------- */
-
-void reset_phys(void)
-{
-       int phyno;
-       unsigned short v;
-
-       udelay(10000);
-       /* reset the damn phys */
-       mii_init();
-
-       for (phyno = 0; phyno < 32; ++phyno) {
-               fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
-               if (v == 0xFFFF)
-                       continue;
-               fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
-               udelay(10000);
-               fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
-                               BMCR_RESET | BMCR_ANENABLE);
-               udelay(10000);
-       }
-}
-
-/* ------------------------------------------------------------------------- */
-
-/* GP = general purpose, SP = special purpose (on chip peripheral) */
-
-/* bits that can have a special purpose or can be configured as inputs/outputs */
-#define PA_GP_INMASK   0
-#define PA_GP_OUTMASK  (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
-#define PA_SP_MASK     0
-#define PA_ODR_VAL     0
-#define PA_GP_OUTVAL   (_BW(3) | _BW(14) | _BW(15))
-#define PA_SP_DIRVAL   0
-
-#define PB_GP_INMASK   _B(28)
-#define PB_GP_OUTMASK  (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_MASK     (_BR(22, 25))
-#define PB_ODR_VAL     0
-#define PB_GP_OUTVAL   (_B(26) | _B(27) | _B(29) | _B(30))
-#define PB_SP_DIRVAL   0
-
-#if CONFIG_NETTA2_VERSION == 1
-#define PC_GP_INMASK   _BW(12)
-#define PC_GP_OUTMASK  (_BW(10) | _BW(11) | _BW(13) | _BW(15))
-#elif CONFIG_NETTA2_VERSION == 2
-#define PC_GP_INMASK   (_BW(13) | _BW(15))
-#define PC_GP_OUTMASK  (_BW(10) | _BW(11) | _BW(12))
-#endif
-#define PC_SP_MASK     0
-#define PC_SOVAL       0
-#define PC_INTVAL      0
-#define PC_GP_OUTVAL   (_BW(10) | _BW(11))
-#define PC_SP_DIRVAL   0
-
-#if CONFIG_NETTA2_VERSION == 1
-#define PE_GP_INMASK   _B(31)
-#define PE_GP_OUTMASK  (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
-#define PE_GP_OUTVAL   (_B(20) | _B(24) | _B(27) | _B(28))
-#elif CONFIG_NETTA2_VERSION == 2
-#define PE_GP_INMASK   _BR(28, 31)
-#define PE_GP_OUTMASK  (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
-#define PE_GP_OUTVAL   (_B(20) | _B(24) | _B(27))
-#endif
-#define PE_SP_MASK     0
-#define PE_ODR_VAL     0
-#define PE_SP_DIRVAL   0
-
-int board_early_init_f(void)
-{
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       volatile iop8xx_t *ioport = &immap->im_ioport;
-       volatile cpm8xx_t *cpm = &immap->im_cpm;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-       /* NAND chip select */
-#if CONFIG_NETTA2_VERSION == 1
-       memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
-       memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
-#elif CONFIG_NETTA2_VERSION == 2
-       upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
-       memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
-       memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
-       memctl->memc_mamr = 0;  /* all clear */
-#endif
-
-       /* DSP chip select */
-       memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
-       memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
-
-#if CONFIG_NETTA2_VERSION == 1
-       memctl->memc_br4 &= ~BR_V;
-#endif
-       memctl->memc_br5 &= ~BR_V;
-       memctl->memc_br6 &= ~BR_V;
-       memctl->memc_br7 &= ~BR_V;
-
-       ioport->iop_padat       = PA_GP_OUTVAL;
-       ioport->iop_paodr       = PA_ODR_VAL;
-       ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
-       ioport->iop_papar       = PA_SP_MASK;
-
-       cpm->cp_pbdat           = PB_GP_OUTVAL;
-       cpm->cp_pbodr           = PB_ODR_VAL;
-       cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
-       cpm->cp_pbpar           = PB_SP_MASK;
-
-       ioport->iop_pcdat       = PC_GP_OUTVAL;
-       ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
-       ioport->iop_pcso        = PC_SOVAL;
-       ioport->iop_pcint       = PC_INTVAL;
-       ioport->iop_pcpar       = PC_SP_MASK;
-
-       cpm->cp_pedat           = PE_GP_OUTVAL;
-       cpm->cp_peodr           = PE_ODR_VAL;
-       cpm->cp_pedir           = PE_GP_OUTMASK | PE_SP_DIRVAL;
-       cpm->cp_pepar           = PE_SP_MASK;
-
-       return 0;
-}
-
-#ifdef CONFIG_HW_WATCHDOG
-
-void hw_watchdog_reset(void)
-{
-       /* XXX add here the really funky stuff */
-}
-
-#endif
-
-#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
-int overwrite_console(void)
-{
-       /* printf("overwrite_console called\n"); */
-       return 0;
-}
-#endif
-
-extern int drv_phone_init(void);
-extern int drv_phone_use_me(void);
-extern int drv_phone_is_idle(void);
-
-int misc_init_r(void)
-{
-       return 0;
-}
-
-int last_stage_init(void)
-{
-#if CONFIG_NETTA2_VERSION == 2
-       int i;
-#endif
-
-#if CONFIG_NETTA2_VERSION == 2
-       /* assert peripheral reset */
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
-       for (i = 0; i < 10; i++)
-               udelay(1000);
-       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
-#endif
-       reset_phys();
-
-       return 0;
-}
diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds
deleted file mode 100644 (file)
index 0dff5a4..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text        :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o    (.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o    (.text*)
-
-    *(.text*)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug
deleted file mode 100644 (file)
index a198cf9..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
-   __DYNAMIC = 0;    */
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .interp : { *(.interp) }
-  .hash          : { *(.hash)          }
-  .dynsym        : { *(.dynsym)                }
-  .dynstr        : { *(.dynstr)                }
-  .rel.text      : { *(.rel.text)              }
-  .rela.text     : { *(.rela.text)     }
-  .rel.data      : { *(.rel.data)              }
-  .rela.data     : { *(.rela.data)     }
-  .rel.rodata    : { *(.rel.rodata)    }
-  .rela.rodata   : { *(.rela.rodata)   }
-  .rel.got       : { *(.rel.got)               }
-  .rela.got      : { *(.rela.got)              }
-  .rel.ctors     : { *(.rel.ctors)     }
-  .rela.ctors    : { *(.rela.ctors)    }
-  .rel.dtors     : { *(.rel.dtors)     }
-  .rela.dtors    : { *(.rela.dtors)    }
-  .rel.bss       : { *(.rel.bss)               }
-  .rela.bss      : { *(.rela.bss)              }
-  .rel.plt       : { *(.rel.plt)               }
-  .rela.plt      : { *(.rela.plt)              }
-  .init          : { *(.init)  }
-  .plt : { *(.plt) }
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within */
-    /* the sector layout of our flash chips!   XXX FIXME XXX   */
-
-    arch/powerpc/cpu/mpc8xx/start.o            (.text)
-    common/dlmalloc.o          (.text)
-    lib/vsprintf.o     (.text)
-    lib/crc32.o                (.text)
-
-    . = env_offset;
-    common/env_embedded.o(.text)
-
-    *(.text)
-    *(.got1)
-  }
-  _etext = .;
-  PROVIDE (etext = .);
-  .rodata    :
-  {
-    *(.rodata)
-    *(.rodata1)
-    *(.rodata.str1.4)
-    *(.eh_frame)
-  }
-  .fini      : { *(.fini)    } =0
-  .ctors     : { *(.ctors)   }
-  .dtors     : { *(.dtors)   }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    *(.got)
-    _GOT2_TABLE_ = .;
-    *(.got2)
-    _FIXUP_TABLE_ = .;
-    *(.fixup)
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
-  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
-  .data    :
-  {
-    *(.data)
-    *(.data1)
-    *(.sdata)
-    *(.sdata2)
-    *(.dynamic)
-    CONSTRUCTORS
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-
-  . = ALIGN(4);
-  .u_boot_list : {
-       KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss       :
-  {
-   *(.sbss) *(.scommon)
-   *(.dynbss)
-   *(.bss)
-   *(COMMON)
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
index cedf69bef58090ee95d7eb6ccb9b2165218d2ff3..e5d565edbd16450b23bcaeb0797dea81e1c48b8a 100644 (file)
@@ -993,18 +993,6 @@ Active  powerpc     mpc8xx         -           -               ivm
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8                                 IVMS8:IVMS8_16M                                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8_128                             IVMS8:IVMS8_32M                                                                                                                   Wolfgang Denk <wd@denx.de>
 Active  powerpc     mpc8xx         -           -               ivm                 IVMS8_256                             IVMS8:IVMS8_64M                                                                                                                   Wolfgang Denk <wd@denx.de>
-Active  powerpc     mpc8xx         -           -               netphone            NETPHONE                              NETPHONE:NETPHONE_VERSION=1                                                                                                       -
-Active  powerpc     mpc8xx         -           -               netphone            NETPHONE_V2                           NETPHONE:NETPHONE_VERSION=2                                                                                                       -
-Active  powerpc     mpc8xx         -           -               netta               NETTA                                 -                                                                                                                                 -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_6412                            NETTA:NETTA_6412=1                                                                                                                -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_6412_SWAPHOOK                   NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1                                                                                               -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN                            NETTA:NETTA_ISDN=1                                                                                                                -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN_6412                       NETTA:NETTA_ISDN=1,NETTA_6412=1                                                                                                   -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN_6412_SWAPHOOK              NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1                                                                                  -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_ISDN_SWAPHOOK                   NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1                                                                                               -
-Active  powerpc     mpc8xx         -           -               netta               NETTA_SWAPHOOK                        NETTA:NETTA_SWAPHOOK=1                                                                                                            -
-Active  powerpc     mpc8xx         -           -               netta2              NETTA2                                NETTA2:NETTA2_VERSION=1                                                                                                           -
-Active  powerpc     mpc8xx         -           -               netta2              NETTA2_V2                             NETTA2:NETTA2_VERSION=2                                                                                                           -
 Active  powerpc     mpc8xx         -           -               netvia              NETVIA                                NETVIA:NETVIA_VERSION=1                                                                                                           Pantelis Antoniou <panto@intracom.gr>
 Active  powerpc     mpc8xx         -           -               netvia              NETVIA_V2                             NETVIA:NETVIA_VERSION=2                                                                                                           Pantelis Antoniou <panto@intracom.gr>
 Active  powerpc     mpc8xx         -           -               r360mpi             R360MPI                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>
index fe666a572b11c18013f778fcb8c2512175832777..c28bb52ccbc387fb969b380c0e1543d90efd0e7b 100644 (file)
@@ -11,6 +11,9 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+netphone         powerpc     mpc8xx         -           -
+netta2           powerpc     mpc8xx         -           -
+netta            powerpc     mpc8xx         -           -
 rbc823           powerpc     mpc8xx         -           -
 quantum          powerpc     mpc8xx         -           -
 RPXlite_dw       powerpc     mpc8xx         -           -
diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h
deleted file mode 100644 (file)
index 08cfc9e..0000000
+++ /dev/null
@@ -1,701 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
-#error Unsupported CONFIG_NETPHONE version
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC870          1       /* This is a MPC885 CPU         */
-#define CONFIG_NETPHONE                1       /* ...on a NetPhone board       */
-
-#define        CONFIG_SYS_TEXT_BASE    0x40000000
-
-#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE                115200  /* console baudrate = 115kbps   */
-
-/* #define CONFIG_XIN           10000000 */
-#define CONFIG_XIN              50000000
-/* #define MPC8XX_HZ           120000000 */
-#define MPC8XX_HZ               66666666
-
-#define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
-#else
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                                     \
-       "tftpboot; "                                                            \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
-       "bootm"
-
-#define CONFIG_SOURCE
-#define CONFIG_LOADS_ECHO      0       /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
-
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-
-#undef CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
-
-#define        CONFIG_STATUS_LED       1       /* Status LED enabled           */
-#define CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
-
-#define        FEC_ENET                1       /* eth.c needs it that way... */
-#undef CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII             1
-#define CONFIG_MII_INIT                1
-#define CONFIG_RMII            1       /* use RMII interface */
-
-#define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                8       /* phy address of FEC */
-#define CONFIG_FEC1_PHY_NORXERR 1
-
-#define CONFIG_ETHER_ON_FEC2   1
-#define CONFIG_FEC2_PHY                4
-#define CONFIG_FEC2_PHY_NORXERR 1
-
-#define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CDP
-
-
-#define CONFIG_BOARD_EARLY_INIT_F      1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define        CONFIG_SYS_LONGHELP                     /* undef to save memory         */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define        CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
-#else
-#define        CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
-#endif
-#define        CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define        CONFIG_SYS_MAXARGS      16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x0300000       /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
-
-#define        CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR                0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define        CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define        CONFIG_SYS_SDRAM_BASE           0x00000000
-#define CONFIG_SYS_FLASH_BASE          0x40000000
-#if defined(DEBUG)
-#define        CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
-#else
-#define        CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
-#endif
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define        CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
-#if CONFIG_NETPHONE_VERSION == 2
-#define CONFIG_SYS_FLASH_BASE4         0x40080000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS   0x80000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define        CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if CONFIG_NETPHONE_VERSION == 1
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#elif CONFIG_NETPHONE_VERSION == 2
-#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of memory banks           */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
-
-#define        CONFIG_ENV_IS_IN_FLASH  1
-#define CONFIG_ENV_SECT_SIZE   0x10000
-
-#define        CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define        CONFIG_ENV_SIZE         0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                           11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                        SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                           11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef        CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else  /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control                                11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register         11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control               11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  66666666
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register              15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK      SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CONFIG_SYS_SCCR        (/* SCCR_TBS    | */ SCCR_CRQEN | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CONFIG_SYS_SCCR        (/* SCCR_TBS    | */ SCCR_CRQEN | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define      CONFIG_SYS_DER  0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM     0x40000000      /* FLASH bank #0        */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM         0x80000000      /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1       */
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#if CONFIG_NETPHONE_VERSION == 2
-
-#define FLASH_BASE4_PRELIM     0x40080000      /* FLASH bank #1        */
-
-#define CONFIG_SYS_OR4_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR4_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR4_PRELIM  ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#endif
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM     0x00000000      /* SDRAM bank #0        */
-#define        SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)     */
-#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *     PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *     gclk      CPU clock (not bus clock!)
- *     Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_MAMR_PTA             234
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit                */
-#define CONFIG_SYS_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-#define CONFIG_LAST_STAGE_INIT         /* needed to reset the damn phys */
-
-/****************************************************************/
-
-#define DSP_SIZE       0x00010000      /* 64K */
-#define NAND_SIZE      0x00010000      /* 64K */
-
-#define DSP_BASE       0xF1000000
-#define NAND_BASE      0xF1010000
-
-/*****************************************************************************/
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*****************************************************************************/
-
-#if CONFIG_NETPHONE_VERSION == 1
-#define STATUS_LED_BIT         0x00000008              /* bit 28 */
-#elif CONFIG_NETPHONE_VERSION == 2
-#define STATUS_LED_BIT         0x00000080              /* bit 24 */
-#endif
-
-#define STATUS_LED_PERIOD      (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE       STATUS_LED_BLINKING
-
-#define STATUS_LED_ACTIVE      0               /* LED on for bit == 0  */
-#define STATUS_LED_BOOT                0               /* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-
-/* LEDs */
-
-/* led_id_t is unsigned int mask */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-       do { \
-               ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
-       } while(0)
-
-#define __led_set(_msk, _st) \
-       do { \
-               if ((_st)) \
-                       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
-               else \
-                       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
-       } while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-/***********************************************************************************************************
-
- ----------------------------------------------------------------------------------------------
-
-   (V1) version 1 of the board
-   (V2) version 2 of the board
-
- ----------------------------------------------------------------------------------------------
-
-   Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- |  #   | Name           | Type   | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
- | PA7  | DSP_INT        | Output | DSP interrupt
- | PA10 | DSP_RESET      | Output | DSP reset
- | PA14 | USBOE          | Output | USB (1)
- | PA15 | USBRXD         | Output | USB (1)
- | PB19 | BT_RTS         | Output | Bluetooth (0)
- | PB23 | BT_CTS         | Output | Bluetooth (0)
- | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
- | PB27 | SPICS_DISP     | Output | Display chip select
- | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
- | PB29 | SPI_TXD        | Output | SPI Data Tx
- | PB30 | SPI_CLK        | Output | SPI Clock
- | PC10 | DISPA0         | Output | Display A0
- | PC11 | BACKLIGHT      | Output | Display backlit
- | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
- |      | IO_RESET       | Output | (V2) General I/O reset
- | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
- |      | HOOK           | Input  | (V2) Hook input interrupt
- | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
- |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
- | PE17 | F_ALE          | Output | NAND F_ALE
- | PE18 | F_CLE          | Output | NAND F_CLE
- | PE20 | F_CE           | Output | NAND F_CE
- | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
- |      | LED            | Output | (V2) LED
- | PE27 | SPICS_ER       | Output | External serial register CS
- | PE28 | LEDIO1         | Output | (V1) LED
- |      | BKBR1          | Input  | (V2) Keyboard input scan
- | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
- |      | BKBR2          | Input  | (V2) Keyboard input scan
- | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
- |      | BKBR3          | Input  | (V2) Keyboard input scan
- | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
- |      | BKBR4          | Input  | (V2) Keyboard input scan
- +------+----------------+--------+---------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
-   Serial register input:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- |    0 | BKBR1          | (V1) Keyboard input scan
- |    1 | BKBR3          | (V1) Keyboard input scan
- |    2 | BKBR4          | (V1) Keyboard input scan
- |    3 | BKBR2          | (V1) Keyboard input scan
- |    4 | HOOK           | (V1) Hook switch
- |    5 | BT_LINK        | (V1) Bluetooth link status
- |    6 | HOST_WAKE      | (V1) Bluetooth host wake up
- |    7 | OK_ETH         | (V1) Cisco inline power OK status
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
-   Serial register output:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- |    0 | KEY1           | Keyboard output scan
- |    1 | KEY2           | Keyboard output scan
- |    2 | KEY3           | Keyboard output scan
- |    3 | KEY4           | Keyboard output scan
- |    4 | KEY5           | Keyboard output scan
- |    5 | KEY6           | Keyboard output scan
- |    6 | KEY7           | Keyboard output scan
- |    7 | BT_WAKE        | Bluetooth wake up
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | CS0  | CS0            | Boot flash
- | CS1  | CS_FLASH       | NAND flash
- | CS2  | CS_DSP         | DSP
- | CS3  | DCS_DRAM       | DRAM
- | CS4  | CS_FLASH2      | (V2) 2nd flash
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | IRQ_DSP        | DSP interrupt
- | IRQ3 | S_INTER        | DUSLIC ???
- | IRQ4 | F_RY_BY        | NAND
- | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts on PCMCIA pins:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
- | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
- | IP_A2| RMII1_MDINT    | PHY interrupt for #1
- | IP_A3| RMII2_MDINT    | PHY interrupt for #2
- | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
- | IP_A6| OK_ETH         | (V2) Cisco inline power OK
- +------+----------------+------------------------------------------------------------
-
-*************************************************************************************************/
-
-#define CONFIG_SED156X                 1       /* use SED156X */
-#define CONFIG_SED156X_PG12864Q                1       /* type of display used */
-
-/* serial interfacing macros */
-
-#define SED156X_SPI_RXD_PORT   (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_RXD_MASK   0x00000008
-
-#define SED156X_SPI_TXD_PORT   (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_TXD_MASK   0x00000004
-
-#define SED156X_SPI_CLK_PORT   (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_SPI_CLK_MASK   0x00000002
-
-#define SED156X_CS_PORT                (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
-#define SED156X_CS_MASK                0x00000010
-
-#define SED156X_A0_PORT                (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
-#define SED156X_A0_MASK                0x0020
-
-/*************************************************************************************************/
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV           1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE   1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE       1
-
-/*************************************************************************************************/
-
-/* use board specific hardware */
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_SHOW_ACTIVITY
-
-/*************************************************************************************************/
-
-/* phone console configuration */
-
-#define PHONE_CONSOLE_POLL_HZ          (CONFIG_SYS_HZ/200)     /* poll every 5ms */
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID           20
-#define CONFIG_CDP_DEVICE_ID_PREFIX    "NP"    /* netphone */
-#define CONFIG_CDP_PORT_ID             "eth%d"
-#define CONFIG_CDP_CAPABILITIES                0x00000010
-#define CONFIG_CDP_VERSION             "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
-#define CONFIG_CDP_PLATFORM            "Intracom NetPhone"
-#define CONFIG_CDP_TRIGGER             0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION   4300    /* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01    /* ipphone */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE   1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY    1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE      1
-
-/*************************************************************************************************/
-#endif /* __CONFIG_H */
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
deleted file mode 100644 (file)
index 800a922..0000000
+++ /dev/null
@@ -1,666 +0,0 @@
-/*
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC885          1       /* This is a MPC885 CPU         */
-#define CONFIG_NETTA           1       /* ...on a NetTA board          */
-
-#define        CONFIG_SYS_TEXT_BASE    0x40000000
-
-#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE                115200  /* console baudrate = 115kbps   */
-
-/* #define CONFIG_XIN           10000000 */
-#define CONFIG_XIN              50000000
-#define MPC8XX_HZ              120000000
-/* #define MPC8XX_HZ           100000000 */
-/* #define MPC8XX_HZ            50000000 */
-/* #define MPC8XX_HZ            80000000 */
-
-#define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
-#else
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                                     \
-       "tftpboot; "                                                            \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"    \
-       "bootm"
-
-#define CONFIG_LOADS_ECHO      0       /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
-
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-#define CONFIG_HW_WATCHDOG
-
-#undef CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
-
-#define        FEC_ENET                1       /* eth.c needs it that way... */
-#undef  CONFIG_SYS_DISCOVER_PHY                /* do not discover phys */
-#define CONFIG_MII             1
-#define CONFIG_MII_INIT                1
-#define CONFIG_RMII            1       /* use RMII interface */
-
-#if defined(CONFIG_NETTA_ISDN)
-#define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                1       /* phy address of FEC1 */
-#define CONFIG_FEC1_PHY_NORXERR 1
-#undef  CONFIG_ETHER_ON_FEC2
-#else
-#define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                8       /* phy address of FEC1 */
-#define CONFIG_FEC1_PHY_NORXERR 1
-#define CONFIG_ETHER_ON_FEC2   1
-#define CONFIG_FEC2_PHY                1       /* phy address of FEC2 */
-#define CONFIG_FEC2_PHY_NORXERR 1
-#endif
-
-#define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
-
-/* POST support */
-#define CONFIG_POST            (CONFIG_SYS_POST_MEMORY   | \
-                                CONFIG_SYS_POST_CODEC     | \
-                                CONFIG_SYS_POST_DSP       )
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCMCIA
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOARD_EARLY_INIT_F      1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define        CONFIG_SYS_LONGHELP                     /* undef to save memory         */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define        CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
-#else
-#define        CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
-#endif
-#define        CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define        CONFIG_SYS_MAXARGS      16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x0300000       /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
-
-#define        CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR                0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define        CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define        CONFIG_SYS_SDRAM_BASE           0x00000000
-#define CONFIG_SYS_FLASH_BASE          0x40000000
-#if defined(DEBUG)
-#define        CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
-#else
-#define        CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
-#endif
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define        CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define        CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#define CONFIG_SYS_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
-
-#define        CONFIG_ENV_IS_IN_FLASH  1
-#define CONFIG_ENV_SECT_SIZE   0x10000
-
-#define        CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define        CONFIG_ENV_SIZE         0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                           11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                        SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                           11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef        CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else  /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control                                11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register         11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control               11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  80000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  50000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register              15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK      SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CONFIG_SYS_SCCR        (/* SCCR_TBS    | */ SCCR_CRQEN | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CONFIG_SYS_SCCR        (/* SCCR_TBS    | */ SCCR_CRQEN | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define      CONFIG_SYS_DER  0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM     0x40000000      /* FLASH bank #0        */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM         0x80000000      /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1       */
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM     0x00000000      /* SDRAM bank #0        */
-#define        SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)     */
-#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *     PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *     gclk      CPU clock (not bus clock!)
- *     Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#if   MPC8XX_HZ == 120000000
-#define CONFIG_SYS_MAMR_PTA             234
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_MAMR_PTA             195
-#elif MPC8XX_HZ ==  80000000
-#define CONFIG_SYS_MAMR_PTA             156
-#elif MPC8XX_HZ ==  50000000
-#define CONFIG_SYS_MAMR_PTA              98
-#else
-#error Unknown frequency
-#endif
-
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit                */
-#define CONFIG_SYS_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-#define CONFIG_LAST_STAGE_INIT         /* needed to reset the damn phys */
-
-/***********************************************************************************************************
-
-   Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- |  #   | Name           | Type   | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3  | OK_ETH_3V      | Input  | CISCO Ethernet power OK
- |      |                |        | (NetRoute: FEC1, TA: FEC2) (0=power OK)
- | PA6  | P_VCCD1        | Output | TPS2211A PCMCIA
- | PA7  | DCL1_3V        | Periph | IDL1 PCM clock
- | PA8  | DSP_DR1        | Periph | IDL1 PCM Data Rx
- | PA9  | L1TXDA         | Periph | IDL1 PCM Data Tx
- | PA10 | P_VCCD0        | Output | TPS2211A PCMCIA
- | PA12 | P_SHDN         | Output | TPS2211A PCMCIA
- | PA13 | ETH_LOOP       | Output | CISCO Loopback remote power
- |      |                |        | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
- | PA14 | P_VPPD0        | Output | TPS2211A PCMCIA
- | PA15 | P_VPPD1        | Output | TPS2211A PCMCIA
- | PB14 | SPIEN_FXO      | Output | SPI CS for FXO daughter-board
- | PB15 | SPIEN_S1       | Output | SPI CS for S-interface 1 (NetRoute only)
- | PB16 | DREQ1          | Output | D channel request for S-interface chip 1.
- | PB17 | L1ST3          | Periph | IDL1 timeslot enable signal for PPC
- | PB18 | L1ST2          | Periph | IDL1 timeslot enable signal for PPC
- | PB19 | SPIEN_S2       | Output | SPI CS for S-interface 2 (NetRoute only)
- | PB20 | SPIEN_SEEPROM  | Output | SPI CS for serial eeprom
- | PB21 | LEDIO          | Output | Led mode indication for PHY
- | PB22 | UART_CTS       | Input  | UART CTS
- | PB23 | UART_RTS       | Output | UART RTS
- | PB24 | UART_RX        | Periph | UART Data Rx
- | PB25 | UART_TX        | Periph | UART Data Tx
- | PB26 | RMII-MDC       | Periph | Free for future use (MII mgt clock)
- | PB27 | RMII-MDIO      | Periph | Free for future use (MII mgt data)
- | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
- | PB29 | SPI_TXD        | Output | SPI Data Tx
- | PB30 | SPI_CLK        | Output | SPI Clock
- | PB31 | RMII1-REFCLK   | Periph | RMII reference clock for FEC1
- | PC4  | PHY1_LINK      | Input  | PHY link state FEC1 (interrupt)
- | PC5  | PHY2_LINK      | Input  | PHY link state FEC2 (interrupt)
- | PC6  | RMII1-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
- | PC7  | RMII2-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
- | PC8  | P_OC           | Input  | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
- | PC9  | COM_HOOK1      | Input  | Codec interrupt chip #1 (interrupt)
- | PC10 | COM_HOOK2      | Input  | Codec interrupt chip #2 (interrupt)
- | PC11 | COM_HOOK4      | Input  | Codec interrupt chip #4 (interrupt)
- | PC12 | COM_HOOK3      | Input  | Codec interrupt chip #3 (interrupt)
- | PC13 | F_RY_BY        | Input  | NAND ready signal (interrupt)
- | PC14 | FAN_OK         | Input  | Fan status signal (interrupt) (1=OK)
- | PC15 | PC15_DIRECT0   | Periph | PCMCIA DMA request.
- | PD3  | F_ALE          | Output | NAND
- | PD4  | F_CLE          | Output | NAND
- | PD5  | F_CE           | Output | NAND
- | PD6  | DSP_INT        | Output | DSP debug interrupt
- | PD7  | DSP_RESET      | Output | DSP reset
- | PD8  | RMII_MDC       | Periph | MII mgt clock
- | PD9  | SPIEN_C1       | Output | SPI CS for codec #1
- | PD10 | SPIEN_C2       | Output | SPI CS for codec #2
- | PD11 | SPIEN_C3       | Output | SPI CS for codec #3
- | PD12 | FSC2           | Periph | IDL2 frame sync
- | PD13 | DGRANT2        | Input  | D channel grant from S #2
- | PD14 | SPIEN_C4       | Output | SPI CS for codec #4
- | PD15 | TP700          | Output | Testpoint for software debugging
- | PE14 | RMII2-TXD0     | Periph | FEC2 transmit data
- | PE15 | RMII2-TXD1     | Periph | FEC2 transmit data
- | PE16 | RMII2-REFCLK   | Periph | TA: RMII ref clock for
- |      | DCL2           | Periph | NetRoute: PCM clock #2
- | PE17 | TP703          | Output | Testpoint for software debugging
- | PE18 | DGRANT1        | Input  |  D channel grant from S #1
- | PE19 | RMII2-TXEN     | Periph | TA: FEC2 tx enable
- |      | PCM2OUT        | Periph | NetRoute: Tx data for IDL2
- | PE20 | FSC1           | Periph | IDL1 frame sync
- | PE21 | RMII2-RXD0     | Periph | FEC2 receive data
- | PE22 | RMII2-RXD1     | Periph | FEC2 receive data
- | PE23 | L1ST1          | Periph | IDL1 timeslot enable signal for PPC
- | PE24 | U-N1           | Output | Select user/network for S #1 (0=user)
- | PE25 | U-N2           | Output | Select user/network for S #2 (0=user)
- | PE26 | RMII2-RXDV     | Periph | FEC2 valid
- | PE27 | DREQ2          | Output | D channel request for S #2.
- | PE28 | FPGA_DONE      | Input  | FPGA done signal
- | PE29 | FPGA_INIT      | Output | FPGA init signal
- | PE30 | UDOUT2_3V      | Input  | IDL2 PCM input
- | PE31 |                |        | Free
- +------+----------------+--------+---------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | CS0  | CS0            | Boot flash
- | CS1  | CS_FLASH       | NAND flash
- | CS2  | CS_DSP         | DSP
- | CS3  | DCS_DRAM       | DRAM
- | CS4  | CS_ER1         | External output register
- +------+----------------+------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | UINTER_3V      | S interrupt chips interrupt (common)
- | IRQ3 | IRQ_DSP        | DSP interrupt
- | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
- +------+----------------+------------------------------------------------------------
-
-*************************************************************************************************/
-
-#define DSP_SIZE       0x00010000      /* 64K */
-#define NAND_SIZE      0x00010000      /* 64K */
-#define ER_SIZE                0x00010000      /* 64K */
-#define DUMMY_SIZE     0x00010000      /* 64K */
-
-#define DSP_BASE       0xF1000000
-#define NAND_BASE      0xF1010000
-#define ER_BASE                0xF1020000
-#define DUMMY_BASE     0xF1FF0000
-
-/*****************************************************************************/
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_SYS_DIRECT_NAND_TFTP
-
-/*****************************************************************************/
-
-#if 1
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR     (0xE0000000)
-#define CONFIG_SYS_PCMCIA_MEM_SIZE     ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_DMA_ADDR     (0xE4000000)
-#define CONFIG_SYS_PCMCIA_DMA_SIZE     ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_ATTRB_ADDR   (0xE8000000)
-#define CONFIG_SYS_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
-#define CONFIG_SYS_PCMCIA_IO_ADDR      (0xEC000000)
-#define CONFIG_SYS_PCMCIA_IO_SIZE      ( 64 << 20 )
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_IDE_PREINIT     1       /* Use preinit IDE hook */
-#define        CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
-
-#undef CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
-#undef CONFIG_IDE_LED                  /* LED   for ide not supported  */
-#undef CONFIG_IDE_RESET                /* reset for ide not supported  */
-
-#define CONFIG_SYS_IDE_MAXBUS          1       /* max. 1 IDE bus               */
-#define CONFIG_SYS_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
-
-#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR
-
-/* Offset for data I/O                 */
-#define CONFIG_SYS_ATA_DATA_OFFSET     (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET      (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
-
-/* Offset for alternate registers      */
-#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#endif
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID           20
-#define CONFIG_CDP_DEVICE_ID_PREFIX    "NT"    /* netta */
-#define CONFIG_CDP_PORT_ID             "eth%d"
-#define CONFIG_CDP_CAPABILITIES                0x00000010
-#define CONFIG_CDP_VERSION             "u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
-#define CONFIG_CDP_PLATFORM            "Intracom NetTA"
-#define CONFIG_CDP_TRIGGER             0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION   4300    /* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01    /* ipphone? */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE   1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY    1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE      1
-
-/*************************************************************************************************/
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h
deleted file mode 100644 (file)
index 55ae4b5..0000000
+++ /dev/null
@@ -1,654 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
- * U-Boot port on NetTA4 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
-#error Unsupported CONFIG_NETTA2 version
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC870          1       /* This is a MPC885 CPU         */
-#define CONFIG_NETTA2          1       /* ...on a NetTA2 board         */
-
-#define        CONFIG_SYS_TEXT_BASE    0x40000000
-
-#define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
-#undef CONFIG_8xx_CONS_SMC2
-#undef CONFIG_8xx_CONS_NONE
-
-#define CONFIG_BAUDRATE                115200  /* console baudrate = 115kbps   */
-
-/* #define CONFIG_XIN           10000000 */
-#define CONFIG_XIN              50000000
-/* #define MPC8XX_HZ           120000000 */
-#define MPC8XX_HZ               66666666
-
-#define CONFIG_8xx_GCLK_FREQ   MPC8XX_HZ
-
-#if 0
-#define CONFIG_BOOTDELAY       -1      /* autoboot disabled            */
-#else
-#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
-#endif
-
-#undef CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
-
-#define CONFIG_PREBOOT "echo;"
-
-#undef CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND                                                     \
-       "tftpboot; "                                                            \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
-       "bootm"
-
-#define CONFIG_SOURCE
-#define CONFIG_LOADS_ECHO      0       /* echo off for serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
-
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-
-#undef CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
-
-#define        CONFIG_STATUS_LED       1       /* Status LED enabled           */
-#define CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_NISDOMAIN
-
-
-#undef CONFIG_MAC_PARTITION
-#undef CONFIG_DOS_PARTITION
-
-#define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
-
-#define        FEC_ENET                1       /* eth.c needs it that way... */
-#undef CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII             1
-#define CONFIG_MII_INIT                1
-#define CONFIG_RMII            1       /* use RMII interface */
-
-#define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                8       /* phy address of FEC */
-#define CONFIG_FEC1_PHY_NORXERR 1
-
-#define CONFIG_ETHER_ON_FEC2   1
-#define CONFIG_FEC2_PHY                4
-#define CONFIG_FEC2_PHY_NORXERR 1
-
-#define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_CDP
-
-
-#define CONFIG_BOARD_EARLY_INIT_F      1
-#define CONFIG_MISC_INIT_R
-
-/*
- * Miscellaneous configurable options
- */
-#define        CONFIG_SYS_LONGHELP                     /* undef to save memory         */
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#if defined(CONFIG_CMD_KGDB)
-#define        CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
-#else
-#define        CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
-#endif
-#define        CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define        CONFIG_SYS_MAXARGS      16              /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START       0x0300000       /* memtest works on     */
-#define CONFIG_SYS_MEMTEST_END         0x0700000       /* 3 ... 7 MB in DRAM   */
-
-#define        CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR                0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define        CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define        CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define        CONFIG_SYS_SDRAM_BASE           0x00000000
-#define CONFIG_SYS_FLASH_BASE          0x40000000
-#if defined(DEBUG)
-#define        CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
-#else
-#define        CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
-#endif
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
-#define        CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
-#if CONFIG_NETTA2_VERSION == 2
-#define CONFIG_SYS_FLASH_BASE4         0x40080000
-#endif
-
-#define CONFIG_SYS_RESET_ADDRESS   0x80000000
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define        CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#if CONFIG_NETTA2_VERSION == 1
-#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* max number of memory banks           */
-#elif CONFIG_NETTA2_VERSION == 2
-#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of memory banks           */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT      8       /* max number of sectors on one chip    */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
-
-#define        CONFIG_ENV_IS_IN_FLASH  1
-#define CONFIG_ENV_SECT_SIZE   0x10000
-
-#define        CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x60000)
-#define CONFIG_ENV_OFFSET              0
-#define        CONFIG_ENV_SIZE         0x4000
-
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
-#define CONFIG_ENV_OFFSET_REDUND       0
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
-#endif
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control                           11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                        SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
-#endif
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration                           11-6
- *-----------------------------------------------------------------------
- * PCMCIA config., multi-function pin tri-state
- */
-#ifndef        CONFIG_CAN_DRIVER
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#else  /* we must activate GPL5 in the SIUMCR for CAN */
-#define CONFIG_SYS_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control                                11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
-
-/*-----------------------------------------------------------------------
- * RTCSC - Real-Time Clock Status and Control Register         11-27
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control               11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR       (PISCR_PS | PISCR_PITF)
-
-/*-----------------------------------------------------------------------
- * PLPRCR - PLL, Low-Power, and Reset Control Register         15-30
- *-----------------------------------------------------------------------
- * Reset PLL lock status sticky bit, timer expired status bit and timer
- * interrupt status bit
- *
- */
-
-#if CONFIG_XIN == 10000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 50000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 25000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 40000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 75000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 10MHz
-#endif
-
-#elif CONFIG_XIN == 50000000
-
-#if MPC8XX_HZ == 120000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ == 100000000
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#elif MPC8XX_HZ ==  66666666
-#define CONFIG_SYS_PLPRCR      ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
-                        (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
-#else
-#error unsupported CPU freq for XIN = 50MHz
-#endif
-
-#else
-
-#error unsupported XIN freq
-#endif
-
-
-/*
- *-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register              15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- *
- * Note: When TBS == 0 the timebase is independent of current cpu clock.
- */
-
-#define SCCR_MASK      SCCR_EBDF11
-#if MPC8XX_HZ > 66666666
-#define CONFIG_SYS_SCCR        (/* SCCR_TBS     | */ SCCR_CRQEN | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00 | SCCR_EBDF01)
-#else
-#define CONFIG_SYS_SCCR        (/* SCCR_TBS     | */ SCCR_CRQEN | \
-                        SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-                        SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
-                        SCCR_DFALCD00)
-#endif
-
-/*-----------------------------------------------------------------------
- *
- *-----------------------------------------------------------------------
- *
- */
-/*#define      CONFIG_SYS_DER  0x2002000F*/
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM     0x40000000      /* FLASH bank #0        */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM         0x80000000      /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
-
-/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1       */
-#define CONFIG_SYS_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
-
-#define CONFIG_SYS_OR0_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#if CONFIG_NETTA2_VERSION == 2
-
-#define FLASH_BASE4_PRELIM     0x40080000      /* FLASH bank #1        */
-
-#define CONFIG_SYS_OR4_REMAP   (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_OR4_PRELIM  (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
-#define CONFIG_SYS_BR4_PRELIM  ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
-
-#endif
-
-/*
- * BR3 and OR3 (SDRAM)
- *
- */
-#define SDRAM_BASE3_PRELIM     0x00000000      /* SDRAM bank #0        */
-#define        SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)     */
-#define CONFIG_SYS_OR_TIMING_SDRAM     (OR_CSNT_SAM | OR_G5LS)
-
-#define CONFIG_SYS_OR3_PRELIM  ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
-#define CONFIG_SYS_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
-
-/*
- * Memory Periodic Timer Prescaler
- */
-
-/*
- * Memory Periodic Timer Prescaler
- *
- * The Divider for PTA (refresh timer) configuration is based on an
- * example SDRAM configuration (64 MBit, one bank). The adjustment to
- * the number of chip selects (NCS) and the actually needed refresh
- * rate is done by setting MPTPR.
- *
- * PTA is calculated from
- *     PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
- *
- *     gclk      CPU clock (not bus clock!)
- *     Trefresh  Refresh cycle * 4 (four word bursts used)
- *
- * 4096  Rows from SDRAM example configuration
- * 1000  factor s -> ms
- *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
- *    4  Number of refresh cycles per period
- *   64  Refresh cycle in ms per number of rows
- * --------------------------------------------
- * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
- *
- * 50 MHz => 50.000.000 / Divider =  98
- * 66 Mhz => 66.000.000 / Divider = 129
- * 80 Mhz => 80.000.000 / Divider = 156
- */
-
-#define CONFIG_SYS_MAMR_PTA             234
-
-/*
- * For 16 MBit, refresh rates could be 31.3 us
- * (= 64 ms / 2K = 125 / quad bursts).
- * For a simpler initialization, 15.6 us is used instead.
- *
- * #define CONFIG_SYS_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
- * #define CONFIG_SYS_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
- */
-#define CONFIG_SYS_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit                */
-#define CONFIG_SYS_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
-#define CONFIG_SYS_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
-
-/*
- * MAMR settings for SDRAM
- */
-
-/* 8 column SDRAM */
-#define CONFIG_SYS_MAMR_8COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-/* 9 column SDRAM */
-#define CONFIG_SYS_MAMR_9COL   ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
-                        MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-
-#define CONFIG_LAST_STAGE_INIT         /* needed to reset the damn phys */
-
-/****************************************************************/
-
-#define DSP_SIZE       0x00010000      /* 64K */
-#define NAND_SIZE      0x00010000      /* 64K */
-
-#define DSP_BASE       0xF1000000
-#define NAND_BASE      0xF1010000
-
-/*****************************************************************************/
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*****************************************************************************/
-
-#if CONFIG_NETTA2_VERSION == 1
-#define STATUS_LED_BIT         0x00000008              /* bit 28 */
-#elif CONFIG_NETTA2_VERSION == 2
-#define STATUS_LED_BIT         0x00000080              /* bit 24 */
-#endif
-
-#define STATUS_LED_PERIOD      (CONFIG_SYS_HZ / 2)
-#define STATUS_LED_STATE       STATUS_LED_BLINKING
-
-#define STATUS_LED_ACTIVE      0               /* LED on for bit == 0  */
-#define STATUS_LED_BOOT                0               /* LED 0 used for boot status */
-
-#ifndef __ASSEMBLY__
-
-/* LEDs */
-
-/* led_id_t is unsigned int mask */
-typedef unsigned int led_id_t;
-
-#define __led_toggle(_msk) \
-       do { \
-               ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
-       } while(0)
-
-#define __led_set(_msk, _st) \
-       do { \
-               if ((_st)) \
-                       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
-               else \
-                       ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
-       } while(0)
-
-#define __led_init(msk, st) __led_set(msk, st)
-
-#endif
-
-/***********************************************************************************************************
-
- ----------------------------------------------------------------------------------------------
-
-   (V1) version 1 of the board
-   (V2) version 2 of the board
-
- ----------------------------------------------------------------------------------------------
-
-   Pin definitions:
-
- +------+----------------+--------+------------------------------------------------------------
- |  #   | Name           | Type   | Comment
- +------+----------------+--------+------------------------------------------------------------
- | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
- | PA7  | DSP_INT        | Output | DSP interrupt
- | PA10 | DSP_RESET      | Output | DSP reset
- | PA14 | USBOE          | Output | USB (1)
- | PA15 | USBRXD         | Output | USB (1)
- | PB19 | BT_RTS         | Output | Bluetooth (0)
- | PB23 | BT_CTS         | Output | Bluetooth (0)
- | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
- | PB27 | SPICS_DISP     | Output | Display chip select
- | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
- | PB29 | SPI_TXD        | Output | SPI Data Tx
- | PB30 | SPI_CLK        | Output | SPI Clock
- | PC10 | DISPA0         | Output | Display A0
- | PC11 | BACKLIGHT      | Output | Display backlit
- | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
- |      | IO_RESET       | Output | (V2) General I/O reset
- | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
- |      | HOOK           | Input  | (V2) Hook input interrupt
- | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
- |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
- | PE17 | F_ALE          | Output | NAND F_ALE
- | PE18 | F_CLE          | Output | NAND F_CLE
- | PE20 | F_CE           | Output | NAND F_CE
- | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
- |      | LED            | Output | (V2) LED
- | PE27 | SPICS_ER       | Output | External serial register CS
- | PE28 | LEDIO1         | Output | (V1) LED
- |      | BKBR1          | Input  | (V2) Keyboard input scan
- | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
- |      | BKBR2          | Input  | (V2) Keyboard input scan
- | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
- |      | BKBR3          | Input  | (V2) Keyboard input scan
- | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
- |      | BKBR4          | Input  | (V2) Keyboard input scan
- +------+----------------+--------+---------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
-   Serial register input:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- |    4 | HOOK           | Hook switch
- |    5 | BT_LINK        | Bluetooth link status
- |    6 | HOST_WAKE      | Bluetooth host wake up
- |    7 | OK_ETH         | Cisco inline power OK status
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Chip selects:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | CS0  | CS0            | Boot flash
- | CS1  | CS_FLASH       | NAND flash
- | CS2  | CS_DSP         | DSP
- | CS3  | DCS_DRAM       | DRAM
- | CS4  | CS_FLASH2      | (V2) 2nd flash
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IRQ1 | IRQ_DSP        | DSP interrupt
- | IRQ3 | S_INTER        | DUSLIC ???
- | IRQ4 | F_RY_BY        | NAND
- | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
- +------+----------------+------------------------------------------------------------
-
- ----------------------------------------------------------------------------------------------
-
- Interrupts on PCMCIA pins:
-
- +------+----------------+------------------------------------------------------------
- |  #   | Name           | Comment
- +------+----------------+------------------------------------------------------------
- | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
- | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
- | IP_A2| RMII1_MDINT    | PHY interrupt for #1
- | IP_A3| RMII2_MDINT    | PHY interrupt for #2
- | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
- | IP_A6| OK_ETH         | (V2) Cisco inline power OK
- +------+----------------+------------------------------------------------------------
-
-**************************************************************************************************/
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV           1
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE   1
-#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE       1
-
-/*************************************************************************************************/
-
-/* use board specific hardware */
-#undef CONFIG_WATCHDOG                 /* watchdog disabled            */
-#define CONFIG_HW_WATCHDOG
-
-/*************************************************************************************************/
-
-#define CONFIG_CDP_DEVICE_ID           20
-#define CONFIG_CDP_DEVICE_ID_PREFIX    "NT"    /* netta2 */
-#define CONFIG_CDP_PORT_ID             "eth%d"
-#define CONFIG_CDP_CAPABILITIES                0x00000010
-#define CONFIG_CDP_VERSION             "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
-#define CONFIG_CDP_PLATFORM            "Intracom NetTA2"
-#define CONFIG_CDP_TRIGGER             0x20020001
-#define CONFIG_CDP_POWER_CONSUMPTION   4300    /* 90 mA @ 48V */
-#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01    /* ipphone ? */
-
-/*************************************************************************************************/
-
-#define CONFIG_AUTO_COMPLETE   1
-
-/*************************************************************************************************/
-
-#define CONFIG_CRC32_VERIFY    1
-
-/*************************************************************************************************/
-
-#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE      1
-
-/*************************************************************************************************/
-#endif /* __CONFIG_H */
index b0f6b924043a9e47654b1ed0eb89bf00aace1202..b1f325bcd66096cd52039f9568cb2868c72f796e 100644 (file)
@@ -41,8 +41,6 @@
 # define CONFIG_PCMCIA_SLOT_B
 #elif defined(CONFIG_ATC)              /* The ATC use SLOT_A   */
 # define CONFIG_PCMCIA_SLOT_A
-#elif defined(CONFIG_NETTA)
-# define CONFIG_PCMCIA_SLOT_A
 #elif defined(CONFIG_UC100)            /* The UC100 use SLOT_B         */
 # define CONFIG_PCMCIA_SLOT_B
 #else
index 61eb66a8975db01dbc60d907c3a6cbe25d3ffd41..0eb91b869510b3fa8a8c06a958007ff343f8fdb4 100644 (file)
@@ -231,9 +231,6 @@ void status_led_set  (int led, int state);
 
 # define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
 
-/*****  NetPhone   ********************************************************/
-#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
-/* XXX empty just to avoid the error */
 /*****  STx XTc    ********************************************************/
 #elif defined(CONFIG_STXXTC)
 /* XXX empty just to avoid the error */