powerpc/86xx: Rework SBC8641 pci_init_board to use common FSL PCIe code

Remove duplicated code in SBC8641 board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>

diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index 705e1c2964f1127f33b99b503b563d0f2343ca59..a6f60eeb6e0d0aa77730dd4f403f7cb345ffef5b 100644 (file)
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -49,11 +49,7 @@ struct law_entry law_table[] = {
        SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                 LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
 #endif
-       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-       SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
        SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-       SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-       SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
        SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
        SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };

diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 5ee8f73c22ab75160b59e641f6e7cea61e8e9305..5c30b2676e4d573b13ea047c27a95a0e04520ef5 100644 (file)
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -181,70 +181,11 @@ long int fixed_sdram (void)
  * Initialize PCI Devices, report devices found.
  */
 
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
-       {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-        PCI_IDSEL_NUMBER, PCI_ANY_ID,
-        pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
-                                    PCI_ENET0_MEMADDR,
-                                    PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
-       {}
-};
-#endif
-
-static struct pci_controller pcie1_hose = {
-#ifndef CONFIG_PCI_PNP
-       config_table:pci_mpc86xxcts_config_table
-#endif
-};
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif /* CONFIG_PCIE2 */
-
-int first_free_busno = 0;
-
 void pci_init_board(void)
 {
-       struct fsl_pci_info pci_info[2];
-       volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
-       volatile ccsr_gur_t *gur = &immap->im_gur;
-       uint devdisr = in_be32(&gur->devdisr);
-       int pcie_ep;
-       int num = 0;
-
-#ifdef CONFIG_PCIE1
-       int pcie_configured = is_serdes_configured(PCIE1);
-
-       if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-               SET_STD_PCIE_INFO(pci_info[num], 1);
-               pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("PCIE1: connected as %s (base addr %lx)\n",
-                       pcie_ep ? "Endpoint" : "Root Complex",
-                       pci_info[num].regs);
-               first_free_busno = fsl_pci_init_port(&pci_info[num++],
-                                       &pcie1_hose, first_free_busno);
-       } else {
-               puts("PCIE1: disabled\n");
-       }
-#else
-       puts("PCIE1: disabled\n");
-#endif /* CONFIG_PCIE1 */
-
-#ifdef CONFIG_PCIE2
-
-       SET_STD_PCIE_INFO(pci_info[num], 2);
-       pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
-       printf("PCIE2: connected as %s (base addr %lx)\n",
-               pcie_ep ? "Endpoint" : "Root Complex",
-               pci_info[num].regs);
-       first_free_busno = fsl_pci_init_port(&pci_info[num++],
-                               &pcie2_hose, first_free_busno);
-#else
-       puts("PCIE2: disabled\n");
-#endif /* CONFIG_PCIE2 */
+       fsl_pcie_init_board(0);
 }
+#endif /* CONFIG_PCI */
 
 
 #if defined(CONFIG_OF_BOARD_SETUP)