rockchip: sdram: Fix register layout for Linux

The ChromeOS kernel reads the RAM settings from PMU_SYS_REG2 and expects
the bootloader to store the necessary information there.  We're using
the same register to pass the same information between the SPL and
U-Boot but in a slightly different format.

Change this to use the format expected by the Linux DMC driver so that
the system doesn't hang in Linux by misconfiguring the RAM.

This is almost the same as commit b5788dc ("rockchip: rk3288: correct
sdram setting") which was reverted in commit b525556 ("Revert "rockchip:
rk3288: correct sdram setting"") but parenthese have been added to apply
the mask correctly when reading the "bw" setting and a couple of minor
style issues have been fixed to keep check_patch.pl happy.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 4364d5a504bb8ddafe0a0187784ef5c61e7d7c4a..cf9ef2e8451aa9f2f6dca33953bf1f2be3a7f5b4 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -575,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram,
                        &sdram_params->ch[chan];
 
                sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
-               sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
+               sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
                sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
                sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
-               sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
+               sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
                sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
                sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
-               sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
-               sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
+               sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+               sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
 
                dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
        }
@@ -734,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu)
                rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
                        SYS_REG_RANK_MASK);
                col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
-               bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
+               bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
                cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
                                SYS_REG_CS0_ROW_MASK);
                cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
                                SYS_REG_CS1_ROW_MASK);
-               bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
-                       SYS_REG_BW_MASK;
+               bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) &
+                       SYS_REG_BW_MASK));
                row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
                        SYS_REG_ROW_3_4_MASK;