Enable L2 cache parity/ECC error checking
authorJames Yang <James.Yang@freescale.com>
Mon, 25 Mar 2013 07:39:58 +0000 (07:39 +0000)
committerAndy Fleming <afleming@freescale.com>
Fri, 24 May 2013 21:54:09 +0000 (16:54 -0500)
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/start.S

index 48e6a05d38d1d5b37dfcf09b045b3a96834fd868..d5b17de7c678098076ed940215a6329fb7332c6b 100644 (file)
@@ -337,7 +337,7 @@ int enable_cluster_l2(void)
                        while ((in_be32(&l2cache->l2csr0)
                                & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
                                        ;
-                       out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE);
                }
                i++;
        } while (!(cluster & TP_CLUSTER_EOC));
index 5542d0afb24983c4b4ce44ecef6af9a551fca523..87168e202dd8af194f7276cb2f113ff5977431ba 100644 (file)
@@ -734,7 +734,7 @@ enable_l2_cluster_l2:
        isync
        and.    r1, r0, r4
        bne     1b
-       lis     r4, L2CSR0_L2E@h
+       lis     r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
        sync
        stw     r4, 0(r3)       /* enable L2 */
 delete_ccsr_l2_tlb: