Add support for the DevKit8000 board

This patch adds support for the DevKit8000 board.

Signed-off-by: Frederik Kriewitz <frederik@kriewitz.eu>

diff --git a/MAINTAINERS b/MAINTAINERS
index e4f3dee83c2dd1f102734ac05e88a8348e7420a7..439c1b8af306e98bcf36ab4e4f9941da6ae0bb32 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -592,6 +592,10 @@ Nishant Kamat <nskamat@ti.com>
 
        omap1610h2      ARM926EJS
 
+Frederik Kriewitz <frederik@kriewitz.eu>
+
+       devkit8000      ARM CORTEX-A8 (OMAP3530 SoC)
+
 Sergey Kubushyn <ksi@koi8.net>
 
        DV-EVM          ARM926EJS

diff --git a/MAKEALL b/MAKEALL
index 03e8b7a205cb4bc100ef2307f211543a568dadcb..13f3f5ec3f1e56597b62393b648b8d55f12d0581 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -581,6 +581,7 @@ LIST_ARM11="                        \
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="           \
+       devkit8000              \
        omap3_beagle            \
        omap3_overo             \
        omap3_evm               \

diff --git a/Makefile b/Makefile
index 831be626d05e416849cf7a9fa39b2c1a1c1bb471..8e820846cdbd949cb57ee899dd1462733af702ae 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3145,6 +3145,9 @@ SMN42_config      :       unconfig
 ## ARM CORTEX Systems
 #########################################################################
 
+devkit8000_config :    unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
+
 omap3_beagle_config :  unconfig
        @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 beagle ti omap3
 

diff --git a/board/timll/devkit8000/Makefile b/board/timll/devkit8000/Makefile
new file mode 100644 (file)
index 0000000..38600c4
--- /dev/null
+++ b/board/timll/devkit8000/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := devkit8000.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/timll/devkit8000/config.mk b/board/timll/devkit8000/config.mk
new file mode 100644 (file)
index 0000000..6bfcef7
--- /dev/null
+++ b/board/timll/devkit8000/config.mk
@@ -0,0 +1,35 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# (C) Copyright 2009
+# Frederik Kriewitz <frederik@kriewitz.eu>
+#
+# DevKit8000 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000

diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
new file mode 100644 (file)
index 0000000..db7d2e2
--- /dev/null
+++ b/board/timll/devkit8000/devkit8000.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Sunil Kumar <sunilsaini05@gmail.com>
+ *     Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/mach-types.h>
+#include "devkit8000.h"
+#ifdef CONFIG_DRIVER_DM9000
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+       gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+       /* board id for Linux */
+       gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
+       /* boot param addr */
+       gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+       return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+       struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
+#ifdef CONFIG_DRIVER_DM9000
+       uchar enetaddr[6];
+       u32 die_id_0;
+#endif
+
+       twl4030_power_init();
+#ifdef CONFIG_TWL4030_LED
+       twl4030_led_init();
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+       /* Configure GPMC registers for DM9000 */
+       writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1);
+       writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2);
+       writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3);
+       writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4);
+       writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5);
+       writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6);
+       writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
+
+       /* Use OMAP DIE_ID as MAC address */
+       if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+               printf("ethaddr not set, using Die ID\n");
+               die_id_0 = readl(&id_base->die_id_0);
+               enetaddr[0] = 0x02; /* locally administered */
+               enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
+               enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
+               enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
+               enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
+               enetaddr[5] = (die_id_0 & 0x000000ff);
+               eth_setenv_enetaddr("ethaddr", enetaddr);
+       }
+#endif
+
+       dieid_num_r();
+
+       return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *             hardware. Many pins need to be moved from protect to primary
+ *             mode.
+ */
+void set_muxconf_regs(void)
+{
+       MUX_DEVKIT8000();
+}
+
+#ifdef CONFIG_DRIVER_DM9000
+/*
+ * Routine: board_eth_init
+ * Description: Setting up the Ethernet hardware.
+ */
+int board_eth_init(bd_t *bis)
+{
+       return dm9000_initialize(bis);
+}
+#endif

diff --git a/board/timll/devkit8000/devkit8000.h b/board/timll/devkit8000/devkit8000.h
new file mode 100644 (file)
index 0000000..6fcc75a
--- /dev/null
+++ b/board/timll/devkit8000/devkit8000.h
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _DEVKIT8000_H_
+#define _DEVKIT8000_H_
+
+const omap3_sysinfo sysinfo = {
+       DDR_STACKED,
+       "OMAP3 DevKit8000",
+       "NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEVKIT8000() \
+ /* SDRC */\
+ MUX_VAL(CP(SDRC_D0),          (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),          (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),          (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),          (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),          (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),          (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),          (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),          (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),          (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),          (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10),         (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11),         (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12),         (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13),         (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14),         (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15),         (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16),         (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17),         (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18),         (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19),         (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20),         (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21),         (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22),         (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23),         (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24),         (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25),         (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26),         (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27),         (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28),         (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29),         (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30),         (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31),         (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK),         (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),                (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),                (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),                (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),                (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /* GPMC */\
+ MUX_VAL(CP(GPMC_A1),          (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),          (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),          (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),          (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),          (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),          (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),          (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),          (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),          (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10),         (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),          (IEN  | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),          (IEN  | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),          (IEN  | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),          (IEN  | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4),          (IEN  | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5),          (IEN  | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6),          (IEN  | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7),          (IEN  | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8),          (IEN  | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9),          (IEN  | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10),         (IEN  | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11),         (IEN  | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12),         (IEN  | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13),         (IEN  | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14),         (IEN  | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15),         (IEN  | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS0 NAND*/\
+ MUX_VAL(CP(GPMC_NCS1),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS6 DM9000*/\
+ MUX_VAL(CP(GPMC_NCS7),                (IDIS | PTU | EN  | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_NBE1),                (IEN  | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_WAIT2),       (IEN  | PTU | EN  | M0)) /*GPMC_WAIT2*/\
+ MUX_VAL(CP(GPMC_WAIT3),       (IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+ MUX_VAL(CP(GPMC_CLK),         (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE),    (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE),         (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE),         (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE),    (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NWP),         (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0),       (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1),       (IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ /* DSS */\
+ MUX_VAL(CP(DSS_PCLK),         (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC),                (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC),                (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS),       (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0),                (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1),                (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2),                (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3),                (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4),                (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5),                (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6),                (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7),                (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8),                (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9),                (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10),       (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11),       (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12),       (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13),       (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14),       (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15),       (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16),       (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17),       (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18),       (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19),       (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20),       (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21),       (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22),       (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23),       (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /* CAMERA */\
+ MUX_VAL(CP(CAM_HS),           (IEN  | PTU | EN  | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS),           (IEN  | PTU | EN  | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA),                (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK),         (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD),          (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0),           (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1),           (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2),           (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3),           (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4),           (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5),           (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6),           (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7),           (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8),           (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9),           (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10),          (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11),          (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB),                (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN),          (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE),       (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0),         (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0),         (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1),         (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1),         (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /* Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX),       (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX),      (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR),                (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX),                (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /* MMC Slot */\
+ MUX_VAL(CP(MMC1_CLK),         (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD),         (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7),                (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
+ /* Expansion Header */\
+ MUX_VAL(CP(MMC2_CLK),         (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD),         (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0),                (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1),                (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2),                (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3),                (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4),                (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5),                (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6),                (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7),                (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ MUX_VAL(CP(MCBSP3_DX),                (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(MCBSP3_DR),                (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(MCBSP3_CLKX),      (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(MCBSP3_FSX),       (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+ MUX_VAL(CP(UART2_CTS),                (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
+ MUX_VAL(CP(UART2_RTS),                (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
+ MUX_VAL(CP(UART2_TX),         (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
+ MUX_VAL(CP(UART2_RX),         (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
+ MUX_VAL(CP(UART1_TX),         (IDIS | PTD | DIS | M0)) /*GPIO_148*/\
+ MUX_VAL(CP(UART1_RTS),                (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS),                (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX),         (IEN  | PTD | DIS | M0)) /*GPIO_151*/\
+ MUX_VAL(CP(MCBSP4_CLKX),      (IEN  | PTD | DIS | M1)) /*GPIO_152*/\
+ MUX_VAL(CP(MCBSP4_DR),                (IEN  | PTD | DIS | M1)) /*GPIO_153*/\
+ MUX_VAL(CP(MCBSP4_DX),                (IEN  | PTD | DIS | M1)) /*GPIO_154*/\
+ MUX_VAL(CP(MCBSP4_FSX),       (IEN  | PTD | DIS | M1)) /*GPIO_155*/\
+ MUX_VAL(CP(MCBSP1_CLKR),      (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR),       (IDIS | PTU | EN  | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX),                (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(MCBSP1_DR),                (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS),       (IEN  | PTU | DIS | M0)) /*GPIO_160*/\
+ MUX_VAL(CP(MCBSP1_FSX),       (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX),      (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /* Serial Interface */\
+ MUX_VAL(CP(UART3_CTS_RCTX),   (IDIS | PTD | EN  | M4)) /*GPIO_163 - LED2*/\
+ MUX_VAL(CP(UART3_RTS_SD),     (IDIS | PTU | EN  | M4)) /*GPIO_164 - LED3*/\
+ MUX_VAL(CP(UART3_RX_IRRX),    (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX),    (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ /* Host USB0 */\
+ MUX_VAL(CP(HSUSB0_CLK),       (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP),       (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR),       (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT),       (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL),         (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA),         (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL),         (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA),         (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL),         (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA),         (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL),         (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA),         (IEN  | PTU | DIS | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO),          (IDIS | PTD | DIS | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK),       (IEN  | PTD | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO),      (IEN  | PTD | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI),      (IEN  | PTD | DIS | M0)) /*MCSPI1_SOMI*/\
+ MUX_VAL(CP(MCSPI1_CS0),       (IEN  | PTD | DIS | M0)) /*MCSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1),       (IDIS | PTD | DIS | M0)) /*MCSPI1_CS1*/\
+ MUX_VAL(CP(MCSPI1_CS2),       (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
+ /* USB EHCI (port 2) */\
+ MUX_VAL(CP(MCSPI1_CS3),       (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA2*/\
+ MUX_VAL(CP(MCSPI2_CLK),       (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA7*/\
+ MUX_VAL(CP(MCSPI2_SIMO),      (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA4*/\
+ MUX_VAL(CP(MCSPI2_SOMI),      (IEN  | PTD | DIS | M0)) /*HSUSB2_DATA5*/\
+ MUX_VAL(CP(MCSPI2_CS0),       (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA6*/\
+ MUX_VAL(CP(MCSPI2_CS1),       (IEN  | PTD | EN  | M0)) /*HSUSB2_DATA3*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K),          (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ),       (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ),         (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0),                (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+ MUX_VAL(CP(SYS_BOOT1),                (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
+ MUX_VAL(CP(SYS_BOOT2),                (IEN  | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
+ MUX_VAL(CP(SYS_BOOT3),                (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4),                (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5),                (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6),                (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
+ MUX_VAL(CP(SYS_OFF_MODE),     (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1),      (IDIS | PTD | EN  | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2),      (IDIS | PTU | EN  | M4)) /*GPIO_186 - LED1*/\
+ MUX_VAL(CP(ETK_CLK_ES2),      (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2),      (IDIS | PTD | EN  | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2),       (IDIS | PTU | EN  | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2),       (IEN  | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2),       (IEN  | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2),      (IDIS | PTU | EN  | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2),      (IEN  | PTU | EN  | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2),      (IEN  | PTU | EN  | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2),      (IEN  | PTU | EN  | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2),      (IEN  | PTU | EN  | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2),      (IEN  | PTU | EN  | M4)) /*GPIO_29*/\
+ MUX_VAL(CP(D2D_MCAD1),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD1*/\
+ MUX_VAL(CP(D2D_MCAD2),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD2*/\
+ MUX_VAL(CP(D2D_MCAD3),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD3*/\
+ MUX_VAL(CP(D2D_MCAD4),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD4*/\
+ MUX_VAL(CP(D2D_MCAD5),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD5*/\
+ MUX_VAL(CP(D2D_MCAD6),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD6*/\
+ MUX_VAL(CP(D2D_MCAD7),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD7*/\
+ MUX_VAL(CP(D2D_MCAD8),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD8*/\
+ MUX_VAL(CP(D2D_MCAD9),                (IEN  | PTD | EN  | M0)) /*D2D_MCAD9*/\
+ MUX_VAL(CP(D2D_MCAD10),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD10*/\
+ MUX_VAL(CP(D2D_MCAD11),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD11*/\
+ MUX_VAL(CP(D2D_MCAD12),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD12*/\
+ MUX_VAL(CP(D2D_MCAD13),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD13*/\
+ MUX_VAL(CP(D2D_MCAD14),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD14*/\
+ MUX_VAL(CP(D2D_MCAD15),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD15*/\
+ MUX_VAL(CP(D2D_MCAD16),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD16*/\
+ MUX_VAL(CP(D2D_MCAD17),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD17*/\
+ MUX_VAL(CP(D2D_MCAD18),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD18*/\
+ MUX_VAL(CP(D2D_MCAD19),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD19*/\
+ MUX_VAL(CP(D2D_MCAD20),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD20*/\
+ MUX_VAL(CP(D2D_MCAD21),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD21*/\
+ MUX_VAL(CP(D2D_MCAD22),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD22*/\
+ MUX_VAL(CP(D2D_MCAD23),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD23*/\
+ MUX_VAL(CP(D2D_MCAD24),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD24*/\
+ MUX_VAL(CP(D2D_MCAD25),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD25*/\
+ MUX_VAL(CP(D2D_MCAD26),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD26*/\
+ MUX_VAL(CP(D2D_MCAD27),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD27*/\
+ MUX_VAL(CP(D2D_MCAD28),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD28*/\
+ MUX_VAL(CP(D2D_MCAD29),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD29*/\
+ MUX_VAL(CP(D2D_MCAD30),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD30*/\
+ MUX_VAL(CP(D2D_MCAD31),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD31*/\
+ MUX_VAL(CP(D2D_MCAD32),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD32*/\
+ MUX_VAL(CP(D2D_MCAD33),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD33*/\
+ MUX_VAL(CP(D2D_MCAD34),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD34*/\
+ MUX_VAL(CP(D2D_MCAD35),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD35*/\
+ MUX_VAL(CP(D2D_MCAD36),       (IEN  | PTD | EN  | M0)) /*D2D_MCAD36*/\
+ MUX_VAL(CP(D2D_CLK26MI),      (IEN  | PTD | DIS | M0)) /*D2D_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON),    (IEN  | PTD | EN  | M0)) /*D2D_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM),     (IEN  | PTU | EN  | M0)) /*D2D_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ),     (IEN  | PTD | DIS | M0)) /*D2D_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ),    (IEN  | PTD | DIS | M0)) /*D2D_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT),                (IEN  | PTD | EN  | M0)) /*D2D_spint*/\
+ MUX_VAL(CP(D2D_FRINT),                (IEN  | PTD | EN  | M0)) /*D2D_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0),      (IEN  | PTD | DIS | M0)) /*D2D_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1),      (IEN  | PTD | DIS | M0)) /*D2D_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2),      (IEN  | PTD | DIS | M0)) /*D2D_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3),      (IEN  | PTD | DIS | M0)) /*D2D_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST),      (IEN  | PTD | DIS | M0)) /*D2D_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI),       (IEN  | PTD | DIS | M0)) /*D2D_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO),       (IEN  | PTD | DIS | M0)) /*D2D_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS),       (IEN  | PTD | DIS | M0)) /*D2D_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK),       (IEN  | PTD | DIS | M0)) /*D2D_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK),      (IEN  | PTD | DIS | M0)) /*D2D_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY),       (IEN  | PTU | EN  | M0)) /*D2D_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP),      (IEN  | PTD | EN  | M0)) /*D2D_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ),      (IEN  | PTD | DIS | M0)) /*D2D_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK),      (IEN  | PTU | EN  | M0)) /*D2D_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE),       (IEN  | PTD | DIS | M0)) /*D2D_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE),       (IEN  | PTD | DIS | M0)) /*D2D_swrite*/\
+ MUX_VAL(CP(D2D_MREAD),                (IEN  | PTD | DIS | M0)) /*D2D_mread*/\
+ MUX_VAL(CP(D2D_SREAD),                (IEN  | PTD | DIS | M0)) /*D2D_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG),     (IEN  | PTD | DIS | M0)) /*D2D_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG),     (IEN  | PTD | DIS | M0)) /*D2D_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0),                (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1),                (IDIS | PTD | DIS | M7)) /*sdrc_cke1*/
+
+#endif

diff --git a/doc/README.timll b/doc/README.timll
new file mode 100644 (file)
index 0000000..609bf51
--- /dev/null
+++ b/doc/README.timll
@@ -0,0 +1,15 @@
+DevKit8000
+==========
+
+The OMAP3 DevKit8000 from Embest/Timll is a clone of the OMAP3 beagle board
+with Ethernet and Touch Screen controller on board.
+
+For more information go to:
+http://www.embedinfo.com/English/Product/devkit8000.asp
+
+There's no real MAC address available.
+If ethaddr is not set, 5 Bytes of the OMAP Die ID will be used.
+
+Build:
+make devkit8000_config
+make

diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
new file mode 100644 (file)
index 0000000..cd40da6
--- /dev/null
+++ b/include/configs/devkit8000.h
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Configuration settings for the DevKit8000 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARMCORTEXA8     1       /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP            1       /* in a TI OMAP core */
+#define CONFIG_OMAP34XX                1       /* which is a 34XX */
+#define CONFIG_OMAP3430                1       /* which is in a 3430 */
+#define CONFIG_OMAP3_DEVKIT8000        1       /* working with DevKit8000 */
+
+#include <asm/arch/cpu.h>              /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO         1
+#define CONFIG_DISPLAY_BOARDINFO       1
+
+/* Clock Defines */
+#define V_OSCK                         26000000        /* Clock output from T2 */
+#define V_SCLK                         (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ                  /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS       1
+#define CONFIG_INITRD_TAG              1
+#define CONFIG_REVISION_TAG            1
+
+/* Size of malloc() pool */
+#define CONFIG_ENV_SIZE                        SZ_128K /* Total Size Environment */
+                                               /* Sector */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* bytes reserved for */
+                                               /* initial data */
+
+/* Hardware drivers */
+
+/* DM9000 */
+#define CONFIG_NET_MULTI               1
+#define CONFIG_NET_RETRY_COUNT         20
+#define        CONFIG_DRIVER_DM9000            1
+#define        CONFIG_DM9000_BASE              0x2c000000
+#define        DM9000_IO                       CONFIG_DM9000_BASE
+#define        DM9000_DATA                     (CONFIG_DM9000_BASE + 0x400)
+#define        CONFIG_DM9000_USE_16BIT         1
+#define CONFIG_DM9000_NO_SROM          1
+#undef CONFIG_DM9000_DEBUG
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    (-4)
+#define CONFIG_SYS_NS16550_CLK         48000000 /* 48MHz (APLL96/2) */
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX              3
+#define CONFIG_SYS_NS16550_COM3                OMAP34XX_UART3
+#define CONFIG_SERIAL3                 3
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE      {4800, 9600, 19200, 38400, 57600,\
+                                       115200}
+
+/* MMC */
+#define CONFIG_MMC                     1
+#define CONFIG_OMAP3_MMC               1
+#define CONFIG_DOS_PARTITION           1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           1
+#define CONFIG_SYS_I2C_BUS             0
+#define CONFIG_SYS_I2C_BUS_SELECT      1
+#define CONFIG_DRIVER_OMAP34XX_I2C     1
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER           1
+#define CONFIG_TWL4030_LED             1
+
+/* Board NAND Info */
+#define CONFIG_SYS_NO_FLASH            /* no NOR flash */
+#define CONFIG_MTD_DEVICE              /* needed for mtdparts commands */
+#define MTDIDS_DEFAULT                 "nand0=nand"
+#define MTDPARTS_DEFAULT               "mtdparts=nand:" \
+                                               "512k(x-loader)," \
+                                               "1920k(u-boot)," \
+                                               "128k(u-boot-env)," \
+                                               "4m(kernel)," \
+                                               "-(fs)"
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR           NAND_BASE       /* physical address */
+                                                       /* to access nand */
+#define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
+                                                       /* to access nand at */
+                                                       /* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT    1
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
+                                                       /* devices */
+#define CONFIG_SYS_64BIT_VSPRINTF                      /* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV               "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET       0x680000
+#define CONFIG_JFFS2_PART_SIZE         0xf980000       /* size of jffs2 */
+                                                       /* partition */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP                        /* DHCP support                 */
+#define CONFIG_CMD_EXT2                        /* EXT2 Support                 */
+#define CONFIG_CMD_FAT                 /* FAT support                  */
+#define CONFIG_CMD_I2C                 /* I2C serial bus support       */
+#define CONFIG_CMD_JFFS2               /* JFFS2 Support                */
+#define CONFIG_CMD_MMC                 /* MMC support                  */
+#define CONFIG_CMD_MTDPARTS            /* Enable MTD parts commands    */
+#define CONFIG_CMD_NAND                        /* NAND support                 */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK    /* nand (un)lock commands       */
+
+#undef CONFIG_CMD_FPGA                 /* FPGA configuration Support   */
+#undef CONFIG_CMD_IMI                  /* iminfo                       */
+
+/* BOOTP/DHCP options */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+#undef CONFIG_BOOTP_VENDOREX
+
+/* Environment information */
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+
+#define CONFIG_BOOTDELAY               3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "loadaddr=0x82000000\0" \
+       "console=ttyS2,115200n8\0" \
+       "vram=12M\0" \
+       "dvimode=1024x768MR-16@60\0" \
+       "defaultdisplay=dvi\0" \
+       "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
+       "kernelopts=rw\0" \
+       "commonargs=" \
+               "setenv bootargs console=${console} " \
+               "vram=${vram} " \
+               "omapfb.mode=dvi:${dvimode} " \
+               "omapdss.def_disp=${defaultdisplay}\0" \
+       "mmcargs=" \
+               "run commonargs; " \
+               "setenv bootargs ${bootargs} " \
+               "root=/dev/mmcblk0p2 " \
+               "${kernelopts}\0" \
+       "nandargs=" \
+               "run commonargs; " \
+               "setenv bootargs ${bootargs} " \
+               "omapfb.mode=dvi:${dvimode} " \
+               "omapdss.def_disp=${defaultdisplay} " \
+               "root=/dev/mtdblock4 " \
+               "rootfstype=jffs2 " \
+               "${kernelopts}\0" \
+       "netargs=" \
+               "run commonargs; " \
+               "setenv bootargs ${bootargs} " \
+               "root=/dev/nfs " \
+               "nfsroot=${serverip}:${rootpath},${nfsopts} " \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
+               "${kernelopts} " \
+               "dnsip1=${dnsip} " \
+               "dnsip2=${dnsip2}\0" \
+       "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+       "bootscript=echo Running bootscript from mmc ...; " \
+               "source ${loadaddr}\0" \
+       "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+       "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
+       "mmcboot=echo Booting from mmc ...; " \
+               "run mmcargs; " \
+               "bootm ${loadaddr}\0" \
+       "nandboot=echo Booting from nand ...; " \
+               "run nandargs; " \
+               "nand read ${loadaddr} 280000 400000; " \
+               "bootm ${loadaddr}\0" \
+       "netboot=echo Booting from network ...; " \
+               "dhcp ${loadaddr}; " \
+               "run netargs; " \
+               "bootm ${loadaddr}\0" \
+       "autoboot=if mmc init 0; then " \
+                       "if run loadbootscript; then " \
+                               "run bootscript; " \
+                       "else " \
+                               "if run loaduimage; then " \
+                                       "run mmcboot; " \
+                               "else run nandboot; " \
+                               "fi; " \
+                       "fi; " \
+               "else run nandboot; fi\0"
+
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE           1
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "OMAP3 DevKit8000 # "
+#define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             128     /* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE            (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START       (OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_MEMTEST_START + \
+                                       0x01000000) /* 16MB */
+
+#define CONFIG_SYS_LOAD_ADDR           (OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE           (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV                 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ                  1000
+
+/* The stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE               SZ_128K /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ           SZ_4K   /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ           SZ_4K   /* FIQ stack */
+#endif
+
+/*  Physical Memory Map  */
+#define CONFIG_NR_DRAM_BANKS           2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1                   OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE              SZ_128M /* at least 128 meg */
+#define PHYS_SDRAM_2                   OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C                     1
+
+/* NAND and environment organization  */
+#define PISMO1_NAND_SIZE               GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN         SZ_256K /* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND          1
+#define SMNAND_ENV_OFFSET              0x260000 /* environment starts here */
+
+#define CONFIG_ENV_OFFSET              boot_flash_off
+
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */