cpu9260: update board support
authorEric Benard <eric@eukrea.com>
Sun, 3 Apr 2011 06:35:54 +0000 (06:35 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 27 Apr 2011 17:38:10 +0000 (19:38 +0200)
- update to new relocation code
- switch to boards.cfg
- get rid of LEGACY (still a little hack in .h to compile)
- add nand boot configuration
- boot tested for the following configurations :
9260 (64MB RAM & nor boot)
9260_nand (64MB RAM & nand boot)
9G20_128M (128MB RAM & nor boot)
9G20_nand_128M (128MB RAM & nand boot)
(nor boot is using lowlevel init)

Signed-off-by: Eric BĂ©nard <eric@eukrea.com>
board/eukrea/cpu9260/config.mk [deleted file]
board/eukrea/cpu9260/cpu9260.c
board/eukrea/cpu9260/led.c
boards.cfg
include/configs/cpu9260.h

diff --git a/board/eukrea/cpu9260/config.mk b/board/eukrea/cpu9260/config.mk
deleted file mode 100644 (file)
index 2077692..0000000
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_SYS_TEXT_BASE = 0x21f00000
index 61b6c3323dd37a74adfe07bb9891f833be74c7ec..9ec48a0d21cbcac105d034be345cf50dfdc1fe52 100644 (file)
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9260.h>
-#include <asm/arch/at91sam9_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -53,116 +54,103 @@ DECLARE_GLOBAL_DATA_PTR;
 static void cpu9260_nand_hw_init(void)
 {
        unsigned long csa;
+       at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE;
+       at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
+       at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
 
        /* Enable CS3 */
-       csa = at91_sys_read(AT91_MATRIX_EBICSA);
-       at91_sys_write(AT91_MATRIX_EBICSA,
-                      csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+       csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
+       writel(csa, &matrix->csa);
 
        /* Configure SMC CS3 for NAND/SmartMedia */
 #if defined(CONFIG_CPU9G20)
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
-                      AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
-       at91_sys_write(AT91_SMC_MODE(3),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
-                      AT91_SMC_DBW_8 |
-                      AT91_SMC_TDF_(3));
+       writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
+               AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+               &smc->cs[3].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+               AT91_SMC_MODE_EXNW_DISABLE |
+               AT91_SMC_MODE_DBW_8 |
+               AT91_SMC_MODE_TDF_CYCLE(3),
+               &smc->cs[3].mode);
 #elif defined(CONFIG_CPU9260)
-       at91_sys_write(AT91_SMC_SETUP(3),
-                      AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-                      AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-       at91_sys_write(AT91_SMC_PULSE(3),
-                      AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
-                      AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
-       at91_sys_write(AT91_SMC_CYCLE(3),
-                      AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
-       at91_sys_write(AT91_SMC_MODE(3),
-                      AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-                      AT91_SMC_EXNWMODE_DISABLE |
-                      AT91_SMC_DBW_8 |
-                      AT91_SMC_TDF_(2));
+       writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+               AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+               &smc->cs[3].setup);
+       writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+               AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+               &smc->cs[3].pulse);
+       writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+               &smc->cs[3].cycle);
+       writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+               AT91_SMC_MODE_EXNW_DISABLE |
+               AT91_SMC_MODE_DBW_8 |
+               AT91_SMC_MODE_TDF_CYCLE(2),
+               &smc->cs[3].mode);
 #endif
 
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+       writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer);
 
        /* Configure RDY/BSY */
-       at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+       at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 
        /* Enable NandFlash */
-       at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+       at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void cpu9260_macb_hw_init(void)
 {
-       unsigned long rstc;
+       unsigned long rstcmr;
+       at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+       at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
 
        /* Enable clock */
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
-
-       /*
-        * Disable pull-up on:
-        *      RXDV (PA17) => PHY normal mode (not Test mode)
-        *      ERX0 (PA14) => PHY ADDR0
-        *      ERX1 (PA15) => PHY ADDR1
-        *      ERX2 (PA25) => PHY ADDR2
-        *      ERX3 (PA26) => PHY ADDR3
-        *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
-        *
-        * PHY has internal pull-down
-        */
-       writel(pin_to_mask(AT91_PIN_PA14) |
-              pin_to_mask(AT91_PIN_PA15) |
-              pin_to_mask(AT91_PIN_PA17) |
-              pin_to_mask(AT91_PIN_PA25) |
-              pin_to_mask(AT91_PIN_PA26) |
-              pin_to_mask(AT91_PIN_PA28),
-              pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
-
-       rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+       writel(1 << AT91SAM9260_ID_EMAC, &pmc->pcer);
+
+       at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+
+       rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 
        /* Need to reset PHY -> 500ms reset */
-       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
-                      AT91_RSTC_URSTEN);
+       writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
+                               AT91_RSTC_MR_URSTEN, &rstc->mr);
 
-       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+       writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 
        /* Wait for end hardware reset */
-       while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
+       while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
                ;
 
        /* Restore NRST value */
-       at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-                      (rstc) |
-                      AT91_RSTC_URSTEN);
-
-       /* Re-enable pull-up */
-       writel(pin_to_mask(AT91_PIN_PA14) |
-              pin_to_mask(AT91_PIN_PA15) |
-              pin_to_mask(AT91_PIN_PA17) |
-              pin_to_mask(AT91_PIN_PA25) |
-              pin_to_mask(AT91_PIN_PA26) |
-              pin_to_mask(AT91_PIN_PA28),
-              pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+       writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
 
        at91_macb_hw_init();
 }
 #endif
 
-int board_init(void)
+int board_early_init_f(void)
 {
-       /* Enable Ctrlc */
-       console_init_f();
+       at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
+       writel((1 << AT91SAM9260_ID_PIOA) |
+               (1 << AT91SAM9260_ID_PIOC) |
+               (1 << AT91SAM9260_ID_PIOB),
+               &pmc->pcer);
+
+       at91_serial_hw_init();
+
+       return 0;
+}
 
+
+int board_init(void)
+{
        /* arch number of the board */
 #if defined(CONFIG_CPU9G20)
        gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20;
@@ -171,9 +159,8 @@ int board_init(void)
 #endif
 
        /* adress of boot parameters */
-       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-       at91_serial_hw_init();
 #ifdef CONFIG_CMD_NAND
        cpu9260_nand_hw_init();
 #endif
@@ -188,26 +175,16 @@ int board_init(void)
 
 int dram_init(void)
 {
-       gd->bd->bi_dram[0].start = PHYS_SDRAM;
-       if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) !=
-           PHYS_SDRAM_SIZE)
-               return -1;
-
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
+                       CONFIG_SYS_SDRAM_SIZE);
        return 0;
 }
 
-#ifdef CONFIG_RESET_PHY_R
-void reset_phy(void)
-{
-}
-#endif
-
 int board_eth_init(bd_t *bis)
 {
        int rc = 0;
 #ifdef CONFIG_MACB
-       rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+       rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0);
 #endif
        return rc;
 }
index e73543bb12736e2a3052b45f9d6a810480cea541..d0906bc894d1f84bc25d5fc555308a78838ad670 100644 (file)
@@ -35,65 +35,67 @@ static unsigned int saved_state[4] = {STATUS_LED_OFF, STATUS_LED_OFF,
 
 void coloured_LED_init(void)
 {
+       at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
        /* Enable clock */
-       at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
+       writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer);
 
-       at91_set_gpio_output(CONFIG_RED_LED, 1);
-       at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-       at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
-       at91_set_gpio_output(CONFIG_BLUE_LED, 1);
+       at91_set_pio_output(CONFIG_RED_LED, 1);
+       at91_set_pio_output(CONFIG_GREEN_LED, 1);
+       at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+       at91_set_pio_output(CONFIG_BLUE_LED, 1);
 
-       at91_set_gpio_value(CONFIG_RED_LED, 1);
-       at91_set_gpio_value(CONFIG_GREEN_LED, 1);
-       at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
-       at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+       at91_set_pio_value(CONFIG_RED_LED, 1);
+       at91_set_pio_value(CONFIG_GREEN_LED, 1);
+       at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+       at91_set_pio_value(CONFIG_BLUE_LED, 1);
 }
 
 void red_LED_off(void)
 {
-       at91_set_gpio_value(CONFIG_RED_LED, 1);
+       at91_set_pio_value(CONFIG_RED_LED, 1);
        saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
 }
 
 void green_LED_off(void)
 {
-       at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+       at91_set_pio_value(CONFIG_GREEN_LED, 1);
        saved_state[STATUS_LED_GREEN] = STATUS_LED_OFF;
 }
 
 void yellow_LED_off(void)
 {
-       at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+       at91_set_pio_value(CONFIG_YELLOW_LED, 1);
        saved_state[STATUS_LED_YELLOW] = STATUS_LED_OFF;
 }
 
 void blue_LED_off(void)
 {
-       at91_set_gpio_value(CONFIG_BLUE_LED, 1);
+       at91_set_pio_value(CONFIG_BLUE_LED, 1);
        saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
 }
 
 void red_LED_on(void)
 {
-       at91_set_gpio_value(CONFIG_RED_LED, 0);
+       at91_set_pio_value(CONFIG_RED_LED, 0);
        saved_state[STATUS_LED_RED] = STATUS_LED_ON;
 }
 
 void green_LED_on(void)
 {
-       at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+       at91_set_pio_value(CONFIG_GREEN_LED, 0);
        saved_state[STATUS_LED_GREEN] = STATUS_LED_ON;
 }
 
 void yellow_LED_on(void)
 {
-       at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+       at91_set_pio_value(CONFIG_YELLOW_LED, 0);
        saved_state[STATUS_LED_YELLOW] = STATUS_LED_ON;
 }
 
 void blue_LED_on(void)
 {
-       at91_set_gpio_value(CONFIG_BLUE_LED, 0);
+       at91_set_pio_value(CONFIG_BLUE_LED, 0);
        saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
 }
 
index 4aa21f3b55426b5467811fb140c5a04d393c4fb2..0f7daf54c3b774c4ac4cceedbcd0d5e3e73212f1 100644 (file)
@@ -73,6 +73,14 @@ omap1510inn                  arm         arm925t     -                   ti
 aspenite                     arm         arm926ejs   -                   Marvell        armada100
 afeb9260                     arm         arm926ejs   -                   -              at91
 at91cap9adk                  arm         arm926ejs   -                   atmel          at91
+cpu9260                      arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260
+cpu9260_nand                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,NANDBOOT
+cpu9260_128M                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,CPU9260_128M
+cpu9260_nand_128M            arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9260,CPU9260_128M,NANDBOOT
+cpu9G20                      arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9G20
+cpu9G20_nand                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9G20,NANDBOOT
+cpu9G20_128M                 arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9G20,CPU9G20_128M
+cpu9G20_nand_128M            arm         arm926ejs   cpu9260             eukrea         at91        cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT
 top9000eval_xe               arm         arm926ejs   top9000             emk            at91        top9000:EVAL9000
 top9000su_xe                 arm         arm926ejs   top9000             emk            at91        top9000:SU9000
 meesc                        arm         arm926ejs   -                   esd            at91
index d2394235f193f109340c76a63f5ad5b8780f9ee2..a8ada2d418ba0246c28f303fc70beb55fc777c3e 100644 (file)
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_AT91_LEGACY
-
-#define CONFIG_DISPLAY_CPUINFO 1
+/* to be removed once maemory-map.h is fixed */
+#define AT91_BASE_SYS  0xffffe800
+#define AT91_DBGU      (0xfffff200 - AT91_BASE_SYS)
 
 #define CONFIG_SYS_AT91_MAIN_CLOCK     18432000
 #define CONFIG_SYS_HZ          1000
 
-#define CONFIG_ARM926EJS       1
-
-#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9260)
-#define CONFIG_CPU9260         1
-#elif defined(CONFIG_CPU9G20_128M) || defined(CONFIG_CPU9G20)
-#define CONFIG_CPU9G20         1
-#endif
+#define CONFIG_ARM926EJS
 
 #if defined(CONFIG_CPU9G20)
-#define CONFIG_AT91SAM9G20     1
+#define CONFIG_AT91SAM9G20
 #elif defined(CONFIG_CPU9260)
-#define CONFIG_AT91SAM9260     1
+#define CONFIG_AT91SAM9260
 #else
 #error "Unknown board"
 #endif
 
+#define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
 #undef CONFIG_USE_IRQ
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
 
-#define CONFIG_CMDLINE_TAG             1
-#define CONFIG_SETUP_MEMORY_TAGS       1
-#define CONFIG_INITRD_TAG              1
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE           0x23f00000
+#else
+#define CONFIG_SYS_TEXT_BASE           0x00000000
+#endif
 
 /* clocks */
 #if defined(CONFIG_CPU9G20)
 
 /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
 #define CONFIG_SYS_MATRIX_EBICSA_VAL           \
-       (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
-       AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
+               (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
+               AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
 
 /* SDRAM */
 /* SDRAMC_MR Mode register */
 /* setup SMC0, CS0 (NOR Flash) - 16-bit */
 #if defined(CONFIG_CPU9G20)
 #define CONFIG_SYS_SMC0_SETUP0_VAL                                     \
-               (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |     \
-                AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+               (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |     \
+                AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
 #define CONFIG_SYS_SMC0_PULSE0_VAL                                     \
-               (AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) |     \
-                AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
+               (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |     \
+                AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL     \
-               (AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
+               (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
 #define CONFIG_SYS_SMC0_MODE0_VAL                              \
-               (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |       \
-                AT91_SMC_DBW_16 |                              \
-                AT91_SMC_TDFMODE |                             \
-                AT91_SMC_TDF_(3))
+               (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
+                AT91_SMC_MODE_DBW_16 |                         \
+                AT91_SMC_MODE_TDF |                            \
+                AT91_SMC_MODE_TDF_CYCLE(3))
 #elif defined(CONFIG_CPU9260)
 #define CONFIG_SYS_SMC0_SETUP0_VAL                                     \
-               (AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |     \
-                AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
+               (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |     \
+                AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
 #define CONFIG_SYS_SMC0_PULSE0_VAL                                     \
-               (AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) |     \
-                AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
+               (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |     \
+                AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
 #define CONFIG_SYS_SMC0_CYCLE0_VAL     \
-               (AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
+               (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
 #define CONFIG_SYS_SMC0_MODE0_VAL                              \
-               (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |       \
-                AT91_SMC_DBW_16 |                              \
-                AT91_SMC_TDFMODE |                             \
-                AT91_SMC_TDF_(2))
+               (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
+                AT91_SMC_MODE_DBW_16 |                         \
+                AT91_SMC_MODE_TDF |                            \
+                AT91_SMC_MODE_TDF_CYCLE(2))
 #endif
 
 /* user reset enable */
 #define CONFIG_SYS_RSTC_RMR_VAL                        \
                (AT91_RSTC_KEY |                \
-               AT91_RSTC_PROCRST |             \
-               AT91_RSTC_RSTTYP_WAKEUP |       \
-               AT91_RSTC_RSTTYP_WATCHDOG)
+               AT91_RSTC_CR_PROCRST |          \
+               AT91_RSTC_MR_ERSTL(1) | \
+               AT91_RSTC_MR_ERSTL(2))
 
 /* Disable Watchdog */
 #define CONFIG_SYS_WDTC_WDMR_VAL                               \
-               (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |       \
-                AT91_WDT_WDV |                                 \
-                AT91_WDT_WDDIS |                               \
-                AT91_WDT_WDD)
+               (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
+                AT91_WDT_MR_WDV(0xfff) |                       \
+                AT91_WDT_MR_WDDIS |                            \
+                AT91_WDT_MR_WDD(0xfff))
 
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO       1
-#define CONFIG_ATMEL_USART     1
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_USART
 #undef CONFIG_USART0
 #undef CONFIG_USART1
 #undef CONFIG_USART2
-#define CONFIG_USART3          1       /* USART 3 is DBGU */
+#define CONFIG_USART3
 
 #define CONFIG_BOOTDELAY       3
 
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE      1
-#define CONFIG_BOOTP_BOOTPATH          1
-#define CONFIG_BOOTP_GATEWAY           1
-#define CONFIG_BOOTP_HOSTNAME          1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
 
 /*
  * Command line configuration.
 #undef CONFIG_CMD_LOADS
 #undef CONFIG_CMD_IMLS
 
-#define CONFIG_CMD_PING                1
-#define CONFIG_CMD_DHCP                1
-#define CONFIG_CMD_NAND                1
-#define CONFIG_CMD_USB         1
-#define CONFIG_CMD_FAT         1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MII
 
 /* SDRAM */
 #define CONFIG_NR_DRAM_BANKS   1
-#define PHYS_SDRAM             0x20000000
+#define CONFIG_SYS_SDRAM_BASE          0x20000000
 #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
-#define PHYS_SDRAM_SIZE                0x08000000      /* 128 MB */
+#define CONFIG_SYS_SDRAM_SIZE          (128 * 1024 * 1024)
 #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
 #else
-#define PHYS_SDRAM_SIZE                0x04000000      /* 64 MB */
+#define CONFIG_SYS_SDRAM_SIZE          (64 * 1024 * 1024)
 #define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
 #endif
 
 /* NAND flash */
-#define CONFIG_NAND_ATMEL                      1
+#define CONFIG_NAND_ATMEL
 #define NAND_MAX_CHIPS                         1
 #define CONFIG_SYS_MAX_NAND_DEVICE             1
 #define CONFIG_SYS_NAND_BASE                   0x40000000
 #define CONFIG_SYS_NAND_DBW_8                  1
-#define CONFIG_SYS_NAND_READY_PIN              AT91_PIN_PC13
-#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN              AT91_PIO_PORTC, 13
+#define CONFIG_SYS_NAND_ENABLE_PIN             AT91_PIO_PORTC, 14
 #define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
 
 /* NOR flash */
-#define CONFIG_SYS_FLASH_CFI                   1
-#define CONFIG_FLASH_CFI_DRIVER                        1
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
 #define PHYS_FLASH_1                           0x10000000
 #define PHYS_FLASH_2                           0x12000000
 #define CONFIG_SYS_FLASH_BANKS_LIST            \
 #define CONFIG_SYS_MAX_FLASH_SECT              (255+4)
 #define CONFIG_SYS_MAX_FLASH_BANKS             2
 #define CONFIG_SYS_FLASH_CFI_WIDTH             FLASH_CFI_16BIT
-#define CONFIG_SYS_FLASH_EMPTY_INFO            1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      1
-#define CONFIG_SYS_FLASH_PROTECTION            1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_MONITOR_BASE                        PHYS_FLASH_1
+#endif
 
 /* Ethernet */
-#define CONFIG_MACB                            1
-#define CONFIG_RMII                            1
-#define CONFIG_RESET_PHY_R                     1
-#define CONFIG_NET_MULTI                       1
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT                 20
-#define CONFIG_MACB_SEARCH_PHY                 1
+#define CONFIG_MACB_SEARCH_PHY
 
 /* LEDS */
 /* Status LED */
-#define CONFIG_STATUS_LED                      1 /* Status LED enabled */
-#define CONFIG_BOARD_SPECIFIC_LED              1
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
 #define STATUS_LED_RED                         0
 #define STATUS_LED_GREEN                       1
 #define STATUS_LED_YELLOW                      2
 /* Optional value */
 #define STATUS_LED_BOOT                                STATUS_LED_BIT
 
-#define CONFIG_RED_LED                         AT91_PIN_PC11
-#define CONFIG_GREEN_LED                       AT91_PIN_PC12
-#define CONFIG_YELLOW_LED                      AT91_PIN_PC7
-#define CONFIG_BLUE_LED                                AT91_PIN_PC9
+#define CONFIG_RED_LED                         AT91_PIO_PORTC, 11
+#define CONFIG_GREEN_LED                       AT91_PIO_PORTC, 12
+#define CONFIG_YELLOW_LED                      AT91_PIO_PORTC, 7
+#define CONFIG_BLUE_LED                                AT91_PIO_PORTC, 9
 
 /* USB */
-#define CONFIG_USB_ATMEL                       1
-#define CONFIG_USB_OHCI_NEW                    1
-#define CONFIG_DOS_PARTITION                   1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT           1
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
 #define CONFIG_SYS_USB_OHCI_REGS_BASE          0x00500000
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9g20"
+#elif defined(CONFIG_CPU9260)
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME          "at91sam9260"
+#endif
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     2
-#define CONFIG_USB_STORAGE                     1
+#define CONFIG_USB_STORAGE
 
 #define CONFIG_SYS_LOAD_ADDR                   0x21000000
+#define CONFIG_LOADADDR                                CONFIG_SYS_LOAD_ADDR
 
-#define CONFIG_SYS_MEMTEST_START               PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END                 0x21e00000
+#define CONFIG_SYS_MEMTEST_START               CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END                 \
+       (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
 
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_SYS_USE_FLASH
+#else
+#define CONFIG_SYS_USE_FLASH
 #undef CONFIG_SYS_USE_NANDFLASH
-#define CONFIG_SYS_USE_FLASH                   1
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_BASEDIR     "cpu9G20"
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_BASEDIR     "cpu9260"
+#endif
 
 #if defined(CONFIG_SYS_USE_FLASH)
-#define CONFIG_ENV_IS_IN_FLASH         1
+#define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OFFSET              0x40000
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define        CONFIG_ENV_SIZE                 0x20000
-#define CONFIG_ENV_OVERWRITE           1
+#define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_BOOTCOMMAND             "run flashboot"
 
-#define MTDIDS_DEFAULT         "nor0=physmap-flash.0,nand0=atmel_nand"
+#define MTDIDS_DEFAULT         "nor0=physmap-flash.0,nand0=atmel_nand"
 #define MTDPARTS_DEFAULT               \
        "mtdparts=physmap-flash.0:"     \
                "256k(u-boot)ro,"       \
 
 #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
 
-#if defined(CONFIG_CPU9G20)
-#define CONFIG_SYS_BASEDIR     "cpu9G20"
-#elif defined(CONFIG_CPU9260)
-#define CONFIG_SYS_BASEDIR     "cpu9260"
-#endif
-
 #define CONFIG_EXTRA_ENV_SETTINGS                              \
        "mtdids=" MTDIDS_DEFAULT "\0"                           \
        "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
        "partition=nand0,0\0"                                   \
        "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
-       "ramboot=tftpboot 0x22000000 cpu9260/uImage;"           \
+       "ramboot=tftpboot 0x22000000 $(basedir)/uImage;"        \
                "run ramargs;bootm 22000000\0"                  \
        "flashboot=run ramargs;bootm 0x10060000\0"              \
        "basedir=" CONFIG_SYS_BASEDIR "\0"                      \
                "0x10220000 0x13ffffff;cp.b 0x24000000 "        \
                "0x10220000 $(filesize)\0" \
        ""
+#elif defined(CONFIG_NANDBOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              0x60000
+#define CONFIG_ENV_OFFSET_REDUND       0x80000
+#define CONFIG_ENV_SECT_SIZE           0x20000
+#define        CONFIG_ENV_SIZE                 0x20000
+#define CONFIG_ENV_SIZE_REDUND         (CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTCOMMAND             "run flashboot"
+
+#define MTDIDS_DEFAULT         "nand0=atmel_nand"
+#define MTDPARTS_DEFAULT               \
+       "mtdparts=atmel_nand:"          \
+               "128k(bootstrap)ro,"    \
+               "256k(u-boot)ro,"       \
+               "128k(u-boot-env)ro,"   \
+               "128k(u-boot-env2)ro,"  \
+               "2M(kernel),"   \
+               "-(rootfs)"
+
+#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs "     \
+       "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                              \
+       "mtdids=" MTDIDS_DEFAULT "\0"                           \
+       "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
+       "partition=nand0,5\0"                                   \
+       "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
+       "ramboot=tftpboot 0x22000000 $(basedir)/uImage;"        \
+               "run ramargs;bootm 22000000\0"                  \
+       "flashboot=run ramargs; nand read 0x22000000 0xA0000 "  \
+               "0x200000; bootm 0x22000000\0"                  \
+       "basedir=" CONFIG_SYS_BASEDIR "\0"                      \
+       "u-boot=u-boot-eukrea-cpu9260.bin\0"                    \
+       "kernel=uImage-eukrea-cpu9260.bin\0"                    \
+       "rootfs=image-eukrea-cpu9260.ubi\0"                     \
+       "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; "        \
+               "nand erase 20000 40000; "                      \
+               "nand write ${loadaddr} 20000 40000\0"          \
+       "updtui=tftp ${loadaddr} $(basedir)/${kernel}; "        \
+               "nand erase a0000 200000; "                     \
+               "nand write ${loadaddr} a0000 200000\0"         \
+       "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; "       \
+               "nand erase  2a0000 fd60000; "                  \
+               "nand write ${loadaddr} 2a0000 ${filesize}\0"
 #endif
 
 #define CONFIG_BAUDRATE                        115200
 #define CONFIG_SYS_MAXARGS             16
 #define CONFIG_SYS_PBSIZE              \
                (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_LONGHELP            1
-#define CONFIG_CMDLINE_EDITING         1
-#define CONFIG_SILENT_CONSOLE          1
-#define CONFIG_NETCONSOLE              1
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_NETCONSOLE
 
 /*
  * Size of malloc() pool
 #define CONFIG_SYS_MALLOC_LEN          \
                ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 
+#define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+                               GENERATED_GBL_DATA_SIZE)
+
 #define CONFIG_STACKSIZE               (32 * 1024)
 
 #if defined(CONFIG_USE_IRQ)