board/spear/common: move code to arch/arm/cpu/arm926ejs/spear/
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 15 Aug 2017 20:52:44 +0000 (22:52 +0200)
committerTom Rini <trini@konsulko.com>
Sat, 26 Aug 2017 18:56:10 +0000 (14:56 -0400)
The code in board/spear/common/ is not board-specific but
SoC-specific. Therefore, boards from other vendors than "spear" may
want to re-use this code, which is currently difficult with the code
being placed in board/spear/common/.

Since this code really is SoC-specific, this commit moves it to
arch/arm/cpu/arm926ejs/spear/, with the rest of the SPEAr related
code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
arch/arm/cpu/arm926ejs/spear/Makefile
arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spr_misc.c [new file with mode: 0644]
board/spear/common/Makefile [deleted file]
board/spear/common/spr_lowlevel_init.S [deleted file]
board/spear/common/spr_misc.c [deleted file]

index 7b15d4ef7ef61cd7c0a59268234f47f16f997e04..39924015907caf0c34c0720b69bff8d8a56682b4 100644 (file)
@@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
 obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
 obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
 obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+else
+obj-y += spr_misc.o spr_lowlevel_init.o
 endif
 
 extra-$(CONFIG_SPL_BUILD) := start.o
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S
new file mode 100644 (file)
index 0000000..6494883
--- /dev/null
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2006
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+
+/*
+ * platform specific initializations are already done in Xloader
+ * Initializations already done include
+ * DDR, PLLs, IP's clock enable and reset release etc
+ */
+.globl lowlevel_init
+lowlevel_init:
+       mov     pc, lr
+
+/* void setfreq(unsigned int device, unsigned int frequency) */
+.global setfreq
+setfreq:
+       stmfd   sp!,{r14}
+       stmfd   sp!,{r0-r12}
+
+       mov     r8,sp
+       ldr     sp,SRAM_STACK_V
+
+       /* Saving the function arguements for later use */
+       mov     r4,r0
+       mov     r5,r1
+
+       /* Putting DDR into self refresh */
+       ldr     r0,DDR_07_V
+       ldr     r1,[r0]
+       ldr     r2,DDR_ACTIVE_V
+       bic     r1, r1, r2
+       str     r1,[r0]
+       ldr     r0,DDR_57_V
+       ldr     r1,[r0]
+       ldr     r2,CYCLES_MASK_V
+       bic     r1, r1, r2
+       ldr     r2,REFRESH_CYCLES_V
+       orr     r1, r1, r2, lsl #16
+       str     r1,[r0]
+       ldr     r0,DDR_07_V
+       ldr     r1,[r0]
+       ldr     r2,SREFRESH_MASK_V
+       orr     r1, r1, r2
+       str     r1,[r0]
+
+       /* flush pipeline */
+       b       flush
+       .align 5
+flush:
+       /* Delay to ensure self refresh mode */
+       ldr     r0,SREFRESH_DELAY_V
+delay:
+       sub     r0,r0,#1
+       cmp     r0,#0
+       bne     delay
+
+       /* Putting system in slow mode */
+       ldr     r0,SCCTRL_V
+       mov     r1,#2
+       str     r1,[r0]
+
+       /* Changing PLL(1/2) frequency */
+       mov     r0,r4
+       mov     r1,r5
+
+       cmp     r4,#0
+       beq     pll1_freq
+
+       /* Change PLL2 (DDR frequency) */
+       ldr     r6,PLL2_FREQ_V
+       ldr     r7,PLL2_CNTL_V
+       b       pll2_freq
+
+pll1_freq:
+       /* Change PLL1 (CPU frequency) */
+       ldr     r6,PLL1_FREQ_V
+       ldr     r7,PLL1_CNTL_V
+
+pll2_freq:
+       mov     r0,r6
+       ldr     r1,[r0]
+       ldr     r2,PLLFREQ_MASK_V
+       bic     r1,r1,r2
+       mov     r2,r5,lsr#1
+       orr     r1,r1,r2,lsl#24
+       str     r1,[r0]
+
+       mov     r0,r7
+       ldr     r1,P1C0A_V
+       str     r1,[r0]
+       ldr     r1,P1C0E_V
+       str     r1,[r0]
+       ldr     r1,P1C06_V
+       str     r1,[r0]
+       ldr     r1,P1C0E_V
+       str     r1,[r0]
+
+lock:
+       ldr     r1,[r0]
+       and     r1,r1,#1
+       cmp     r1,#0
+       beq     lock
+
+       /* Putting system back to normal mode */
+       ldr     r0,SCCTRL_V
+       mov     r1,#4
+       str     r1,[r0]
+
+       /* Putting DDR back to normal */
+       ldr     r0,DDR_07_V
+       ldr     r1,[R0]
+       ldr     r2,SREFRESH_MASK_V
+       bic     r1, r1, r2
+       str     r1,[r0]
+       ldr     r2,DDR_ACTIVE_V
+       orr     r1, r1, r2
+       str     r1,[r0]
+
+       /* Delay to ensure self refresh mode */
+       ldr     r0,SREFRESH_DELAY_V
+1:
+       sub     r0,r0,#1
+       cmp     r0,#0
+       bne     1b
+
+       mov     sp,r8
+       /* Resuming back to code */
+       ldmia   sp!,{r0-r12}
+       ldmia   sp!,{pc}
+
+SCCTRL_V:
+       .word 0xfca00000
+PLL1_FREQ_V:
+       .word 0xfca8000C
+PLL1_CNTL_V:
+       .word 0xfca80008
+PLL2_FREQ_V:
+       .word 0xfca80018
+PLL2_CNTL_V:
+       .word 0xfca80014
+PLLFREQ_MASK_V:
+       .word 0xff000000
+P1C0A_V:
+       .word 0x1C0A
+P1C0E_V:
+       .word 0x1C0E
+P1C06_V:
+       .word 0x1C06
+
+SREFRESH_DELAY_V:
+       .word 0x9999
+SRAM_STACK_V:
+       .word 0xD2800600
+DDR_07_V:
+       .word 0xfc60001c
+DDR_ACTIVE_V:
+       .word 0x01000000
+DDR_57_V:
+       .word 0xfc6000e4
+CYCLES_MASK_V:
+       .word 0xffff0000
+REFRESH_CYCLES_V:
+       .word 0xf0f0
+SREFRESH_MASK_V:
+       .word 0x00010000
+
+.global setfreq_sz
+setfreq_sz:
+       .word setfreq_sz - setfreq
diff --git a/arch/arm/cpu/arm926ejs/spear/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c
new file mode 100644 (file)
index 0000000..a02304f
--- /dev/null
@@ -0,0 +1,249 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <net.h>
+#include <linux/mtd/st_smi.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_emi.h>
+#include <asm/arch/spr_defs.h>
+
+#define CPU            0
+#define DDR            1
+#define SRAM_REL       0xD2801000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer);
+#endif
+
+int dram_init(void)
+{
+       /* Store complete RAM size and return */
+       gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
+
+       return 0;
+}
+
+int dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = gd->ram_size;
+
+       return 0;
+}
+
+int board_early_init_f()
+{
+#if defined(CONFIG_ST_SMI)
+       smi_init();
+#endif
+       return 0;
+}
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_NET)
+       uchar mac_id[6];
+
+       if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
+               eth_env_set_enetaddr("ethaddr", mac_id);
+#endif
+       env_set("verify", "n");
+
+#if defined(CONFIG_SPEAR_USBTTY)
+       env_set("stdin", "usbtty");
+       env_set("stdout", "usbtty");
+       env_set("stderr", "usbtty");
+
+#ifndef CONFIG_SYS_NO_DCACHE
+       dcache_enable();
+#endif
+#endif
+       return 0;
+}
+
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+       unsigned int tap;
+       unsigned int tsdp;
+       unsigned int tdpw;
+       unsigned int tdpr;
+       unsigned int tdcs;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+       .tap = 0x10,
+       .tsdp = 0x05,
+       .tdpw = 0x0a,
+       .tdpr = 0x0a,
+       .tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+       .tap = 0xf,
+       .tsdp = 0x0,
+       .tdpw = 0xff,
+       .tdpr = 0x111,
+       .tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+       const struct cust_emi_para *p = &emi_timing_m28w640hc;
+       struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+       unsigned int cs;
+       unsigned int val, tmp;
+
+       val = readl(CONFIG_SPEAR_RASBASE);
+
+       if (val & EMI_ACKMSK)
+               tmp = 0x3f;
+       else
+               tmp = 0x0;
+
+       writel(tmp, &emi_regs_p->ack);
+
+       for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+               writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+               writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+               writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+               writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+               writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+               writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+                      &emi_regs_p->bank_regs[cs].control);
+       }
+}
+#endif
+
+int spear_board_init(ulong mach_type)
+{
+       gd->bd->bi_arch_number = mach_type;
+
+       /* adress of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+#ifdef CONFIG_SPEAR_EMI
+       spear_emi_init();
+#endif
+       return 0;
+}
+
+#if defined(CONFIG_CMD_NET)
+static int i2c_read_mac(uchar *buffer)
+{
+       u8 buf[2];
+
+       i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+       /* Check if mac in i2c memory is valid */
+       if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+               /* Valid mac address is saved in i2c eeprom */
+               i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
+               return 0;
+       }
+
+       return -1;
+}
+
+static int write_mac(uchar *mac)
+{
+       u8 buf[2];
+
+       buf[0] = (u8)MAGIC_BYTE0;
+       buf[1] = (u8)MAGIC_BYTE1;
+       i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+       buf[0] = (u8)~MAGIC_BYTE0;
+       buf[1] = (u8)~MAGIC_BYTE1;
+
+       i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
+
+       /* check if valid MAC address is saved in I2C EEPROM or not? */
+       if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
+               i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
+               puts("I2C EEPROM written with mac address \n");
+               return 0;
+       }
+
+       puts("I2C EEPROM writing failed\n");
+       return -1;
+}
+#endif
+
+int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       void (*sram_setfreq) (unsigned int, unsigned int);
+       unsigned int frequency;
+#if defined(CONFIG_CMD_NET)
+       unsigned char mac[6];
+#endif
+
+       if ((argc > 3) || (argc < 2))
+               return cmd_usage(cmdtp);
+
+       if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
+
+               frequency = simple_strtoul(argv[2], NULL, 0);
+
+               if (frequency > 333) {
+                       printf("Frequency is limited to 333MHz\n");
+                       return 1;
+               }
+
+               sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
+
+               if (!strcmp(argv[1], "cpufreq")) {
+                       sram_setfreq(CPU, frequency);
+                       printf("CPU frequency changed to %u\n", frequency);
+               } else {
+                       sram_setfreq(DDR, frequency);
+                       printf("DDR frequency changed to %u\n", frequency);
+               }
+
+               return 0;
+
+#if defined(CONFIG_CMD_NET)
+       } else if (!strcmp(argv[1], "ethaddr")) {
+
+               u32 reg;
+               char *e, *s = argv[2];
+               for (reg = 0; reg < 6; ++reg) {
+                       mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+                       if (s)
+                               s = (*e) ? e + 1 : e;
+               }
+               write_mac(mac);
+
+               return 0;
+#endif
+       } else if (!strcmp(argv[1], "print")) {
+#if defined(CONFIG_CMD_NET)
+               if (!i2c_read_mac(mac)) {
+                       printf("Ethaddr (from i2c mem) = %pM\n", mac);
+               } else {
+                       printf("Ethaddr (from i2c mem) = Not set\n");
+               }
+#endif
+               return 0;
+       }
+
+       return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
+          "configure chip",
+          "chip_config cpufreq/ddrfreq frequency\n"
+#if defined(CONFIG_CMD_NET)
+          "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
+#endif
+          "chip_config print");
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
deleted file mode 100644 (file)
index b0ba320..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-# necessary to create built-in.o
-obj- := __dummy__.o
-else
-obj-y  := spr_misc.o
-obj-y  += spr_lowlevel_init.o
-endif
diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S
deleted file mode 100644 (file)
index 6494883..0000000
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * (C) Copyright 2006
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-
-/*
- * platform specific initializations are already done in Xloader
- * Initializations already done include
- * DDR, PLLs, IP's clock enable and reset release etc
- */
-.globl lowlevel_init
-lowlevel_init:
-       mov     pc, lr
-
-/* void setfreq(unsigned int device, unsigned int frequency) */
-.global setfreq
-setfreq:
-       stmfd   sp!,{r14}
-       stmfd   sp!,{r0-r12}
-
-       mov     r8,sp
-       ldr     sp,SRAM_STACK_V
-
-       /* Saving the function arguements for later use */
-       mov     r4,r0
-       mov     r5,r1
-
-       /* Putting DDR into self refresh */
-       ldr     r0,DDR_07_V
-       ldr     r1,[r0]
-       ldr     r2,DDR_ACTIVE_V
-       bic     r1, r1, r2
-       str     r1,[r0]
-       ldr     r0,DDR_57_V
-       ldr     r1,[r0]
-       ldr     r2,CYCLES_MASK_V
-       bic     r1, r1, r2
-       ldr     r2,REFRESH_CYCLES_V
-       orr     r1, r1, r2, lsl #16
-       str     r1,[r0]
-       ldr     r0,DDR_07_V
-       ldr     r1,[r0]
-       ldr     r2,SREFRESH_MASK_V
-       orr     r1, r1, r2
-       str     r1,[r0]
-
-       /* flush pipeline */
-       b       flush
-       .align 5
-flush:
-       /* Delay to ensure self refresh mode */
-       ldr     r0,SREFRESH_DELAY_V
-delay:
-       sub     r0,r0,#1
-       cmp     r0,#0
-       bne     delay
-
-       /* Putting system in slow mode */
-       ldr     r0,SCCTRL_V
-       mov     r1,#2
-       str     r1,[r0]
-
-       /* Changing PLL(1/2) frequency */
-       mov     r0,r4
-       mov     r1,r5
-
-       cmp     r4,#0
-       beq     pll1_freq
-
-       /* Change PLL2 (DDR frequency) */
-       ldr     r6,PLL2_FREQ_V
-       ldr     r7,PLL2_CNTL_V
-       b       pll2_freq
-
-pll1_freq:
-       /* Change PLL1 (CPU frequency) */
-       ldr     r6,PLL1_FREQ_V
-       ldr     r7,PLL1_CNTL_V
-
-pll2_freq:
-       mov     r0,r6
-       ldr     r1,[r0]
-       ldr     r2,PLLFREQ_MASK_V
-       bic     r1,r1,r2
-       mov     r2,r5,lsr#1
-       orr     r1,r1,r2,lsl#24
-       str     r1,[r0]
-
-       mov     r0,r7
-       ldr     r1,P1C0A_V
-       str     r1,[r0]
-       ldr     r1,P1C0E_V
-       str     r1,[r0]
-       ldr     r1,P1C06_V
-       str     r1,[r0]
-       ldr     r1,P1C0E_V
-       str     r1,[r0]
-
-lock:
-       ldr     r1,[r0]
-       and     r1,r1,#1
-       cmp     r1,#0
-       beq     lock
-
-       /* Putting system back to normal mode */
-       ldr     r0,SCCTRL_V
-       mov     r1,#4
-       str     r1,[r0]
-
-       /* Putting DDR back to normal */
-       ldr     r0,DDR_07_V
-       ldr     r1,[R0]
-       ldr     r2,SREFRESH_MASK_V
-       bic     r1, r1, r2
-       str     r1,[r0]
-       ldr     r2,DDR_ACTIVE_V
-       orr     r1, r1, r2
-       str     r1,[r0]
-
-       /* Delay to ensure self refresh mode */
-       ldr     r0,SREFRESH_DELAY_V
-1:
-       sub     r0,r0,#1
-       cmp     r0,#0
-       bne     1b
-
-       mov     sp,r8
-       /* Resuming back to code */
-       ldmia   sp!,{r0-r12}
-       ldmia   sp!,{pc}
-
-SCCTRL_V:
-       .word 0xfca00000
-PLL1_FREQ_V:
-       .word 0xfca8000C
-PLL1_CNTL_V:
-       .word 0xfca80008
-PLL2_FREQ_V:
-       .word 0xfca80018
-PLL2_CNTL_V:
-       .word 0xfca80014
-PLLFREQ_MASK_V:
-       .word 0xff000000
-P1C0A_V:
-       .word 0x1C0A
-P1C0E_V:
-       .word 0x1C0E
-P1C06_V:
-       .word 0x1C06
-
-SREFRESH_DELAY_V:
-       .word 0x9999
-SRAM_STACK_V:
-       .word 0xD2800600
-DDR_07_V:
-       .word 0xfc60001c
-DDR_ACTIVE_V:
-       .word 0x01000000
-DDR_57_V:
-       .word 0xfc6000e4
-CYCLES_MASK_V:
-       .word 0xffff0000
-REFRESH_CYCLES_V:
-       .word 0xf0f0
-SREFRESH_MASK_V:
-       .word 0x00010000
-
-.global setfreq_sz
-setfreq_sz:
-       .word setfreq_sz - setfreq
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
deleted file mode 100644 (file)
index a02304f..0000000
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2009
- * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <i2c.h>
-#include <net.h>
-#include <linux/mtd/st_smi.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spr_emi.h>
-#include <asm/arch/spr_defs.h>
-
-#define CPU            0
-#define DDR            1
-#define SRAM_REL       0xD2801000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer);
-#endif
-
-int dram_init(void)
-{
-       /* Store complete RAM size and return */
-       gd->ram_size = get_ram_size(PHYS_SDRAM_1, PHYS_SDRAM_1_MAXSIZE);
-
-       return 0;
-}
-
-int dram_init_banksize(void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size = gd->ram_size;
-
-       return 0;
-}
-
-int board_early_init_f()
-{
-#if defined(CONFIG_ST_SMI)
-       smi_init();
-#endif
-       return 0;
-}
-int misc_init_r(void)
-{
-#if defined(CONFIG_CMD_NET)
-       uchar mac_id[6];
-
-       if (!eth_env_get_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id))
-               eth_env_set_enetaddr("ethaddr", mac_id);
-#endif
-       env_set("verify", "n");
-
-#if defined(CONFIG_SPEAR_USBTTY)
-       env_set("stdin", "usbtty");
-       env_set("stdout", "usbtty");
-       env_set("stderr", "usbtty");
-
-#ifndef CONFIG_SYS_NO_DCACHE
-       dcache_enable();
-#endif
-#endif
-       return 0;
-}
-
-#ifdef CONFIG_SPEAR_EMI
-struct cust_emi_para {
-       unsigned int tap;
-       unsigned int tsdp;
-       unsigned int tdpw;
-       unsigned int tdpr;
-       unsigned int tdcs;
-};
-
-/* EMI timing setting of m28w640hc of linux kernel */
-const struct cust_emi_para emi_timing_m28w640hc = {
-       .tap = 0x10,
-       .tsdp = 0x05,
-       .tdpw = 0x0a,
-       .tdpr = 0x0a,
-       .tdcs = 0x05,
-};
-
-/* EMI timing setting of bootrom */
-const struct cust_emi_para emi_timing_bootrom = {
-       .tap = 0xf,
-       .tsdp = 0x0,
-       .tdpw = 0xff,
-       .tdpr = 0x111,
-       .tdcs = 0x02,
-};
-
-void spear_emi_init(void)
-{
-       const struct cust_emi_para *p = &emi_timing_m28w640hc;
-       struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
-       unsigned int cs;
-       unsigned int val, tmp;
-
-       val = readl(CONFIG_SPEAR_RASBASE);
-
-       if (val & EMI_ACKMSK)
-               tmp = 0x3f;
-       else
-               tmp = 0x0;
-
-       writel(tmp, &emi_regs_p->ack);
-
-       for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
-               writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
-               writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
-               writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
-               writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
-               writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
-               writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
-                      &emi_regs_p->bank_regs[cs].control);
-       }
-}
-#endif
-
-int spear_board_init(ulong mach_type)
-{
-       gd->bd->bi_arch_number = mach_type;
-
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-
-#ifdef CONFIG_SPEAR_EMI
-       spear_emi_init();
-#endif
-       return 0;
-}
-
-#if defined(CONFIG_CMD_NET)
-static int i2c_read_mac(uchar *buffer)
-{
-       u8 buf[2];
-
-       i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-       /* Check if mac in i2c memory is valid */
-       if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-               /* Valid mac address is saved in i2c eeprom */
-               i2c_read(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, buffer, MAC_LEN);
-               return 0;
-       }
-
-       return -1;
-}
-
-static int write_mac(uchar *mac)
-{
-       u8 buf[2];
-
-       buf[0] = (u8)MAGIC_BYTE0;
-       buf[1] = (u8)MAGIC_BYTE1;
-       i2c_write(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-       buf[0] = (u8)~MAGIC_BYTE0;
-       buf[1] = (u8)~MAGIC_BYTE1;
-
-       i2c_read(CONFIG_I2C_CHIPADDRESS, MAGIC_OFF, 1, buf, MAGIC_LEN);
-
-       /* check if valid MAC address is saved in I2C EEPROM or not? */
-       if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) {
-               i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN);
-               puts("I2C EEPROM written with mac address \n");
-               return 0;
-       }
-
-       puts("I2C EEPROM writing failed\n");
-       return -1;
-}
-#endif
-
-int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       void (*sram_setfreq) (unsigned int, unsigned int);
-       unsigned int frequency;
-#if defined(CONFIG_CMD_NET)
-       unsigned char mac[6];
-#endif
-
-       if ((argc > 3) || (argc < 2))
-               return cmd_usage(cmdtp);
-
-       if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
-
-               frequency = simple_strtoul(argv[2], NULL, 0);
-
-               if (frequency > 333) {
-                       printf("Frequency is limited to 333MHz\n");
-                       return 1;
-               }
-
-               sram_setfreq = memcpy((void *)SRAM_REL, setfreq, setfreq_sz);
-
-               if (!strcmp(argv[1], "cpufreq")) {
-                       sram_setfreq(CPU, frequency);
-                       printf("CPU frequency changed to %u\n", frequency);
-               } else {
-                       sram_setfreq(DDR, frequency);
-                       printf("DDR frequency changed to %u\n", frequency);
-               }
-
-               return 0;
-
-#if defined(CONFIG_CMD_NET)
-       } else if (!strcmp(argv[1], "ethaddr")) {
-
-               u32 reg;
-               char *e, *s = argv[2];
-               for (reg = 0; reg < 6; ++reg) {
-                       mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
-                       if (s)
-                               s = (*e) ? e + 1 : e;
-               }
-               write_mac(mac);
-
-               return 0;
-#endif
-       } else if (!strcmp(argv[1], "print")) {
-#if defined(CONFIG_CMD_NET)
-               if (!i2c_read_mac(mac)) {
-                       printf("Ethaddr (from i2c mem) = %pM\n", mac);
-               } else {
-                       printf("Ethaddr (from i2c mem) = Not set\n");
-               }
-#endif
-               return 0;
-       }
-
-       return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
-          "configure chip",
-          "chip_config cpufreq/ddrfreq frequency\n"
-#if defined(CONFIG_CMD_NET)
-          "chip_config ethaddr XX:XX:XX:XX:XX:XX\n"
-#endif
-          "chip_config print");