The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.
The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
#endif
#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
+struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
#endif
#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
+struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
#endif
#ifdef CONFIG_USB_GADGET
-static struct s3c_plat_otg_data bcm_otg_data = {
+static struct dwc2_plat_otg_data bcm_otg_data = {
.regs_otg = HSOTG_BASE_ADDR
};
}
#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
+struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
#endif
#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
+struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
return 0;
}
-struct s3c_plat_otg_data s5pc110_otg_data = {
+struct dwc2_plat_otg_data s5pc110_otg_data = {
.phy_control = s5pc1xx_phy_control,
.regs_phy = S5PC110_PHY_BASE,
.regs_otg = S5PC110_OTG_BASE,
return regulator_set_mode(dev, OPMODE_LPM);
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,
#endif
static void check_hw_revision(void);
-struct s3c_plat_otg_data s5pc210_otg_data;
+struct dwc2_plat_otg_data s5pc210_otg_data;
int exynos_init(void)
{
return 0;
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
return 0;
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4X12_USBPHY_BASE,
.regs_otg = EXYNOS4X12_USBOTG_BASE,
return 0;
}
-struct s3c_plat_otg_data s5pc210_otg_data = {
+struct dwc2_plat_otg_data s5pc210_otg_data = {
.phy_control = s5pc210_phy_control,
.regs_phy = EXYNOS4_USBPHY_BASE,
.regs_otg = EXYNOS4_USBOTG_BASE,
#endif
#ifdef CONFIG_USB_GADGET
-struct s3c_plat_otg_data socfpga_otg_data = {
+struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
* probe - binds to the platform device
*/
-int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
+int s3c_udc_probe(struct dwc2_plat_otg_data *pdata)
{
struct dwc2_udc *dev = &memory;
int retval = 0;
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
- struct s3c_plat_otg_data *pdata;
+ struct dwc2_plat_otg_data *pdata;
int ep0state;
struct dwc2_ep ep[DWC2_MAX_ENDPOINTS];
#define PHY0_SLEEP (1 << 5)
-struct s3c_plat_otg_data {
+struct dwc2_plat_otg_data {
int (*phy_control)(int on);
unsigned int regs_phy;
unsigned int regs_otg;
unsigned int usb_gusbcfg;
};
-int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
+int s3c_udc_probe(struct dwc2_plat_otg_data *pdata);
#endif