Be consistent with register names in common QC/A header

diff --git a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S
index 1bf0e6b1cafc87020049c14c864605149598b351..442f957426298c53023f0a8ba21556e4909830c1 100644 (file)
--- a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S
+++ b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S
@@ -64,7 +64,7 @@ set_xtal_40mhz:
  * Several WLAN module resets as in Atheros (Q)SDK
  */
 wlan_rst_init:
-       li  t8, QCA_RST_RST_REG
+       li  t8, QCA_RST_RESET_REG
 
        /* 2x WLAN resets */
        lw  t9, 0(t8)
@@ -90,7 +90,7 @@ wlan_rst_init:
        nop
 
 wlan_rst:
-       li  t8, QCA_RST_RST_REG
+       li  t8, QCA_RST_RESET_REG
 
        lw  t9, 0(t8)
        or  t9, t9, QCA_RST_RESET_WLAN_RST_MASK

diff --git a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S
index 31a66f18f2af5445cfd444359bd52edd44e930cc..5ecfa697bff04fc388ea8c7fe7618dc2c774b131 100755 (executable)
--- a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S
+++ b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S
@@ -76,7 +76,7 @@ ahb_max_timeout:
  * TODO: do we need to reset RTC at all?
  */
 rtc_reset:
-       li  t8, QCA_RST_RST_REG
+       li  t8, QCA_RST_RESET_REG
        lw  t9, 0(t8)
        or  t9, t9, QCA_RST_RESET_RTC_RST_MASK
        sw  t9, 0(t8)

diff --git a/u-boot/cpu/mips/ar7240/qca_common.c b/u-boot/cpu/mips/ar7240/qca_common.c
index 6d50f80147d681dfbf7ef758b36c289d9784d24a..6c87659e1c21782f75d7388a88cb9a713eab8687 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_common.c
+++ b/u-boot/cpu/mips/ar7240/qca_common.c
@@ -1,7 +1,7 @@
 /*
  * Qualcomm/Atheros WiSoCs common/helper functions
  *
- * Copyright (C) 2015 Piotr Dymacz <piotr@dymacz.pl>
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
  *
  * SPDX-License-Identifier: GPL-2.0
  */
@@ -28,7 +28,7 @@ void qca_full_chip_reset(void)
        volatile u32 i = 1;
 
        do {
-               qca_soc_reg_write(QCA_RST_RST_REG,
+               qca_soc_reg_write(QCA_RST_RESET_REG,
                                                  QCA_RST_RESET_FULL_CHIP_RST_MASK
                                                  | QCA_RST_RESET_DDR_RST_MASK);
        } while (i);

diff --git a/u-boot/cpu/mips/ar7240/qca_gpio_init.S b/u-boot/cpu/mips/ar7240/qca_gpio_init.S
index 433c2e427ad23d54b434ab3bbb3188b78e8ce197..9009928411cccd7602dfd279eb5a86a36621cc88 100644 (file)
--- a/u-boot/cpu/mips/ar7240/qca_gpio_init.S
+++ b/u-boot/cpu/mips/ar7240/qca_gpio_init.S
@@ -465,7 +465,7 @@ first_boot:
        nop
 
 full_reset:
-       li t8, QCA_RST_RST_REG
+       li t8, QCA_RST_RESET_REG
        lw t9, 0(t8)
        or t9, t9, QCA_RST_RESET_FULL_CHIP_RST_MASK
        sw t9, 0(t8)

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index 53879d176201668e57789943d94105bdb73c93f6..5a1395fa58a75ee493f0851b4cd31028621d24d4 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -1246,7 +1246,7 @@
 #define QCA_RST_MISC_INTERRUPT_STATUS_REG              QCA_RST_BASE_REG + 0x10
 #define QCA_RST_MISC_INTERRUPT_MASK_REG                        QCA_RST_BASE_REG + 0x14
 #define QCA_RST_GLOBALINTERRUPT_STATUS_REG             QCA_RST_BASE_REG + 0x18
-#define QCA_RST_RST_REG                                                        QCA_RST_BASE_REG + 0x1C
+#define QCA_RST_RESET_REG                                              QCA_RST_BASE_REG + 0x1C
 #define QCA_RST_REVISION_ID_REG                                        QCA_RST_BASE_REG + 0x90
 #define QCA_RST_GENERAL_TIMER2_REG                             QCA_RST_BASE_REG + 0x94
 #define QCA_RST_GENERAL_TIMER2_RELOAD_REG              QCA_RST_BASE_REG + 0x98