};
&qspi {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&qspi {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
&qspi {
+ u-boot,dm-pre-reloc;
status = "okay";
};
};
usb_phy0: phy0 {
- compatible = "usb-nop-xceiv";
#phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ reset-gpios = <&gpio0 46 1>;
};
};
#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
#define ZYNQ_GEM_BASEADDR3 0xFF0E0000
-#define ZYNQ_SPI_BASEADDR0 0xFF040000
-#define ZYNQ_SPI_BASEADDR1 0xFF050000
-
#define ZYNQ_I2C_BASEADDR0 0xFF020000
#define ZYNQ_I2C_BASEADDR1 0xFF030000
#define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
-#define ZYNQ_SPI_BASEADDR0 0xE0006000
-#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_SMC_BASEADDR 0xE000E000
#define ZYNQ_NAND_BASEADDR 0xE1000000
int dram_init(void)
{
-#if CONFIG_IS_ENABLED(OF_CONTROL)
int node;
fdt_addr_t addr;
fdt_size_t size;
return -1;
}
gd->ram_size = size;
-#else
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-#endif
zynq_ddrc_init();
return 0;
*/
static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- enum { unknown, EDO, SDRAM, DDR2 } type;
+ enum { unknown, EDO, SDRAM, DDR, DDR2, DDR3, DDR4 } type;
uint chip;
u_char data[128];
type = SDRAM;
puts ("SDRAM\n");
break;
+ case 7:
+ type = DDR;
+ puts("DDR\n");
+ break;
case 8:
type = DDR2;
puts ("DDR2\n");
break;
+ case 11:
+ type = DDR3;
+ puts("DDR3\n");
+ break;
+ case 12:
+ type = DDR4;
+ puts("DDR4\n");
+ break;
default:
type = unknown;
puts ("unknown\n");
CONFIG_CMD_TIMER=y
CONFIG_OF_EMBED=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_ZYNQ_GEM=y
# CONFIG_REGEX is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_ZYNQ_GEM=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_ZYNQ_SDHCI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_ZYNQ_GEM=y
help
Support for Microchip PIC32 SDHCI controller.
+config ZYNQ_SDHCI
+ bool "Arasan SDHCI controller support"
+ depends on DM_MMC && OF_CONTROL
+ help
+ Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform
+
endmenu
return 0;
}
+static int rtl8211e_startup(struct phy_device *phydev)
+{
+ genphy_update_link(phydev);
+ genphy_parse_link(phydev);
+
+ return 0;
+}
+
static int rtl8211f_startup(struct phy_device *phydev)
{
/* Read the Status (2x to make sure link is right) */
.mask = 0xffffff,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211x_config,
- .startup = &rtl8211x_startup,
+ .startup = &rtl8211e_startup,
.shutdown = &genphy_shutdown,
};
* As far as we know it doesn't make sense to support selection of
* these options at run-time, so use the existing CONFIG options.
*/
- serial_out_shift(addr, plat->reg_shift, value);
+ serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value);
}
static int ns16550_readb(NS16550_t port, int offset)
offset *= 1 << plat->reg_shift;
addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
- return serial_in_shift(addr, plat->reg_shift);
+ return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
}
/* We can clean these up once everything is moved to driver model */
return -EINVAL;
plat->base = addr;
+ plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "reg-offset", 0);
plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"reg-shift", 0);
plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
DECLARE_GLOBAL_DATA_PTR;
-#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define ZYNQ_UART_SR_TXEMPTY (1 << 3) /* TX FIFO empty */
#define ZYNQ_UART_SR_TXACTIVE (1 << 11) /* TX active */
#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c)
{
- if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL)
+ if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY))
return -EAGAIN;
writel(c, ®s->tx_rx_fifo);
# define CONFIG_CMD_SF
#endif
-#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
# define CONFIG_SDHCI
-# define CONFIG_ZYNQ_SDHCI
# define CONFIG_CMD_MMC
# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000
# endif
-#endif
-
-#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_FAT_WRITE
# define CONFIG_CMD_EXT4_WRITE
#endif
#ifndef __CONFIG_ZYNQMP_EP_H
#define __CONFIG_ZYNQMP_EP_H
-#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
#define CONFIG_ZYNQ_I2C0
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHY_MARVELL
+# define CONFIG_PHY_REALTEK
# define CONFIG_BOOTP_SERVERIP
# define CONFIG_BOOTP_BOOTPATH
# define CONFIG_BOOTP_GATEWAY
#endif
/* MMC */
-#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+#if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_MMC
# define CONFIG_GENERIC_MMC
# define CONFIG_SDHCI
-# define CONFIG_ZYNQ_SDHCI
# define CONFIG_CMD_MMC
# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
#endif
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
-# if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+# if defined(CONFIG_ZYNQ_SDHCI)
# define CONFIG_DFU_MMC
# define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"usbboot=if usb start; then " \
"echo Copying FIT from USB to RAM... && " \
"load usb 0 ${load_addr} ${fit_image} && " \
- "bootm ${load_addr}\0" \
- "fi\0" \
+ "bootm ${load_addr}; fi\0" \
DFU_ALT_INFO
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
/* Boot FreeBSD/vxWorks from an ELF image */
-#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
-# define CONFIG_SYS_MMC_MAX_DEVICE 1
-#endif
+#define CONFIG_SYS_MMC_MAX_DEVICE 1
#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds"
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-zynq/u-boot-spl.lds"
/* MMC support */
-#ifdef CONFIG_ZYNQ_SDHCI0
+#ifdef CONFIG_ZYNQ_SDHCI
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#ifndef __CONFIG_ZYNQ_MICROZED_H
#define __CONFIG_ZYNQ_MICROZED_H
-#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ZYNQ_SDHCI0
-
#include <configs/zynq-common.h>
#endif /* __CONFIG_ZYNQ_MICROZED_H */
#ifndef __CONFIG_ZYNQ_PICOZED_H
#define __CONFIG_ZYNQ_PICOZED_H
-#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ZYNQ_SDHCI1
#define CONFIG_ZYNQ_USB
-#define CONFIG_ZYNQ_BOOT_FREEBSD
#include <configs/zynq-common.h>
#ifndef __CONFIG_ZYNQ_ZC70X_H
#define __CONFIG_ZYNQ_ZC70X_H
-#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_USB
#define CONFIG_ZYNQ_I2C0
#define CONFIG_ZYNQ_EEPROM
-#define CONFIG_ZYNQ_BOOT_FREEBSD
#include <configs/zynq-common.h>
#ifndef __CONFIG_ZYNQ_ZC770_H
#define __CONFIG_ZYNQ_ZC770_H
-#define CONFIG_SYS_SDRAM_SIZE (1024 * 1024 * 1024)
-
#define CONFIG_SYS_NO_FLASH
-#if defined(CONFIG_ZC770_XM010)
-# define CONFIG_ZYNQ_SDHCI0
-
-#elif defined(CONFIG_ZC770_XM011)
-
-#elif defined(CONFIG_ZC770_XM012)
+#if defined(CONFIG_ZC770_XM012)
# undef CONFIG_SYS_NO_FLASH
-#elif defined(CONFIG_ZC770_XM013)
-
#endif
#include <configs/zynq-common.h>
#ifndef __CONFIG_ZYNQ_ZED_H
#define __CONFIG_ZYNQ_ZED_H
-#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_USB
-#define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_ZYNQ_BOOT_FREEBSD
#include <configs/zynq-common.h>
#ifndef __CONFIG_ZYNQ_ZYBO_H
#define __CONFIG_ZYNQ_ZYBO_H
-#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ZYNQ_USB
-#define CONFIG_ZYNQ_SDHCI0
-#define CONFIG_ZYNQ_BOOT_FREEBSD
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_I2C1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_DISPLAY
+#define CONFIG_I2C_EDID
/* Define ZYBO PS Clock Frequency to 50MHz */
#define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL
*/
struct ns16550_platdata {
unsigned long base;
+ int reg_offset;
int reg_shift;
int clock;
};