Setup AHB master tout in QCA95xx low level init, as it's done for AR933x

diff --git a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S
index cdab8a7bfb9efe567b1900a983383d8b7f1a3aa7..31a66f18f2af5445cfd444359bd52edd44e930cc 100755 (executable)
--- a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S
+++ b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S
@@ -54,12 +54,19 @@ lowlevel_init:
        bgtz t9, set_xtal_40mhz
        nop
 
-       b rtc_reset
+       b ahb_max_timeout
        nop
 
 set_xtal_40mhz:
        li reg_ref_clk_val, 40
 
+/* AHB max master timeout */
+ahb_max_timeout:
+       li t8, QCA_AHB_MASTER_TOUT_MAX_REG
+       lw t9, 0(t8)
+       or t9, t9, 0xFFFFF
+       sw t9, 0(t8)
+
 /*
  * Reset RTC:
  * 1. First reset RTC submodule using RST_RESET register