will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1
+ CFG_SPD_BUS_NUM
+
+ If defined, then this indicates the I2C bus number for DDR SPD.
+ If not defined, then U-Boot assumes that SPD is on I2C bus 0.
+
+ CONFIG_FSL_I2C
+
+ Define this option if you want to use Freescale's I2C driver in
+ drivers/fsl_i2c.c.
+
+
- SPI Support: CONFIG_SPI
Enables SPI driver (so far only tested with
*/
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
-
- if(orig_i2c_bus != 2)
- i2c_set_bus_num(2);
+ i2c_set_bus_num(1);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);
printf("PCI2: 32-bit on PMC3\n");
#endif
/* Reset to original I2C bus */
- if(orig_i2c_bus != 2)
- i2c_set_bus_num(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
}
/**************************************************************************
};
#endif /* CONFIG_PCI */
-/* If MPC8349E-mITX is soldered with SDRAM, then initialize it.
-*/
+/* If MPC8349E-mITX is soldered with SDRAM, then initialize it. */
void sdram_init(void)
{
int checkboard(void)
{
-#ifdef CONFIG_HARD_I2C
- u8 i2c_data;
-#endif
-
- puts("Board: Freescale MPC8349E-mITX");
-
-#ifdef CONFIG_HARD_I2C
- i2c_set_bus_num(2);
- if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) ==
- 0)
- printf(" %u.%u (PCF8475A)", (i2c_data & 0x02) >> 1,
- i2c_data & 0x01);
- else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data))
- == 0)
- printf(" %u.%u (PCF8475)", (i2c_data & 0x02) >> 1,
- i2c_data & 0x01);
- else
- printf(" ?.?");
-#endif
-
- puts("\n");
+ puts("Board: Freescale MPC8349E-mITX\n");
return 0;
}
-/**
+/*
* Implement a work-around for a hardware problem with compact
* flash.
*
return 0;
}
-/**
+/*
* Make sure the EEPROM has the HRCW correctly programmed.
* Make sure the RTC is correctly programmed.
*
#ifdef CONFIG_HARD_I2C
- uchar orig_bus = i2c_get_bus_num();;
+ unsigned int orig_bus = i2c_get_bus_num();;
+ u8 i2c_data;
#ifdef CFG_I2C_RTC_ADDR
char ds1339_data[17];
};
u8 data[sizeof(eeprom_data)];
+#endif
+ printf("Board revision: ");
i2c_set_bus_num(1);
+ if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+ else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+ printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
+ else {
+ printf("Unknown\n");
+ rc = 1;
+ }
+
+#ifdef CFG_I2C_EEPROM_ADDR
+ i2c_set_bus_num(0);
if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
#endif
#ifdef CFG_I2C_RTC_ADDR
- i2c_set_bus_num(2);
+ i2c_set_bus_num(1);
if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
== 0) {
#include <pci.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
udelay(2000);
#ifdef CONFIG_HARD_I2C
- i2c_set_bus_num(2);
+ i2c_set_bus_num(1);
/* Read the PCI_M66EN jumper setting */
if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
(i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
#include <pci.h>
#include <i2c.h>
-#include <asm/i2c.h>
+#include <asm/fsl_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
-
- if(orig_i2c_bus != 2)
- i2c_set_bus_num(2);
+ i2c_set_bus_num(1);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);
asm("eieio");
/* Reset to original I2C bus */
- if(orig_i2c_bus != 2)
- i2c_set_bus_num(orig_i2c_bus);
-
- /* Reset to original I2C bus */
- if(orig_i2c_bus != 2)
- i2c_set_bus_num(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
/*
* Release PCI RST Output signal
START = start.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- i2c.o spd_sdram.o qe_io.o
+ spd_sdram.o qe_io.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
}
-/**
+/*
* Program a UPM with the code supplied in the table.
*
* The 'dummy' variable is used to increment the MAD. 'dummy' is
* upm: 0=UPMA, 1=UPMB, 2=UPMC
* table: Pointer to an array of values to program
* size: Number of elements in the array. Must be 64 or less.
-*/
+ */
void upmconfig (uint upm, uint *table, uint size)
{
#if defined(CONFIG_MPC834X)
+++ /dev/null
-/*
- * (C) Copyright 2006 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao <x.xiao@motorola.com>
- * Adapted for Motorola 85xx chip.
- *
- * (C) Copyright 2003
- * Gleb Natapov <gnatapov@mrv.com>
- * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
- *
- * Hardware I2C driver for MPC107 PCI bridge.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Change log:
- *
- * 20050101: Eran Liberty (liberty@freescale.com)
- * Initial file creating (porting from 85XX & 8260)
- * 20060601: Dave Liu (daveliu@freescale.com)
- * Unified variable names for mpc83xx
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_HARD_I2C
-#include <i2c.h>
-#include <asm/i2c.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
- * Default is bus 1. This is necessary because the DDR initialization
- * runs from ROM, and we can't switch buses because we can't modify
- * the i2c_dev variable. Everything gets straightened out once i2c_init
- * is called from RAM. */
-
-#ifndef CFG_SPD_BUS_NUM
-#define CFG_SPD_BUS_NUM 1
-#endif
-
-static unsigned int i2c_bus_num = CFG_SPD_BUS_NUM;
-
-#if CFG_SPD_BUS_NUM == 1
-static volatile i2c_t *i2c_dev = I2C_1;
-#else
-static volatile i2c_t *i2c_dev = I2C_2;
-#endif
-
-static int i2c_bus_speed[2] = {0, 0};
-
-/*
- * Map the frequency divider to the FDR. This data is taken from table 17-5
- * of the MPC8349EA reference manual, with duplicates removed.
- */
-static struct {
- unsigned int divider;
- u8 fdr;
-} i2c_speed_map[] =
-{
- {0, 0x20},
- {256, 0x20},
- {288, 0x21},
- {320, 0x22},
- {352, 0x23},
- {384, 0x24},
- {416, 0x01},
- {448, 0x25},
- {480, 0x02},
- {512, 0x26},
- {576, 0x27},
- {640, 0x28},
- {704, 0x05},
- {768, 0x29},
- {832, 0x06},
- {896, 0x2A},
- {1024, 0x2B},
- {1152, 0x08},
- {1280, 0x2C},
- {1536, 0x2D},
- {1792, 0x2E},
- {1920, 0x0B},
- {2048, 0x2F},
- {2304, 0x0C},
- {2560, 0x30},
- {3072, 0x31},
- {3584, 0x32},
- {3840, 0x0F},
- {4096, 0x33},
- {4608, 0x10},
- {5120, 0x34},
- {6144, 0x35},
- {7168, 0x36},
- {7680, 0x13},
- {8192, 0x37},
- {9216, 0x14},
- {10240, 0x38},
- {12288, 0x39},
- {14336, 0x3A},
- {15360, 0x17},
- {16384, 0x3B},
- {18432, 0x18},
- {20480, 0x3C},
- {24576, 0x3D},
- {28672, 0x3E},
- {30720, 0x1B},
- {32768, 0x3F},
- {36864, 0x1C},
- {40960, 0x1D},
- {49152, 0x1E},
- {61440, 0x1F},
- {-1, 0x1F}
-};
-
-#define NUM_I2C_SPEEDS (sizeof(i2c_speed_map) / sizeof(i2c_speed_map[0]))
-
-static int set_speed(unsigned int speed)
-{
- unsigned long i2c_clk;
- unsigned int divider, i;
- u8 fdr = 0x3F;
-
- i2c_clk = (i2c_bus_num == 2) ? gd->i2c2_clk : gd->i2c1_clk;
-
- divider = i2c_clk / speed;
-
- /* Scan i2c_speed_map[] for the closest matching divider.*/
-
- for (i = 0; i < NUM_I2C_SPEEDS-1; i++) {
- /* Locate our divider in between two entries in i2c_speed_map[] */
- if ((divider >= i2c_speed_map[i].divider) &&
- (divider <= i2c_speed_map[i+1].divider)) {
- /* Which one is closer? */
- if ((divider - i2c_speed_map[i].divider) < (i2c_speed_map[i+1].divider - divider)) {
- fdr = i2c_speed_map[i].fdr;
- } else {
- fdr = i2c_speed_map[i+1].fdr;
- }
- break;
- }
- }
-
- writeb(fdr, &i2c_dev->fdr);
- i2c_bus_speed[i2c_bus_num - 1] = speed;
-
- return 0;
-}
-
-
-static void _i2c_init(int speed, int slaveadd)
-{
- /* stop I2C controller */
- writeb(0x00 , &i2c_dev->cr);
-
- /* set clock */
- set_speed(speed);
-
- /* set default filter */
- writeb(IC2_FDR,&i2c_dev->dfsrr);
-
- /* write slave address */
- writeb(slaveadd, &i2c_dev->adr);
-
- /* clear status register */
- writeb(I2C_CR_MTX, &i2c_dev->sr);
-
- /* start I2C controller */
- writeb(I2C_CR_MEN, &i2c_dev->cr);
-}
-
-void i2c_init(int speed, int slaveadd)
-{
- /* Set both interfaces to the same speed and slave address */
- /* Note: This function gets called twice - before and after
- * relocation to RAM. The first time it's called, we are unable
- * to change buses, so whichever one 'i2c_dev' was initialized to
- * gets set twice. When run from RAM both buses get set properly */
-
- i2c_set_bus_num(1);
- _i2c_init(speed, slaveadd);
-#ifdef CFG_I2C2_OFFSET
- i2c_set_bus_num(2);
- _i2c_init(speed, slaveadd);
- i2c_set_bus_num(1);
-#endif /* CFG_I2C2_OFFSET */
-}
-
-static __inline__ int
-i2c_wait4bus (void)
-{
- ulong timeval = get_timer (0);
- while (readb(&i2c_dev->sr) & I2C_SR_MBB) {
- if (get_timer (timeval) > I2C_TIMEOUT) {
- return -1;
- }
- }
- return 0;
-}
-
-static __inline__ int
-i2c_wait (int write)
-{
- u32 csr;
- ulong timeval = get_timer(0);
- do {
- csr = readb(&i2c_dev->sr);
-
- if (!(csr & I2C_SR_MIF))
- continue;
-
- writeb(0x0, &i2c_dev->sr);
-
- if (csr & I2C_SR_MAL) {
- debug("i2c_wait: MAL\n");
- return -1;
- }
-
- if (!(csr & I2C_SR_MCF)) {
- debug("i2c_wait: unfinished\n");
- return -1;
- }
-
- if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
- debug("i2c_wait: No RXACK\n");
- return -1;
- }
-
- return 0;
- } while (get_timer (timeval) < I2C_TIMEOUT);
-
- debug("i2c_wait: timed out\n");
- return -1;
-}
-
-static __inline__ int
-i2c_write_addr (u8 dev, u8 dir, int rsta)
-{
- writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
- (rsta?I2C_CR_RSTA:0),
- &i2c_dev->cr);
-
- writeb((dev << 1) | dir, &i2c_dev->dr);
-
- if (i2c_wait (I2C_WRITE) < 0)
- return 0;
- return 1;
-}
-
-static __inline__ int
-__i2c_write (u8 *data, int length)
-{
- int i;
-
- writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
- &i2c_dev->cr);
-
- for (i=0; i < length; i++) {
- writeb(data[i], &i2c_dev->dr);
-
- if (i2c_wait (I2C_WRITE) < 0)
- break;
- }
- return i;
-}
-
-static __inline__ int
-__i2c_read (u8 *data, int length)
-{
- int i;
-
- writeb(I2C_CR_MEN | I2C_CR_MSTA |
- ((length == 1) ? I2C_CR_TXAK : 0),
- &i2c_dev->cr);
-
- /* dummy read */
- readb(&i2c_dev->dr);
-
- for (i=0; i < length; i++) {
- if (i2c_wait (I2C_READ) < 0)
- break;
-
- /* Generate ack on last next to last byte */
- if (i == length - 2)
- writeb(I2C_CR_MEN | I2C_CR_MSTA |
- I2C_CR_TXAK,
- &i2c_dev->cr);
-
- /* Generate stop on last byte */
- if (i == length - 1)
- writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev->cr);
-
- data[i] = readb(&i2c_dev->dr);
- }
- return i;
-}
-
-int
-i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
-{
- int i = 0;
- u8 *a = (u8*)&addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_READ, 1) == 0)
- goto exit;
-
- i = __i2c_read (data, length);
-
- exit:
- writeb(I2C_CR_MEN, &i2c_dev->cr);
- return !(i == length);
-}
-
-int
-i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
-{
- int i = 0;
- u8 *a = (u8*)&addr;
-
- if (i2c_wait4bus () < 0)
- goto exit;
-
- if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
- goto exit;
-
- if (__i2c_write (&a[4 - alen], alen) != alen)
- goto exit;
-
- i = __i2c_write (data, length);
-
- exit:
- writeb(I2C_CR_MEN, &i2c_dev->cr);
- return !(i == length);
-}
-
-int i2c_probe (uchar chip)
-{
- int tmp;
-
- /*
- * Try to read the first location of the chip. The underlying
- * driver doesn't appear to support sending just the chip address
- * and looking for an <ACK> back.
- */
- udelay(10000);
- return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
-}
-
-uchar i2c_reg_read (uchar i2c_addr, uchar reg)
-{
- uchar buf[1];
-
- i2c_read (i2c_addr, reg, 1, buf, 1);
-
- return (buf[0]);
-}
-
-void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
-{
- i2c_write (i2c_addr, reg, 1, &val, 1);
-}
-
-int i2c_set_bus_num(unsigned int bus)
-{
- if(bus == 1)
- {
- i2c_dev = I2C_1;
- }
-#ifdef CFG_I2C2_OFFSET
- else if(bus == 2)
- {
- i2c_dev = I2C_2;
- }
-#endif
- else
- {
- return -1;
- }
- i2c_bus_num = bus;
- return 0;
-}
-
-int i2c_set_bus_speed(unsigned int speed)
-{
- return set_speed(speed);
-}
-
-unsigned int i2c_get_bus_num(void)
-{
- return i2c_bus_num;
-}
-
-unsigned int i2c_get_bus_speed(void)
-{
- return i2c_bus_speed[i2c_bus_num - 1];
-}
-#endif /* CONFIG_HARD_I2C */
#include <asm/fsl_i2c.h> /* HW definitions */
#define I2C_TIMEOUT (CFG_HZ / 4)
-#define I2C ((struct fsl_i2c *)(CFG_IMMR + CFG_I2C_OFFSET))
+/* Initialize the bus pointer to whatever one the SPD EEPROM is on.
+ * Default is bus 0. This is necessary because the DDR initialization
+ * runs from ROM, and we can't switch buses because we can't modify
+ * the global variables.
+ */
+#ifdef CFG_SPD_BUS_NUM
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
+#else
+static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
+#endif
+
+static volatile struct fsl_i2c *i2c_dev[2] = {
+ (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
+#ifdef CFG_I2C2_OFFSET
+ (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
+#endif
+};
void
i2c_init(int speed, int slaveadd)
{
- /* stop I2C controller */
- writeb(0x0, &I2C->cr);
-
- /* set clock */
- writeb(0x3f, &I2C->fdr);
-
- /* set default filter */
- writeb(0x10, &I2C->dfsrr);
-
- /* write slave address */
- writeb(slaveadd, &I2C->adr);
-
- /* clear status register */
- writeb(0x0, &I2C->sr);
-
- /* start I2C controller */
- writeb(I2C_CR_MEN, &I2C->cr);
+ volatile struct fsl_i2c *dev;
+
+ dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
+
+ writeb(0, &dev->cr); /* stop I2C controller */
+ writeb(0x3F, &dev->fdr); /* set bus speed */
+ writeb(0x3F, &dev->dfsrr); /* set default filter */
+ writeb(slaveadd, &dev->adr); /* write slave address */
+ writeb(0x0, &dev->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+
+#ifdef CFG_I2C2_OFFSET
+ dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
+
+ writeb(0, &dev->cr); /* stop I2C controller */
+ writeb(0x3F, &dev->fdr); /* set bus speed */
+ writeb(0x3F, &dev->dfsrr); /* set default filter */
+ writeb(slaveadd, &dev->adr); /* write slave address */
+ writeb(0x0, &dev->sr); /* clear status register */
+ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
+#endif /* CFG_I2C2_OFFSET */
}
static __inline__ int
{
ulong timeval = get_timer(0);
- while (readb(&I2C->sr) & I2C_SR_MBB) {
+ while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
if (get_timer(timeval) > I2C_TIMEOUT) {
return -1;
}
ulong timeval = get_timer(0);
do {
- csr = readb(&I2C->sr);
+ csr = readb(&i2c_dev[i2c_bus_num]->sr);
if (!(csr & I2C_SR_MIF))
continue;
- writeb(0x0, &I2C->sr);
+ writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
if (csr & I2C_SR_MAL) {
debug("i2c_wait: MAL\n");
{
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
| (rsta ? I2C_CR_RSTA : 0),
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
- writeb((dev << 1) | dir, &I2C->dr);
+ writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
if (i2c_wait(I2C_WRITE) < 0)
return 0;
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
for (i = 0; i < length; i++) {
- writeb(data[i], &I2C->dr);
+ writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
if (i2c_wait(I2C_WRITE) < 0)
break;
int i;
writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
/* dummy read */
- readb(&I2C->dr);
+ readb(&i2c_dev[i2c_bus_num]->dr);
for (i = 0; i < length; i++) {
if (i2c_wait(I2C_READ) < 0)
/* Generate ack on last next to last byte */
if (i == length - 2)
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
- &I2C->cr);
+ &i2c_dev[i2c_bus_num]->cr);
/* Generate stop on last byte */
if (i == length - 1)
- writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr);
+ writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
- data[i] = readb(&I2C->dr);
+ data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
}
return i;
i = __i2c_read(data, length);
}
- writeb(I2C_CR_MEN, &I2C->cr);
+ writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
if (i == length)
return 0;
i = __i2c_write(data, length);
}
- writeb(I2C_CR_MEN, &I2C->cr);
+ writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
if (i == length)
return 0;
i2c_write(i2c_addr, reg, 1, &val, 1);
}
+int i2c_set_bus_num(unsigned int bus)
+{
+#ifdef CFG_I2C2_OFFSET
+ if (bus > 1) {
+#else
+ if (bus > 0) {
+#endif
+ return -1;
+ }
+
+ i2c_bus_num = bus;
+
+ return 0;
+}
+
+int i2c_set_bus_speed(unsigned int speed)
+{
+ return -1;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+ return i2c_bus_num;
+}
+
+unsigned int i2c_get_bus_speed(void)
+{
+ return 0;
+}
#endif /* CONFIG_HARD_I2C */
#endif /* CONFIG_FSL_I2C */
+++ /dev/null
-/*
- * Freescale I2C Controller
- *
- * This software may be used and distributed according to the
- * terms of the GNU Public License, Version 2, incorporated
- * herein by reference.
- *
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2003, Motorola, Inc.
- * author: Eran Liberty (liberty@freescale.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_I2C_H_
-#define _ASM_I2C_H_
-
-#include <asm/types.h>
-
-typedef struct i2c
-{
- u8 adr; /**< I2C slave address */
-#define I2C_ADR 0xFE
-#define I2C_ADR_SHIFT 1
-#define I2C_ADR_RES ~(I2C_ADR)
- u8 res0[3];
- u8 fdr; /**< I2C frequency divider register */
-#define IC2_FDR 0x3F
-#define IC2_FDR_SHIFT 0
-#define IC2_FDR_RES ~(IC2_FDR)
- u8 res1[3];
- u8 cr; /**< I2C control redister */
-#define I2C_CR_MEN 0x80
-#define I2C_CR_MIEN 0x40
-#define I2C_CR_MSTA 0x20
-#define I2C_CR_MTX 0x10
-#define I2C_CR_TXAK 0x08
-#define I2C_CR_RSTA 0x04
-#define I2C_CR_BCST 0x01
- u8 res2[3];
- u8 sr; /**< I2C status register */
-#define I2C_SR_MCF 0x80
-#define I2C_SR_MAAS 0x40
-#define I2C_SR_MBB 0x20
-#define I2C_SR_MAL 0x10
-#define I2C_SR_BCSTM 0x08
-#define I2C_SR_SRW 0x04
-#define I2C_SR_MIF 0x02
-#define I2C_SR_RXAK 0x01
- u8 res3[3];
- u8 dr; /**< I2C data register */
-#define I2C_DR 0xFF
-#define I2C_DR_SHIFT 0
-#define I2C_DR_RES ~(I2C_DR)
- u8 res4[3];
- u8 dfsrr; /**< I2C digital filter sampling rate register */
-#define I2C_DFSRR 0x3F
-#define I2C_DFSRR_SHIFT 0
-#define I2C_DFSRR_RES ~(I2C_DR)
- u8 res5[3];
- u8 res6[0xE8];
-} i2c_t;
-
-#ifndef CFG_HZ
-#error CFG_HZ is not defined in /include/configs/${BOARD}.h
-#endif
-#define I2C_TIMEOUT (CFG_HZ/4)
-
-#ifndef CFG_IMMR
-#error CFG_IMMR is not defined in /include/configs/${BOARD}.h
-#endif
-
-#ifndef CFG_I2C_OFFSET
-#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h
-#endif
-
-#define I2C_1 ((i2c_t*)(CFG_IMMR + CFG_I2C_OFFSET))
-
-/* Optional support for second I2C bus */
-#ifdef CFG_I2C2_OFFSET
-#define I2C_2 ((i2c_t*)(CFG_IMMR + CFG_I2C2_OFFSET))
-#endif /* CFG_I2C2_OFFSET */
-
-#define I2C_READ 1
-#define I2C_WRITE 0
-
-#endif /* _ASM_I2C_H_ */
#include <config.h>
#include <asm/types.h>
-#include <asm/i2c.h>
+#include <asm/fsl_i2c.h>
/*
* Local Access Window.
qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
#endif
ddr83xx_t ddr; /* DDR Memory Controller Memory */
- i2c_t i2c[2]; /* I2C1 Controller */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
#if defined (CONFIG_MPC8349)
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
Align. Board
Bus Addr Part No. Description Length Location
----------------------------------------------------------------
- I2C1 0x50 M24256-BWMN6P Board EEPROM 2 U64
+ I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
- I2C2 0x20 PCF8574 I2C Expander 0 U8
- I2C2 0x21 PCF8574 I2C Expander 0 U10
- I2C2 0x38 PCF8574A I2C Expander 0 U8
- I2C2 0x39 PCF8574A I2C Expander 0 U10
- I2C2 0x51 (DDR) DDR EEPROM 1 U1
- I2C2 0x68 DS1339 RTC 1 U68
+ I2C1 0x20 PCF8574 I2C Expander 0 U8
+ I2C1 0x21 PCF8574 I2C Expander 0 U10
+ I2C1 0x38 PCF8574A I2C Expander 0 U8
+ I2C1 0x39 PCF8574A I2C Expander 0 U10
+ I2C1 0x51 (DDR) DDR EEPROM 1 U1
+ I2C1 0x68 DS1339 RTC 1 U68
Note that a given board has *either* a pair of 8574s or a pair of 8574As.
*/
#define CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
+#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
-#define CFG_SPD_BUS_NUM 2
+#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */
-#define CFG_I2C_8574_ADDR1 0x20 /* I2C2, PCF8574 */
-#define CFG_I2C_8574_ADDR2 0x21 /* I2C2, PCF8574 */
-#define CFG_I2C_8574A_ADDR1 0x38 /* I2C2, PCF8574A */
-#define CFG_I2C_8574A_ADDR2 0x39 /* I2C2, PCF8574A */
-#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C1, Board EEPROM */
-#define CFG_I2C_RTC_ADDR 0x68 /* I2C2, DS1339 RTC*/
-#define SPD_EEPROM_ADDRESS 0x51 /* I2C2, DDR */
+#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
+#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
+#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
+#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
+#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
+#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
+#define CFG_FLASH_EMPTY_INFO
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
-#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C1 clock mode (0-3) */
+#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */
/* System IO Config */
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif
+#if 1
+#define CONFIG_IPADDR 10.82.19.159
+#define CONFIG_SERVERIP 10.82.48.106
+#define CONFIG_GATEWAYIP 10.82.19.254
+#define CONFIG_NETMASK 255.255.252.0
+#define CONFIG_NETDEV eth0
+
+#define CONFIG_HOSTNAME mpc8349emitx
+#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs
+#define CONFIG_BOOTFILE timur/uImage
+
+#define CONFIG_UBOOTPATH timur/u-boot.bin
+#else
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_BOOTFILE uImage
#define CONFIG_UBOOTPATH u-boot.bin
+#endif
+
#define CONFIG_UBOOTSTART fe700000
#define CONFIG_UBOOTEND fe77ffff
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CFG_I2C_SPEED 0x3F /* I2C speed and slave address */
+#define CONFIG_FSL_I2C
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
*/
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_FSL_I2C
#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
#define CFG_I2C_SLAVE 0x7F /* slave address */
#define CFG_I2C_OFFSET 0x3000
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