" Request Sense returned %02X %02X %02X\n",
pccb->sense_buf[2], pccb->sense_buf[12],
pccb->sense_buf[13]);
- if (dev_desc->removable == 1) {
+ if (dev_desc->removable == 1)
dev_desc->type = perq;
- return 1;
- }
return 0;
}
pccb->pdata = (unsigned char *)cap;
if (!evt->buf)
return ERR_PTR(-ENOMEM);
+ dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
+
return evt;
}
trb->ctrl |= (DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_LST);
- dwc3_flush_cache((long)buf_dma, len);
- dwc3_flush_cache((long)trb, sizeof(*trb));
+ dwc3_flush_cache((uintptr_t)buf_dma, len);
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
if (chain)
return 0;
if (!r)
return;
- dwc3_flush_cache((long)trb, sizeof(*trb));
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING) {
ur->actual += transferred;
trb++;
- dwc3_flush_cache((long)trb, sizeof(*trb));
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
length = trb->size & DWC3_TRB_SIZE_MASK;
ep0->free_slot = 0;
maxp);
transferred = min_t(u32, ur->length - transferred,
transfer_size - length);
- dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
+ dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
memcpy(buf, dwc->ep0_bounce, transferred);
} else {
transferred = ur->length - length;
list_del(&req->list);
req->trb = NULL;
- dwc3_flush_cache((long)req->request.dma, req->request.length);
+ dwc3_flush_cache((uintptr_t)req->request.dma, req->request.length);
if (req->request.status == -EINPROGRESS)
req->request.status = status;
trb->ctrl |= DWC3_TRB_CTRL_HWO;
- dwc3_flush_cache((long)dma, length);
- dwc3_flush_cache((long)trb, sizeof(*trb));
+ dwc3_flush_cache((uintptr_t)dma, length);
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
}
/*
slot %= DWC3_TRB_NUM;
trb = &dep->trb_pool[slot];
- dwc3_flush_cache((long)trb, sizeof(*trb));
+ dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
__dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
dwc3_gadget_giveback(dep, req, status);
int i;
struct dwc3_event_buffer *evt;
+ dwc3_thread_interrupt(0, dwc);
+
+ /* Clean + Invalidate the buffers after touching them */
for (i = 0; i < dwc->num_event_buffers; i++) {
evt = dwc->ev_buffs[i];
- dwc3_flush_cache((long)evt->buf, evt->length);
+ dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
}
-
- dwc3_thread_interrupt(0, dwc);
}
}
writel(value, base + offs);
}
-static inline void dwc3_flush_cache(int addr, int length)
+static inline void dwc3_flush_cache(uintptr_t addr, int length)
{
flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
}
#define STRING_USBDOWN 2
/* Index of String serial */
#define STRING_SERIAL 3
-#define MAX_STRING_SERIAL 32
+#define MAX_STRING_SERIAL 256
/* Number of supported configurations */
#define CONFIGURATION_NUMBER 1
.idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM),
.idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM),
- .iProduct = STRING_PRODUCT,
- .iSerialNumber = STRING_SERIAL,
+ /* .iProduct = DYNAMIC */
+ /* .iSerialNumber = DYNAMIC */
.bNumConfigurations = 1,
};
g_dnl_string_defs[1].id = id;
device_desc.iProduct = id;
- id = usb_string_id(cdev);
- if (id < 0)
- return id;
+ if (strlen(g_dnl_serial)) {
+ id = usb_string_id(cdev);
+ if (id < 0)
+ return id;
- g_dnl_string_defs[2].id = id;
- device_desc.iSerialNumber = id;
+ g_dnl_string_defs[2].id = id;
+ device_desc.iSerialNumber = id;
+ }
g_dnl_bind_fixup(&device_desc, cdev->driver->name);
ret = g_dnl_config_register(cdev);
#include <usbroothubdes.h>
#include <wait_bit.h>
#include <asm/io.h>
+#include <power/regulator.h>
#include "dwc2.h"
mdelay(100);
}
+#if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
+static int dwc_vbus_supply_init(struct udevice *dev)
+{
+ struct udevice *vbus_supply;
+ int ret;
+
+ ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
+ if (ret) {
+ debug("%s: No vbus supply\n", dev->name);
+ return 0;
+ }
+
+ ret = regulator_set_enable(vbus_supply, true);
+ if (ret) {
+ error("Error enabling vbus supply\n");
+ return ret;
+ }
+
+ return 0;
+}
+#else
+static int dwc_vbus_supply_init(struct udevice *dev)
+{
+ return 0;
+}
+#endif
+
/*
* This function initializes the DWC_otg controller registers for
* host mode.
* request queues. Host channels are reset to ensure that they are ready for
* performing transfers.
*
+ * @param dev USB Device (NULL if driver model is not being used)
* @param regs Programming view of DWC_otg controller
*
*/
-static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
+static void dwc_otg_core_host_init(struct udevice *dev,
+ struct dwc2_core_regs *regs)
{
uint32_t nptxfifosize = 0;
uint32_t ptxfifosize = 0;
writel(hprt0, ®s->hprt0);
}
}
+
+ if (dev)
+ dwc_vbus_supply_init(dev);
}
/*
(*pid << DWC2_HCTSIZ_PID_OFFSET),
&hc_regs->hctsiz);
- if (!in && xfer_len) {
- memcpy(aligned_buffer, buffer, xfer_len);
-
- flush_dcache_range((unsigned long)aligned_buffer,
- (unsigned long)aligned_buffer +
- roundup(xfer_len, ARCH_DMA_MINALIGN));
+ if (xfer_len) {
+ if (in) {
+ invalidate_dcache_range(
+ (uintptr_t)aligned_buffer,
+ (uintptr_t)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN));
+ } else {
+ memcpy(aligned_buffer, buffer, xfer_len);
+ flush_dcache_range(
+ (uintptr_t)aligned_buffer,
+ (uintptr_t)aligned_buffer +
+ roundup(xfer_len, ARCH_DMA_MINALIGN));
+ }
}
writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
}
}
-static int dwc2_init_common(struct dwc2_priv *priv)
+static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
{
struct dwc2_core_regs *regs = priv->regs;
uint32_t snpsid;
#endif
dwc_otg_core_init(priv);
- dwc_otg_core_host_init(regs);
+ dwc_otg_core_host_init(dev, regs);
clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
if (board_usb_init(index, USB_INIT_HOST))
return -1;
- return dwc2_init_common(priv);
+ return dwc2_init_common(NULL, priv);
}
int usb_lowlevel_stop(int index)
bus_priv->desc_before_addr = true;
- return dwc2_init_common(priv);
+ return dwc2_init_common(dev, priv);
}
static int dwc2_usb_remove(struct udevice *dev)