fsl-ddr: add the override for write leveling

add the override for write leveling sampling and
start time according to specific board.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index a92f1a330bd525288dec210cf067d836962bfc17..5e37ca6b80643f79ba863192d712b2bfa00aaa40 100644 (file)
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1002,8 +1002,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
 }
 
 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
-static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
-                              unsigned int wrlvl_en)
+static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
+                               const memctl_options_t *popts)
 {
        /*
         * First DQS pulse rising edge after margining mode
@@ -1030,8 +1030,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
                /* tWL_DQSEN min = 25 nCK, we set it 32 */
                wrlvl_dqsen = 0x5;
                /*
-                * Write leveling sample time at least need 14 clocks
-                * due to tWLO = 9, we set it 15 clocks
+                * Write leveling sample time at least need 6 clocks
+                * higher than tWLO to allow enough time for progagation
+                * delay and sampling the prime data bits.
                 */
                wrlvl_smpl = 0xf;
                /*
@@ -1044,9 +1045,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
                 * Write leveling start time
                 * The value use for the DQS_ADJUST for the first sample
                 * when write leveling is enabled.
-                * we set it 1 clock delay
                 */
                wrlvl_start = 0x8;
+               /*
+                * Override the write leveling sample and start time
+                * according to specific board
+                */
+               if (popts->wrlvl_override) {
+                       wrlvl_smpl = popts->wrlvl_sample;
+                       wrlvl_start = popts->wrlvl_start;
+               }
        }
 
        ddr->ddr_wrlvl_cntl = (0
@@ -1332,7 +1340,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        set_timing_cfg_5(ddr);
 
        set_ddr_zq_cntl(ddr, zq_en);
-       set_ddr_wrlvl_cntl(ddr, wrlvl_en);
+       set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
 
        set_ddr_sr_cntr(ddr, sr_it);
 

diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 2e030c11a3b8e18ce277ee723a3225df28349598..3dcd33ddf20d80b12d1abad1b4847f4f4841155a 100644 (file)
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
         * meet the tQDSS under different loading.
         */
        popts->wrlvl_en = 1;
+       popts->wrlvl_override = 0;
 #endif
 
        /*

diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 69b857b41cd1eb31f65e9b133d50a250927848f8..15ab675dc92279816d84c638e202ab8c572c72e7 100644 (file)
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -177,6 +177,11 @@ typedef struct memctl_options_s {
        unsigned int clk_adjust;                /* */
        unsigned int cpo_override;
        unsigned int write_data_delay;          /* DQS adjust */
+
+       unsigned int wrlvl_override;
+       unsigned int wrlvl_sample;              /* Write leveling */
+       unsigned int wrlvl_start;
+
        unsigned int half_strength_driver_enable;
        unsigned int twoT_en;
        unsigned int threeT_en;