Fix wrong DPLL2 in SRIF area register definitions for QCA953x

As usual... you should not trust QC/A datasheets!
They are so buggy and contain lot of copy&paste mistakes.

DPLL2 register in SRIF for QCA953x seems to be totally different
than in other QCA95xx WiSOCs. Happily, definitions in original code
from SDK seem to be correct, so we will use it instead.

Clock settings based on setting default and SRIF PLL was confirmed on scope.

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index 44f6021f2091bf6adc306908173f294806b2fc7f..6d98694579f48686a1838d88ca02a2d4ab6c6a89 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -983,18 +983,43 @@
 #define QCA_PLL_SRIF_DPLL1_REFDIV_MASK                 BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5)
 
 /* DPLL2 (common for CPU, AUD, DDR and PCIE) */
-#define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT                        13
-#define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK                 BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
-#define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT                        16
-#define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK                 (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
-#define QCA_PLL_SRIF_DPLL2_KD_SHIFT                            19
-#define QCA_PLL_SRIF_DPLL2_KD_MASK                             BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
-#define QCA_PLL_SRIF_DPLL2_KI_SHIFT                            26
-#define QCA_PLL_SRIF_DPLL2_KI_MASK                             BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
-#define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT             30
-#define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK              (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
-#define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT                 31
-#define QCA_PLL_SRIF_DPLL2_RANGE_MASK                  (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
+#if (SOC_TYPE & QCA_QCA953X_SOC)
+       #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT               0
+       #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK                (1 << QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT                1
+       #define QCA_PLL_SRIF_DPLL2_SEL_CNT_MASK                 (1 << QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT                2
+       #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK                 BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 10)
+       #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT    12
+       #define QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_MASK             BITS(QCA_PLL_SRIF_DPLL2_PHASE_SHIFT_SHIFT, 7)
+       #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT                 19
+       #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK                  BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 3)
+       #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT                 22
+       #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK                  (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT               23
+       #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK                (1 << QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT             24
+       #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK              (1 << QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_KD_SHIFT                             25
+       #define QCA_PLL_SRIF_DPLL2_KD_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4)
+       #define QCA_PLL_SRIF_DPLL2_KI_SHIFT                             29
+       #define QCA_PLL_SRIF_DPLL2_KI_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 2)
+       #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT              31
+       #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK               (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
+#else
+       #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT                 13
+       #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK                  BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2)
+       #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT                 16
+       #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK                  (1 << QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_KD_SHIFT                             19
+       #define QCA_PLL_SRIF_DPLL2_KD_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7)
+       #define QCA_PLL_SRIF_DPLL2_KI_SHIFT                             26
+       #define QCA_PLL_SRIF_DPLL2_KI_MASK                              BITS(QCA_PLL_SRIF_DPLL2_KI_SHIFT, 4)
+       #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT              30
+       #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK               (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT)
+       #define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT                  31
+       #define QCA_PLL_SRIF_DPLL2_RANGE_MASK                   (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT)
+#endif
 
 /* DPLL3 (common for CPU, AUD, DDR and PCIE) */
 #define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT   23