rockchip: rk3288: sdram: use constants in ddrconf table
authorHeiko Stübner <heiko@sntech.de>
Sat, 18 Feb 2017 18:46:23 +0000 (19:46 +0100)
committerSimon Glass <sjg@chromium.org>
Thu, 16 Mar 2017 22:03:44 +0000 (16:03 -0600)
Use defines to describe the bit shifts used to create the
table for ddrconf register values.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c

index fccabcd2c03e30baf38ce2292ad5a43d883e52f8..9a59075afcf7896a39c4361015dcb2015d264560 100644 (file)
@@ -425,6 +425,14 @@ enum {
 
 #define START_CMD                      (1u << 31)
 
+/*
+ * DDRCONF
+ * [5:4] row(13+n)
+ * [1:0] col(9+n), assume bw=2
+ */
+#define DDRCONF_ROW_SHIFT              4
+#define DDRCONF_COL_SHIFT              0
+
 /* DEVTODEV */
 #define BUSWRTORD_SHIFT                        4
 #define BUSRDTOWR_SHIFT                        2
index 89fd8e6bff1114a80727e44102dccf62358b9124..868b96d51a20af1bdd024986b908fa5095119315 100644 (file)
@@ -596,16 +596,16 @@ static void dram_all_config(const struct dram_info *dram,
 const int ddrconf_table[] = {
        /* row      col,bw */
        0,
-       ((1 << 4) | 1),
-       ((2 << 4) | 1),
-       ((3 << 4) | 1),
-       ((4 << 4) | 1),
-       ((1 << 4) | 2),
-       ((2 << 4) | 2),
-       ((3 << 4) | 2),
-       ((1 << 4) | 0),
-       ((2 << 4) | 0),
-       ((3 << 4) | 0),
+       ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+       ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+       ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+       ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+       ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+       ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+       ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+       ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+       ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+       ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
        0,
        0,
        0,