ARM64: zynqmp: List all SMMU ids
authorMichal Simek <michal.simek@xilinx.com>
Wed, 6 Apr 2016 08:43:23 +0000 (10:43 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 15 Nov 2016 14:30:40 +0000 (15:30 +0100)
Add SMMU description for all tested IPs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/dts/zynqmp.dtsi

index 2b84bfbd6369198820c66db50786bf0ac78335ea..618378fa3d59aede9afc1272686793dbf057a14b 100644 (file)
                        interrupts = <0 124 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14e8>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 125 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14e9>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 126 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14ea>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 127 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14eb>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 128 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14ec>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 129 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14ed>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 130 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14ee>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupts = <0 131 4>;
                        clock-names = "clk_main", "clk_apb";
                        xlnx,bus-width = <128>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x14ef>;
                        power-domains = <&pd_gdma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 77 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x868>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 78 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x869>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 79 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x86a>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 80 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x86b>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 81 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x86c>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 82 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x86d>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 83 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x86e>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupt-parent = <&gic>;
                        interrupts = <0 84 4>;
                        xlnx,bus-width = <64>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x86f>;
                        power-domains = <&pd_adma>;
                };
 
                        interrupts = <0 14 4>;
                        #address-cells = <2>;
                        #size-cells = <1>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x872>;
                        power-domains = <&pd_nand>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
+                       iommus = <&smmu 0x874>;
                        power-domains = <&pd_eth0>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
+                       iommus = <&smmu 0x875>;
                        power-domains = <&pd_eth1>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
+                       iommus = <&smmu 0x876>;
                        power-domains = <&pd_eth2>;
                };
 
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
+                       iommus = <&smmu 0x877>;
                        power-domains = <&pd_eth3>;
                };
 
                              <0x0 0xc0000000 0x8000000>;
                        #address-cells = <1>;
                        #size-cells = <0>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x873>;
                        power-domains = <&pd_qspi>;
                };
 
                        reg = <0x0 0xff160000 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
                        broken-tuning;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x870>;
                        power-domains = <&pd_sd0>;
                };
 
                        reg = <0x0 0xff170000 0x1000>;
                        clock-names = "clk_xin", "clk_ahb";
                        broken-tuning;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x871>;
                        power-domains = <&pd_sd1>;
                };
 
                smmu: smmu@fd800000 {
                        compatible = "arm,mmu-500";
                        reg = <0x0 0xfd800000 0x20000>;
+                       #iommu-cells = <1>;
                        #global-interrupts = <1>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 155 4>,
                        mmu-masters = < &gem0 0x874
                                        &gem1 0x875
                                        &gem2 0x876
-                                       &gem3 0x877 >;
+                                       &gem3 0x877
+                                       &usb0 0x860
+                                       &usb1 0x861
+                                       &qspi 0x873
+                                       &lpd_dma_chan1 0x868
+                                       &lpd_dma_chan2 0x869
+                                       &lpd_dma_chan3 0x86a
+                                       &lpd_dma_chan4 0x86b
+                                       &lpd_dma_chan5 0x86c
+                                       &lpd_dma_chan6 0x86d
+                                       &lpd_dma_chan7 0x86e
+                                       &lpd_dma_chan8 0x86f
+                                       &fpd_dma_chan1 0x14e8
+                                       &fpd_dma_chan2 0x14e9
+                                       &fpd_dma_chan3 0x14ea
+                                       &fpd_dma_chan4 0x14eb
+                                       &fpd_dma_chan5 0x14ec
+                                       &fpd_dma_chan6 0x14ed
+                                       &fpd_dma_chan7 0x14ee
+                                       &fpd_dma_chan8 0x14ef
+                                       &sdhci0 0x870
+                                       &sdhci1 0x871
+                                       &nand0 0x872>;
                };
 
                spi0: spi@ff040000 {
                        compatible = "xlnx,zynqmp-dwc3";
                        clock-names = "bus_clk", "ref_clk";
                        clocks = <&clk125>, <&clk125>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x860>;
                        power-domains = <&pd_usb0>;
                        ranges;
 
                        compatible = "xlnx,zynqmp-dwc3";
                        clock-names = "bus_clk", "ref_clk";
                        clocks = <&clk125>, <&clk125>;
+                       #stream-id-cells = <1>;
+                       iommus = <&smmu 0x861>;
                        power-domains = <&pd_usb1>;
                        ranges;